JP2000010856A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller which can be made small-sized by the reduction of the area of a semiconductor chip, etc., and flexibly adaptive to differences of control over a memory. SOLUTION: An address data controller 12 and an address data path part 13 which perform address generation are constituent elements common to status generators 11a to 11n which generate variation information on addresses when the addresses are generated. An SDRAM controller 14 is equipped with an SDRAM command memory 141, which is stored previously with commands for controlling an SDRAM 5, etc., according to kinds of address generation. The commands stored in the SDRAM command memory 141 are read out according to the variation information (control signal) on the addresses from the data path controller 12 and the SDRAM controller 14 controls the SDRAM 5, etc., according to the read commands.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a synchronous DR.
The present invention relates to a memory control device that controls a semiconductor memory such as an AM (hereinafter, referred to as an SDRAM) or a DRAM.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus for image compression or image decompression such as MPEG (Motion Picture Experts Group) has a large capacity of image data to be handled. And a memory controller for controlling these memories and writing and reading data.

As this type of memory control device, for example, the one shown in FIG. 13 is known. As shown in FIG. 13, this memory control device controls the request / response controller 1, the address generation unit 2, and the SDRAM 5
It comprises a DRAM controller 3, a register 4, and the like. The address generation unit 2 includes a PF address generation unit (pixel filtering address generation unit) 2a, MC
(Motion compensation) address generator 2b,... FIFO (first-in first-out) address generator 2n
And so on.

In the memory control device having such a configuration, when the request / response controller 1 receives a request to read / write data from / to the SDRAM 5, the request / response controller 1 checks the priority, and a request having a higher priority than the request signal is received. If not, the request signal is accepted. When the request signal is received as described above, the address generators 2a to 2n corresponding to the request signal are selected, and the selected address generators 2a to 2n execute the address calculation according to the request signal. Outputs from the addresses calculated by the address generators 2a to 2n are controlled by, for example, a tri-state buffer (not shown). The SDRAM controller 3 receives addresses from the address generation units 2a to 2n and performs predetermined address control on the SDRAM 5.

Here, the SDRAM controller 3 is controlled by a hardware sequencer. In addition, the SDRAM controller 3 performs pre-charging (Pre-ch) at a page boundary (portion where a row address changes) or at the end of data transfer.
arge), the memory chip 2
One bank is precharged.

[0006]

In such a conventional memory control device, the number of address generation units 2a to 2n for performing address calculation based on a request signal from the outside is required in addition to the number of address generation types. , Each address generation unit 2
a to 2n are respectively composed of similar resources such as adders and counters. Therefore, the address generators 2a to 2a
When the number of n is as large as, for example, 10, the resources are increased and the size is increased. In particular, when the memory control device is configured by an integrated circuit, the area of the semiconductor chip is increased. Was desired.

Further, in the conventional memory control device, it is necessary for the SDRAM controller 3 to control the SDRAM 5 according to the type of address generation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device which can be miniaturized by reducing the area of a semiconductor chip and can flexibly cope with a difference in memory control.

[0009]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, the invention according to claim 1 is
A memory controller that generates an address of a memory in response to a request from the outside and controls the memory so as to perform a data read / write operation on a memory cell specified by the generated address. A plurality of status generators are provided for each type of generation, and when receiving the type of address generation in response to an external request, generate address variation information when generating an address according to the received type. Means, address generation means for generating an address in response to the external request based on the address fluctuation information generated by the status generation means, and an address generation type corresponding to the type of address generation. A data read / write operation for a memory cell of the memory specified by the address generated by the address generation means. A control command storage means for storing a plurality of control commands related to the control in advance, and a control command for reading one of the plurality of control commands stored in the command storage means in accordance with fluctuation information from the status generation means. Reading means.

According to a second aspect of the present invention, in the memory control device according to the first aspect, a command for controlling an operation of the plurality of status generating units is added to the control command stored in the control command storage unit. I did it.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First, an outline of the configuration of the memory control device according to this embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the overall configuration of a memory control device according to an embodiment of the present invention, together with a memory to be controlled, and is an example applied to an MPEG image processing device.

As shown in FIG. 1, the memory control device includes a request / response controller 1 and a status generator 1
1, a data path controller 12, an address data path unit 13, an SDRAM controller 14, and a register 4.
It is configured to control M5. In this memory control device, each component is integrated on a chip.

In this memory control device, the status generator 11 has a plurality of status generators 11a to 11n that operate for each type of address generation. Then, at the time of address generation, one of the plurality of status generators 11a to 11n generates address variation information according to the type of the address generation, and based on the generated address variation information, The data path controller 12 and the address data path unit 13 generate an address according to the type. Therefore, the data path controller 12 and the address data path unit 13 are common components of the status generators 11a to 11n.

Further, in this memory control device, the SDR
The AM controller 14 outputs the address generated by the address data path unit 13 to the SDRAM 5,
Data read / write operation is performed on a memory cell of the SDRAM 5 specified by the address.

Next, a detailed configuration of each section of the memory control device will be described below with reference to the drawings. request/
The response controller 1 receives a request to read or write data from or to the SDRAM 5 from the outside, and when there are a plurality of requests, sends an internal request to the status generation units 11a to 11n in accordance with a preset priority. It is configured to output to the controller 12.

The register 4 is electrically connected to the outside,
In addition, a numerical value required for address calculation can be set from the outside as described later. The status generation unit 11
As shown in FIG. 1, the PF status generator (pixel
Filtering status generator) 11a, MC status generator (motion compensation status generator) 11b,.
A FIFO status generator (first-in first-out status generator) 11n; The status generators 11a to 11n correspond to types of address generation such as pixel filtering and motion compensation.
Is selected in response to a request signal from the user.
Then, at the time of address generation, each of the status generators 11a to 11n generates an address change state (status signal) as described later, and notifies the data path controller 12 of the generated status signal of the address. Is configured.

Next, the case of the PF status generator 11a will be described as an example of the address status generation in the status generation unit 11. For example, MPEG
(Motion Picture Expert Gr
pixel filtering (Pixel Fil), which is adopted in “out” and performs a predetermined filtering process on each pixel.
tering) or motion compensation (Motion Co
In the present embodiment, the processing unit of the empension is performed in units of 8 × 8 macroblocks as shown in FIG. 2, and the data transfer to the SDRAM 5 is performed in a block of 4 × 4 as shown in FIG. Each time, the data is stored in the memory cell. The 8 × 8 macro block is used because the data bus width is set to 16 bits and the field unit is used, and may be an ordinary 16 × 16 macro block.

Here, each numerical value in FIG.
Indicates the address within For this reason, if the data crosses the boundary of the block (the thickly drawn boundary line separating the blocks in FIG. 2) during the transfer of the data, the address value changes not sequentially but discontinuously. For example, FIG.
As shown in (1), when data transfer crosses blocks in the horizontal direction, the address value changes by "13", and when data transfers crosses blocks in the vertical direction, the address value changes by "20".

The data transfer area (region: R
Also, the address value changes discontinuously even in the case of the change of the (egion). In this case, the following two statuses can be considered, and this point will be described with reference to FIG. FIG.
FIG. 4 is a diagram schematically illustrating a relationship between a real space of an image and a data transfer area. (A) Small Region (Small Region) A small region is a region where there are less than four consecutive address data in a data transfer region (when the CAS latency is 2, and when the CAS latency is 3, the region is continuous). Address data is less than 5), and the areas “R0” and “R4” in FIG. 3 correspond to the small area. (B) Large Region (Large Region) A large region is a region in which four or more consecutive addresses have data in a data transfer region (CAS latency is 2).
In the case of (3), when the CAS latency is 3, there are five or more data of consecutive addresses), and the region “R” in FIG.
“1” and “R5” correspond to the large area.

The statuses generated by the PF status generator 11a when generating addresses are summarized as shown in the table of FIG. As shown in the table of FIG. 4, the status includes the horizontal region end (Horizonta).
l Region End), Horizontal Block B
oundary, Vertical Block Boundary (Vertical Block Boundary)
y), Next Region
n), Set Small Region (Set Sma
II Region), Set Large Region (Set Large Region), Initialize Address (Initialize Addresses)
s), and their contents are as shown in FIG.
To explain an example of this content, in the case of the horizontal region end, when the data transfer position reaches the end of the region in the horizontal direction, it becomes active, and this is notified to the data path controller 12.

Next, the configuration of the data path controller 12 will be described with reference to FIGS. As shown in FIG. 1, the data path controller 12 receives a status signal corresponding to the type of the address generation from one of the status generators 11a to 11n at the time of generating the address. The address data path unit 13 is configured to control the address data path unit 13 and the like so that the address data path unit 13 generates a predetermined address according to an external request based on the address.

The data path controller 12 is, as shown in FIG.
21, initial address calculation unit 122, control signal generation unit 123, and status generation unit controller 124
It is composed of

The offset address calculator 121 calculates the value of the base address set in the register 4 by, for example, 32
The value is multiplied and output to the adder 139 of the address data path unit 13 as an offset address.

The initial address calculation unit 122 calculates an initial value of an address at the start of data transfer based on an external request, and transfers the calculated initial value to a register (Reg11) of the address data path unit 13. Is configured. For example, in the address calculation of pixel filtering, the head address of each region is calculated.

The control signal generation section 123 transmits the status signals sent from the status generators 11a to 11n and the nop check flag from the SDRAM controller 14 (NO shown in bits 9 to 11 in FIG. 10).
A control signal for controlling the address data path unit 13 is generated based on the P Check Flag, and the generated control signal is output to the instruction memory pointer 130 of the address data path unit 13.

It should be noted that the above-mentioned nop check flag is used by the status generators 11a to 11a during an initial process and a small region jump process described later.
11n etc. are temporarily in a non-operation state (Non-Opera)
The flag is a flag indicating the timing when the timing is set to “t.

The control signals generated by the control signal generator 123 include an address generation start signal, a first addition signal, a second addition signal, an address initial value set signal, and an address generation pause signal. Will be described.

The address generation start signal is a control signal for starting address generation, and is stored in the SDRAM command memory 141 of the SDRAM controller 14 (the control command of bit 3 in FIG. 10).

The first addition signal is a control signal for instructing to add "1" to the current address value. The second addition signal is a control signal for instructing to add a value other than the default value to the current address value. For example, in the table of FIG. 4, when the status is the horizontal region end, 4 is added, and when the status is the horizontal block region, 13 is added.

The address initial value set signal is a control signal for setting an initial address value. In the case of pixel filtering described above, this signal is active when jumping to each region.

Address generation suspension signals (nop 1 to n
op4) is a control signal for temporarily stopping generation of an address in the address data path unit 13. This signal is determined by the number of data at consecutive addresses and the manner of issuing a control command to the SDRAM 5. The address generation suspension signals (nop1 to nop4)
The generation of the address is stopped for 1 to 4 cycles in accordance with the signal. For example, in the case of the small area, the generation of the address in the address data path unit 13 is stopped for one cycle.

In this embodiment, nop1 to nop4 are used as the address generation temporary stop signals. However, it is sufficient to increase the number of nop5 and nop6 in accordance with the cycle in which the address is to be stopped. With this setting, it is possible to cope with various CAS latencies (cycles required from outputting an address to outputting data in an SDRAM).

[0033] The status generation control unit 124
A status generation control signal for controlling the operation of each of the status generators 11a to 11n is generated by a status generation start signal (control command of bit 3 in FIG. 10) from the M controller 14 and the like, and the generated status generation control signal is It is configured to supply to the status generators 11a to 11n.

When the status generation control signal is active, each status generator 11a to 11n operates. The status generation control signal becomes active in response to a status generation start signal from the SDRAM controller 14, and becomes an address generation suspension signal (nop
When (1) to (4) are active, they become inactive. The transfer cycle is counted in the block, and when the count value becomes 0, the status generation control signal is deactivated.

Next, the configuration of the address data path section 13 will be described with reference to FIGS. As shown in FIG. 1, the address data path unit 13 determines a read address of the instruction memory 131 based on a control signal sent from the data path controller 12, and based on the read instruction, an address of the SDRAM 5 ( (Physical address) is generated (calculated).

Specifically, the address data path section 13 includes an instruction memory pointer 130 and an instruction memory 1 as shown in FIG.
31, an instruction decoder 132, a plurality of registers (Reg20 to Reg27), and a register (R
eg10), a register (Reg11), a register selection switch 136, a register selection switch 137,
It comprises an adder 138 and an adder 139.

Instruction memory pointer 13
“0” designates an address of the instruction memory 131 based on a control signal from the data path controller 12. Instruction memory 1
For example, an instruction as shown in FIG. 7 is stored in 31. An example of specific data of this instruction is shown in FIG.
This will be described later.

When the instruction data stored in the instruction memory 131 is read by specifying the address of the instruction memory pointer 130, the instruction decoder 132 decodes (decodes) the read instruction data, and decodes the instruction data. The instruction data is output to the register selection switches 136 and 137.

Each of the registers (Reg20 to Reg27) is composed of 8 bits.
0 to Reg 27) are set (stored) with constant values required for generating addresses. The constant value is previously set in the register 4 at the time of initialization, and when a request is accepted by the request / response controller 1, the register (Reg20 to Reg2) is responded to the request.
7).

The register (Reg11) is composed of 21 bits, and stores the initial address (initial value address) calculated by the initial address calculation unit 122. For example, when transferring data relating to pixel filtering, the head address of each line is stored.

The register (Reg10) is composed of 21 bits, functions as an accumulator (accumulator), and stores the addition result of the adder 138.
The register selection switch 136 is configured to select one of the registers (Reg20 to Reg27) based on the output data from the instruction decoder 132. Therefore, the content stored in the selected register is supplied to one input side of the adder 138.

The register selection switch 137 is a register (Reg10) or a register (Reg1) based on the output data from the instruction decoder 132.
It is configured to select one of the registers 1). Therefore, the content stored in the selected register is supplied to the other input side of the adder 138.

The adder 138 is connected to the register selection switch 1
Register selected at 36 (Reg20 to Reg27)
Is added to the content stored in one of the registers (Reg10) or the register (Reg11) selected by the register selection switch 137, and the addition result is added to the adder 139. Is output to the register (Reg10).

The adder 139 calculates the addition result (relative address) of the adder 138 and the offset address calculator 121.
SDRA by adding the offset address calculated in
The address (physical address) of M5 is calculated, and the result of the addition is output to the SDRAM controller 14.

In the address data path section 13 described above, the value of the initial address is stored in the register (Reg11) and the offset address is supplied to the adder 139. However, the offset address is supplied to the register (Reg11). If the sum of the value and the initial address value is stored, the adder 139 can be omitted.

Next, the instructions stored in the instruction memory 131 will be described with reference to FIG. At each address of the instruction memory 131, FIG.
As shown in (1), one of the registers (Reg10) and the register (Reg11) is selected, and one of the registers (Reg20-Reg27) is selected. The instruction to add the value is stored. For example, at the first address, "ADD Select R11 Select
R20 "is stored. The contents of this instruction are “register (Reg11) and register (Reg2).
0), and add the contents stored in the selected registers. "

As described above, the instruction memory 13
1 is specifically composed of data as shown in FIG.
This will be described with reference to FIG.

This instruction data is composed of 16 bits as shown in FIG. This instruction data is
As shown in FIG. 8, an operation code formed by upper bits 12 to 15 and instructing addition or the like, and a register (Reg) formed by bits 8 to 11 are provided.
10) or a register (Reg11), a register selection instruction formed of bits 4 to 7 to select any one of the registers (Reg20 to Reg27), and a bit 1 (NOP Done) for terminating the nipping operation of the address data path unit 13 formed by the above operation and the read address of the instruction memory 131 formed by bit 0 when the nipping operation of the address data path unit 13 is performed.
Increment (NO
P Increment). For example, when the operation code is “addition (Add)”, the data in the upper bits 12 to 15 becomes “0001”.

As shown in FIG. 7, at addresses 32 to 35 of the instruction memory 131,
Data for NOP operation is stored. When the NOP operation signal for two or more cycles becomes active (any of the above-mentioned signals nop2 to nop4), the data of the corresponding address of the instruction memory 131 (for example, address 32 in the case of the signal nop4) is read out and read. Since “NOP Increment (see FIG. 8)” of bit 0 of the output data is active, the read address of the instruction memory 131 is incremented. During this time, a NOP cycle (dead cycle) occurs. And finally one
The data at the address 35 corresponding to the cycle NOP is read out, and bit 1 of this data is set to “NOP Done (FIG. 8).
) Is described, the NOP cycle ends.

Next, the configuration of the SDRAM controller 14 will be described with reference to FIGS. This S
The DRAM controller 14, as shown in FIG.
A RAM command memory 141 is provided, and a command stored in the SDRAM command memory 141 is read out.
The SDRAM 5 and the data path controller 12 are controlled based on the read command.

The SDRAM controller 14 is, as shown in FIG.
It comprises a read address generator 142, an SDRAM command memory 141, an address selector 143, and a synchronization (synchronization) unit 144.

The SDRAM command memory read address generator 142
41 is read from the data path controller 1
2 in response to a command.

The SDRAM command memory 141 has S
Command data for controlling the DRAM 5 and the like are stored, and the command data is written from an external host computer or the like at the time of initialization. S
Command data stored in the DRAM command memory 141 will be described later.

When the address selector 143 receives the physical address from the adder 139 of the address data path section 13, the address selector 143 converts the row address, the column address and the like from among the received physical addresses to the SDRAM.
The data is selectively output based on bits 4 to 8 of the data stored in the command memory 141.

The synchronizing section 144 has the SD
SDRA read from RAM command memory 141
The control signal of M5 and the SDRAM address selected by the address selector 143 are output to the SDRAM 5 in synchronization with the clock of the SDRAM 5. The control signals output to the SDRAM 5 include a write enable signal (WEN) for writing data and a column address strobe signal (CAS) for outputting a column address, as shown in FIG.
N), a row address for outputting a row address
There are a strobe signal (RASN) and a chip select signal (CSN) for chip selection.

When data stored in the SDRAM command memory 141 is read out, the bit 3 shown in FIG. 10 and the commands of bits 9 to 11 shown in FIG. It outputs to the controller 12 and the status generators 11a to 11n.

Next, an example of command data stored in the SDRAM command memory 141 will be described with reference to FIG. This command data is composed of 16 bits as shown in FIG. The command data includes an SDRAM command formed of upper bits 12 to 15 for controlling the SDRAM 5;
A NOP check flag formed by bits 9 to 11 and indicating the timing at which NOP occurs, a selection signal (selected command) formed by bits 4 to 8 for selecting a control command of the SDRAM 5, and a control command for performing various controls It is composed of

The command data will be described in detail.
In the DRAM command, as shown in FIG. 10, bit 12 is a write enable (Write Enable).
Bar), bit 13 is a column address strobe (Column Address Strobe), and bit 14 is a row address strobe (Row Ad).
dress Strobe) and bit 15 is a chip select (Chip Select).

As shown in FIG. 10, among the selection signals for selecting the control command of the SDRAM 5, bit 4 is an active command (Active Command) and bit 5 is a next bank active command (Nex).
t Bank Active Command), bit 6 is a read / write command (Read / Write)
Command), bit 7 is an Ignore command (I
bit 8 is a precharge command (Pre-Charge Command).
d).

As shown in FIG. 10, of the control commands, bit 0 indicates a command
Process Process D
one), bit 1 is the SDRAM command memory 141
A bit indicating the addition of the read address of the data transfer bit 2 indicates the end of the data transfer.
sfer Done), bit 3 is status generator 1
Status generation start (Status Genera) for instructing the start of operations 1a to 11n
Tion Start).

Incidentally, the SDRAM command memory 14
1 is read out in units of controlling the SDRAM 5 (hereinafter, referred to as a process) as shown in FIG.
Since the AM controller 14 controls the SDRAM 5, an outline of each process will be described below with reference to FIG. The transition between the processes is determined by a status signal (control signal) sent from the data path controller 12. (A) Idle Process This idle process P1 shifts after initialization or when data transfer ends. (B) Initial Process This initial process P2 is a process that is in an idle process state and shifts when a data transfer request is accepted. During this process, the SDRAM
The read address of the command memory 141 is incremented (see bit 1 in FIG. 10). Also, during the period of the initial process, jump to another process is prohibited until the process ends. (C) Read / Write Process The read / write process P3 jumps to issue a new read / write command when an address changes discontinuously. (D) Ignore Process In the Ignore process P4, when the address changes continuously, or when another command cannot be output due to the function of the SDRAM 5 (for example, an active command and a read / write command for the same bank of the SDRAM 5). (Cycle between commands). (E) Small region jump process This small region jump process P5 is a process for transferring data in pixel filtering when the next region is a small region. At this time, a precharge command is issued to end the transfer of the previous region. Therefore, 1
A cycle dead cycle occurs. During this process, the read address of the SDRAM command memory 141 is incremented, and jump to another process other than the end process is prohibited. (F) Large region jump process This large region jump process P6 shifts to the next region which is a large region in the pixel filtering data transfer. During this process, the read address of the SDRAM command memory 141 is incremented, and jump to another process is prohibited. (G) End Process The end process P7 is to be executed when the address generation is completed. In this process, the SDRA
Precharge both banks of M5. After this process, the process moves to an idle process.

Here, the arrows in FIG. 11 indicate the transition of each process. For example, in the initial process, it is indicated that the process can jump to any process located below the initial process.

Next, the operation of the embodiment configured as described above will be described with reference to the drawings. First, a specific example of address generation (calculation) will be described with reference to FIG. FIG.
Represents the real space of an image composed of a set of pixels, and each numerical value at each pixel position in the figure is an address (physical address) in the SDRAM 5 where the data of each pixel is stored.
Is shown. In FIG. 12, a portion designated by a white triangle indicates a block boundary, and a portion designated by a black triangle indicates a macroblock boundary. (1) Initialization (Reset) At the time of initialization or reset, data corresponding to an external request is stored in the instruction memory 131 of the address data path unit 13 from an external host computer at this time, for example. 7 is stored. (2) Acceptance of external request When the request / response controller 1 receives a request signal for pixel filtering from an external module, the request / response controller 1 confirms that there is no request having a higher priority than this request.
The PF status generator 11a and the data path controller 12 are notified of the request as an internal request. (3) Start of Status Generation and Setting of Offset Address Upon receiving the internal request, the data path controller 12 outputs a signal for enabling the PF status generator 11a. The data path controller 12 outputs an address (offset address) indicating the start of data transfer.

For convenience of explanation, the adder 1 shown in FIG.
39 is not used, and its offset address is stored in the register (Reg11) of FIG. In this case, "7" shown in FIG. 12 is stored in the register (Reg11) as an offset address as shown in FIG.

Next, when the data path controller 12 outputs a control signal to the instruction memory pointer 130, the instruction memory pointer 130 specifies the address “0” of the instruction memory 131 based on the control signal. Therefore, the address “0” of the instruction memory 131 shown in FIG.
Is read out and output to the instruction decoder 132. Instruction decoder 1
32 decodes the instruction data and outputs it to the register selection switches 136 and 137.

Here, the instruction memory 131
As shown in FIG. 7, the instruction data stored in the address “0” of the register “Reg.
g20), and add the contents stored in the two selected registers. " Therefore, the selection switch 136
Selects the register (Reg20), while the selection switch 137 selects the register (Reg11). Therefore, “7” stored in the register (Reg11) and “0” stored in the register (Reg20) in advance are selected. Are added by the adder 138, and the result of this addition, "7"
Is output to the adder 139 and the register (Reg)
10). (4) Operation at Block Boundary After that, as shown in FIG. 12, the PF status generator 11a informs the data path controller 12 that the current pixel position is at the boundary of the block indicated by a white triangle. Notice. Upon receiving this status, the data path controller 12 generates a control signal for determining a read address of the instruction memory 131 of the address data path unit 13 and outputs the generated control signal to the instruction memory pointer 130.

In this case, since the read address of the instruction memory 131 is “2”, the instruction data of the address “2” is read and decoded by the instruction decoder 132. This allows
The selection switch 136 selects the register (Reg24), while the selection switch 137 selects the register (Reg10).
Is selected, “7” stored in the register (Reg11) and “13” stored in the register (Reg24) are added by the adder 138, and “20” as the addition result is added to the adder 138. 139 and stored in the register (Reg10). (5) When the address changes continuously Since the address changes continuously between address "21" and address "23", the PF status generator 11a
Does not output any status. The data path controller 12 outputs a control signal for adding “1” to the current address to the instruction memory pointer 130 during that period. As a result, the instruction data at the address “1” in the instruction memory 131 is read out and decoded by the instruction decoder 132. As a result, the selection switch 136 sets the register (R
eg21), while the selection switch 137 selects the register (Reg10).
10) stored in the register (Reg2)
“1” stored in 1) is added by the adder 138, and the addition result “21” is output to the adder 139 and stored in the register (Reg10).
Such an operation is continued until the address “23” is calculated. (6) Operation at Macroblock Boundary Then, as shown in FIG. 12, when the calculation of the address “23” is completed, the PF status generator 11a outputs a signal indicating that the current pixel position is at the macroblock boundary. Output to the data path controller 12. Upon receiving the signal, the data path controller 12 generates a control signal for determining a read address of the instruction memory 131 of the address data path unit 13, and transmits the generated control signal to the instruction memory pointer 130 of the address data path unit 13. Output.

In this case, since the read address of the instruction memory 131 is "3", the instruction data of the address "3" is read and decoded by the instruction decoder 132. This allows
The selection switch 136 selects the register (Reg23), while the selection switch 137 selects the register (Reg11).
Is selected, the address “7” stored in the register (Reg11) and “4” stored in the register (Reg23) are added by the adder 138, and the addition result “11” is added. Is output to the register 139 and stored in the register (Reg11). As a result, the value of the register (Reg11) is updated from "23" to "11". (7) Transition to the next macroblock After that, the calculated value of the address is changed to the address "6" shown in FIG.
At the position "3" (the boundary position of the macroblock in both the vertical and horizontal directions), the PF status generator 11a notifies the data path controller 12 of a signal indicating that the calculation of the address shifts to the next macroblock. . The data path controller 12 calculates the offset address again, and the calculated offset address is stored in the register (Reg11) of the address data path unit 13. The offset address at this time is “68”.

Upon receiving the above notification, the data path controller 12 generates a control signal for determining a read address of the instruction memory 131 of the address data path section, and outputs the generated control signal to the instruction memory pointer 130. .

In this case, since the read address of the instruction memory 131 is “0”, the instruction data of the address “0” is read and decoded by the instruction decoder 132. As a result, the selection switch 136 selects the register (Reg20), while the selection switch 137 selects the register (Reg11). Therefore, “68” stored in the register (Reg11) is stored in the register (Reg20). The added “0” is added by the adder 138, and the added result “68” is output to the adder 139 and stored in the register (Reg10). (8) End The above operation is repeated, and each of the hatched regions (R0, R1, R2) extending over the four macroblocks shown in FIG.
When the transfer of all 81 data of (2, R3) is completed, the data path controller 12 turns off the enable signal of the PF status generator 11a. This allows
The operation of the PF status generator 11a is stopped.

Next, a specific example of the operation of the SDRAM controller 14 will be described in the case of data transfer in pixel filtering shown in FIG. (1) Initialization At initialization, an external host computer
SDRAM command memory 141 of M controller 14
(See FIGS. 1 and 9), instruction data as shown in FIG. 10 is stored. These data are stored in an SDRAM 5 for controlling the SDRAM 5, as shown in FIG.
It is composed of a command, a NOP check flag, a selection signal (selected command) for selecting a control command of the SDRAM 5, and a control command for performing various controls. At the time of initialization, the read address of the SDRAM command memory 141 points to the idle process P1 (see FIG. 11). (2) At the start of transfer When the SDRAM controller 14 is notified by the data path controller 12 that the transfer of data starts,
The process shifts from the current idle process P1 to the next initial process P2. (3) Initial Process When the process proceeds to the initial process P2, four pieces of instruction data relating to the initial process P2 shown in FIG. 11 are sequentially read from the SDRAM command memory 141, and the following processes are performed.

First, as shown in FIG. 9, when a physical address (in this case, "7") from the address data path section 13 is input to the address selector 143, a row address of that address is selected and output. The row address is output from the synchronization section 144 in a form synchronized with the clock of the SDRAM 5. The row address in this case is "0". At this time,
A row address strobe signal (RASN) for controlling the output of the row address is output.

Then, according to the rules of SDRAM 5, an Ignore command which is a command that does nothing for one cycle until the first column address is output (however, C
If the AS latency is 3, two cycles are required).

Further, the synchronization section 144
Output the column address of the first physical address. In this case, the column address is "7"
Becomes At this time, a column address strobe signal (RASN) for outputting a column address is output.

Thereafter, the bank "1" opposite to the current bank of the SDRAM 5 (in this case, bank "0") is activated. At this time, if the next address is a continuous address "8", data of address "8" can be written at the same time as outputting the bank active command in this cycle. In this case, the next address is "8". 20 ", it is necessary to stop address generation for one cycle.

Therefore, the SDRAM controller 14
The fact is notified to the data path controller 12. The data path controller 12 having received this notification outputs an instruction to the address data path unit 13 to shift to the NOP cycle. In addition, the data path controller 1
2 outputs a command to the PF status generator 11a to pause for one cycle. (4) Transition to read / write process As described above, since the address changes discontinuously from "7" to "20", a read / write command is issued, and a new column is issued from the synchronization unit 144. The address "20" is output. (5) Transition to the Ignore Process Since the next address is a continuous address of "21" and the previous address "20", there is no need to output a new read / write command, and the process proceeds to the Ignore process P4. This ignition process is continued until addresses "21" to "23" are output. (6) Transition to Read / Write Process The next address is “11”, which is discontinuous with address “23”. Therefore, the process shifts to the read / write process P3 again. Such processes (4) to (6) are repeated up to the address “63”. (7) Transition to large region jump process The address following address "63" is "68". At this time, the pixel position of the address “68” is included in the region R1, and is a bank opposite to the region R0. The row address of the opposite bank has already been specified. In the region R1, there are four consecutive addresses such as addresses "68" to "71". Therefore, in this case, the process shifts to the large region jump process P6.

When the process shifts to the large region jump process P6, first, this region (region R in FIG. 12)
The data of the first address "68" in 1) is read or written (see FIG. 11).

Next, the bank (in this case, bank "0") in which the region R0 has been performed up to (6) is precharged. Since the addresses are continuous, the data of the next address “69” can be read and written even while the precharge command is issued. Since the next address "70" is also continuous, an Ignore command is issued because there is no need to issue a read / write command. Finally, an active command is issued to the bank “0” opposite to the current bank “1”. At this time, since the addresses are continuous (address "71"), the data at the address "71" can be read and written while the active command is issued.

However, the next address "84" is
As shown in (1), the column address is discontinuous due to a block boundary, so a new column address must be set.
Therefore, the process shifts to the read / write process P3 again. Since the address next to the address "84" is discontinuous with "72", it stays in the read / write process P3.
Since the next addresses “73” to “75” are continuous addresses, the process shifts to the Ignor process P4. These operations are repeated to read data up to address “124”. At this point, all the data in the region R1 has been read. (8) Transition to Small Region Jump Process After reading the data in the region R1, the data in either the region R2 or the region R3 is read. Which area of data is read depends on which bank stores the data of areas R2 and R3. Here, it is assumed that data is read to the region R2.

As can be seen from FIG. 12, in the region R2,
There are no more than four consecutive addresses from the beginning, such as the first address is "515" but the next address is "528". Therefore, in such a case, the process shifts to the small region jump process P5.

In the small region jump process P5, first, a bank (region R) opposite to the current bank is used.
1 bank). Thereafter, the column address of the data at the first address “515” of the region R2 is output. At this time, since the next address is discontinuous with "528", the address generation is suspended for one cycle at this time.

Next, the process shifts to the read / write process P4 to newly output the column address of the address "528". Thereafter, the read / write process P3 and the ignition process P4 are performed in the same manner as in the above (7).
Repeat. Then, after outputting the last address “535”, the process shifts to the region R3. (8) Transition to Large Region Jump Process As can be seen from FIG. 12, since the region R3 has four or more consecutive addresses from the first address, the large region jump process P is performed in the same manner as in (7) above.
Move to 6. Since the operation of this process has been described above, its description is omitted here. (9) Transition to the end process When all the output of the data address of the region R3 is completed,
Move to end process P7. This end process P
At step 7, both the bank “0” and the bank “1” of the SDRAM 5 are precharged. When this is done,
The process shifts to the first idle process P1.

As described above, in this embodiment, a plurality of status generators 11a to 11n for generating address variation information according to the type of address generation are provided by the data path controller 12 for generating addresses and the address data The path unit 13 can be shared. Therefore, in this embodiment, the number of components can be significantly reduced, so that the area of the semiconductor chip can be reduced, and the entire device can be downsized.

In this embodiment, a register (Reg11) functioning as an accumulator and a register (Reg1) storing a predetermined address for data transfer are provided.
1), a register (R
eg20 to Reg27), instruction memory 1
31 based on the fluctuation information generated by the status generators 11a to 11n, and reads out the control data of the instruction memory 131. The register (Reg10) or the register (R) is read in accordance with the read data.
eg11), one of the addresses stored in the registers (Reg20-Reg27) is selected, and the selected address and the fluctuation value are added. Therefore, at the time of address generation, at the time of initialization, control data is stored in the instruction memory 131 and registers (Reg20 to Reg2) are stored in accordance with the type of address generation.
Since the variable value can be stored in 7), there is an advantage that the type of address generation can be flexibly handled.

Further, in this embodiment, the SDR
The AM controller 14 has the SDRAM command memory 14
In the SDRAM command memory 141, a command for controlling the SDRAM 5 and the like in accordance with the type of address generation is stored in advance, and the SDRAM command memory 141 stores the command based on address fluctuation information (control signal) from the data path controller 12. The command stored in the command memory 141 is read, and based on the read command, S
The control operation of the DRAM 5 is performed. in this way,
Various control commands according to the type of address generation
Since it can be stored in the RAM command memory 141 in advance, it is possible to flexibly cope with control according to the type of address generation.

[0086]

As described above, the present invention is provided for each type of memory address generation. When the type of address generation is received in response to a request from the outside, the present invention is executed in accordance with the received type. A plurality of status generating means for generating address change information when generating an address; and an address for generating an address in response to an external request based on the address change information generated by the status generating means. Generating means, and a plurality of status generating means can share the address generating means. Therefore, in the present invention, the number of components can be significantly reduced, and the entire device can be downsized.

Further, according to the present invention, a plurality of data read / write operations corresponding to the type of address generation and related to the control of the data read / write operation with respect to the memory cell of the memory specified by the address generated by the address generation means. Is provided with a control command storage means for storing the control command in advance. For this reason, since a plurality of control commands can be stored in the control command storage means in advance, it is possible to flexibly cope with a difference in control of a memory that differs depending on the type of address generation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a memory control device according to an embodiment of the present invention, together with a memory.

FIG. 2 is a diagram showing a processing unit (macro block) of data processed by pixel filtering.

FIG. 3 is a diagram illustrating a relationship between a real space of an image and a reading range of the image.

FIG. 4 is a table summarizing status names generated when addresses are generated in a PF status generator and their contents.

FIG. 5 is a block diagram illustrating an example of a detailed configuration of a data path controller.

FIG. 6 is a block diagram illustrating an example of a detailed configuration of an address data path unit.

FIG. 7 is a diagram schematically illustrating a storage example of instruction data stored in a memory instruction memory.

FIG. 8 is a table illustrating an example of a configuration of instruction data stored in a memory instruction memory.

FIG. 9 is a block diagram illustrating an example of a detailed configuration of an SDRAM controller.

FIG. 10 is a table illustrating an example of a configuration of a command stored in an SDRAM command memory.

FIG. 11 is a diagram illustrating an example of an execution unit (process) when an SDRAM controller controls an SDRAM or the like;

FIG. 12 is an explanatory diagram for explaining the operation of this embodiment.

FIG. 13 is a block diagram showing a configuration of a conventional device.

[Explanation of symbols]

 1 Request / Response Controller 5 SDRAM 11 Status Generator 11a to 11n Status Generator 12 Data Path Controller 13 Address Data Path 14 SDRAM Controller 130 Instruction Memory Pointer 131 Instruction Memory 132 Instruction Decoder 136, 137 Register Select Switch 138, 139 Addition Unit 141 SDRAM command memory Reg10, Reg11 registers Reg20-Reg27 registers

Claims (2)

[Claims] 1. A memory control device that generates an address of a memory in response to a request from the outside and controls the memory to perform a data read / write operation on a memory cell specified by the generated address. It is provided for each type of address generation of the memory. When an address generation type is received in response to a request from the outside, address variation information is generated when generating an address according to the received type. A plurality of status generating means, an address generating means for generating an address in response to the external request based on the address fluctuation information generated by the status generating means, Data for a memory cell of the memory specified by the address generated by the address generation means. A control command storage means for storing in advance a plurality of control commands related to the control of the read / write operation; and one of the plurality of control commands stored in the command storage means, in accordance with variation information from the status generation means. A memory control device, comprising: control command reading means for reading. 2. The memory control device according to claim 1, wherein a command for controlling the operation of the plurality of status generation units is added to the control command stored in the control command storage unit. .