JPH09198355A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve processing capacity in a processor having two CPUs. SOLUTION: The processor for processing information transmitted through a common bus 12 is provided with first CPU0 (15) processing information supplied through a first bus 28 and second CPU1 (16) processing information supplied through a second bus 29. A memory 17 which stores information from either first or second CPU0 (15) or CPU1 (16), enables the other CPU to refer to pertinent information and which is connected to first and second CPU 0(15) and CPU1 (16), and a switch 23 for changing the common bus 12 to the first or second bus in accordance with requests from CPU0 (15) and CPU1 (16) are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system suitable for constituting a single processor system or a multi processor.

[0002]

2. Description of the Related Art Conventionally, a multi-processor system has, for example, one CPU and a memory, another processor element and a bus switch which operates as a master / slave, as disclosed in Japanese Patent Laid-Open No. 59-208666. Become. In a multi-processor system composed of processor elements with such a single CPU,
There is no problem as far as dedicated task processing with less disturbance, but as the processing contents required for the system such as intelligent control processing become sophisticated, database and system status management, knowledge processing system based on database and sensor information Configuration, multiple interrupt processing, multi-job function, etc. background processing system support is essential, and those processes are described in a high-level language on a high-level operating system that can support real-time multi-tasking and multi-jobs. It is common to do so.

[0003]

In the above-mentioned conventional multi-processor system, the real-time control processing, which is the main factor for speeding up, is positioned as one of the tasks supported by multi-tasking, so that the task switch, The current situation is that fine-grained tightly coupled parallel processing cannot be performed due to overhead and disturbance of the parallel processing schedule. Therefore, the supervisor system often adopts a method in which the intelligent processing system is separated from the control processing system by parallel processing by a super mini computer, but the communication between the parallel processing system and the intelligent processing system tends to be sparse. The characteristics such as decentralization of intelligent processing that requires operating system overhead to manage the local internal status of the processor, decentralization of system management, etc. are not utilized, resulting in a substantial reduction in price / performance ratio, and control processing system As the processing performance is expanded, it is difficult to expand the processing performance of the intelligent processing system and improve the communication throughput between the two systems in proportion to the expansion of the processing performance. Therefore, especially when the control loop of the control processing system is speeded up, relatively large data needs to be exchanged at high speed between the intelligent processing system and the control processing system, and the above-mentioned problem becomes a major bottleneck in the hardware configuration. The price-performance ratio will be significantly reduced.

An object of the present invention is to provide a processor capable of efficiently improving the substantial processing performance of a multi-processor system or a single processor system suitable for general-purpose processing in a well-balanced manner. It is in.

[0005]

SUMMARY OF THE INVENTION The present invention is a processor system for processing information sent via a first and a second common bus, the information processing system being provided with information supplied via a first local bus. A first CPU, a second CPU that processes information supplied via a second local bus, and information from either the first or second CPU, and the other CPU stores the information. The first for making it possible to refer to
And a memory connected to the second CPU, a first common bus, and a first CPU or a second local bus via the first local bus at the request of the first or second CPU. A first switch connected to a second CPU via
The second common bus connecting the second common bus to the first common bus
And a switch, the processor system including the switch.

Further, the present invention is a processor system for processing information sent via the first and second common buses, and a first CPU for processing information supplied via the first local bus. A second CPU for processing information supplied via the second local bus; and the first and second CPUs.
Information from one of the other CPUs and the other CPU
The first and second CPs for enabling the user to refer to the information.
The memory connected to U and the first common bus are normally connected to the first CPU via the first local bus, and the second local bus is requested at the request of the first or second CPU. Disclosed is a processor system including a first switch that connects the second CPU via a second switch and a second switch that connects a second common bus to the first common bus.

[0007]

DETAILED DESCRIPTION OF THE INVENTION The processor of the present invention provides a hardware architecture that allows two CPUs in a base processor element to operate as if they were one processor. Also, paying attention to the high independence of the control processing system and the intelligent processing system based on the database and the sensor information, the control processing system is assigned to the main processing system of the main CPU so that the control calculation is performed with other base processor elements. It is executed by tightly coupled parallel processing, and processing with strong background elements such as interrupt processing, system management, and knowledge processing is assigned to the background processing system of the main CPU and the background CPU as an intelligent processing system,
The control processing system of the main CPU is backed up. As a result, it is possible to remove the task switch overhead and the interrupt factor that disturbs the parallel processing as much as possible, and to operate two highly independent processing systems in parallel with high efficiency. The processing performance of the base processor element is doubled, and even in a multi-processor system in which a plurality of base processor elements are combined, the total processing performance of the conventional processor element is twice as high as that of the base processor element. It is possible to realize well-balanced processing performance expansion of the control processing system and the intelligent processing system corresponding to the expansion of the.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a processor of the present invention. In this figure, a base processor element (BPE) that constitutes a multi-processor system is shown.
The internal configuration of 1 is composed of two CPUs 15 and 16 (CPU 0 and CPU 1), and a dual port RAM (DPR) 1 is provided as a dedicated communication mechanism between the two CPUs 15 and 16.
7 and other base processor elements (BPE)
Two CPUs to communicate with
In order to connect to the BPE local bus 12 which is a common bus between the two, a common bus switch 24 including a multiplex bus buffer 23 which is switch-controlled by the common bus switch control circuit 22 without any conflict is provided and CP
It has a structure for performing communication processing between U15 and U16 and between base processor elements (BPE). The two CPUs 15 and 16 have local memories 18 and 20 and local I / Os 19 and 21, respectively,
Normally, it can operate independently. Also, dual port RAM (DPR) that supports communication between CPUs
The feature of 17 is that it has communication interrupt lines 32 and 33 to the CPUs 15 and 16 of each other, and uses the communication interrupt lines between the CPUs 15 and 16 with small overhead. The local memory 6 and the local I / O 7 of the base processor element are connected to the local bus 12 of the base processor element 1, and a common bus line with other base processor elements is formed. Moreover, a system bus switch 8 for connecting to the system bus 14 to which the system shared memory 9 and the system shared I / O 10 are connected is provided. The system bus switch 8 performs bus arbitration processing related to access to the system bus 14 by the arbitration line 13, uses shared resources on the system bus 14 consistently, and performs communication processing with other base processor elements. To perform parallel processing between base processor elements.

FIG. 5 shows a dual port RAM (DPR).
17 is a hardware block diagram of the dual port RAM (DPR) 17 having two Cs.
It can be regarded as a shared memory shared between the PUs 15 and 16, and is a dual port RA of the two CPUs 15 and 16.
An arbiter 60 that arbitrates access to M (DPR) by using access request signals and access permission signals of the respective processors indicated by reference numerals 77 to 80, and buses 64 and 6 from the CPU according to enable signals 75 and 76 from the arbiter 60.
Bus switch 61 for switching 5 to internal bus 66,
62, the address and control line of the internal bus 66 are decoded to decode the memory enable signal 81 and the interrupt control signal 73,
Decoder 67 for generating 74 and each CPU
Interrupt control signals 73, 7 generated by the decoder 67 to set and reset the interrupt signals 32, 33 to
4 comprises flip-flops 68, 69, etc. Characteristic dual port RAM (DP
The interrupt function for inter-CPU communication of R) is provided with a register for generating an interrupt to CPU0 and a register for generating an interrupt to CPU1 at a specific address of a dual port RAM (DPR), and at the same time, they are provided to each other's CPUs.
It is defined as an instruction register to and receives and sends an instruction and generates an interrupt at the same time. Taking the case where the CPU1 transmits an instruction to the CPU0 as an example, first, the CPU1 first sets an instruction attribute that the CPU0 wants the CPU0 to execute in its own register or the like, and sets it in the instruction register for the CPU0 on the dual port RAM (DPR) ( Interrupt register), the decoder 67 knows that the instruction register to CPU0 has been accessed by monitoring the internal bus 67 of the dual port RAM (DPR) and decoding.
An instruction register access signal pulse to 0 is sent using the access signal 73 to latch the value of the inverted output of Q (ie, the bar of Q; the same applies hereinafter) signal 70 to flip-flop 68. In the initial state, since Q is HI and the inverted output of Q is set to LO by the RESET signal 72, LO is output to Q and HI is output to the inverted output of Q in the above operation, and the CPU0 that is LO active is output. Interrupt signal 30 becomes active for CPU0.

Next, the CPU 0 that receives the interrupt refers to the instruction register to the CPU 0 again in order to obtain the instruction to be executed in its own interrupt service routine,
When the instructed instruction is read out, the decoder 67 similarly monitors the access state and outputs an instruction register access signal pulse to the CPU0 to the flip-flop 68 using the access signal 73, and HI The inverted output 70 of Q is latched and HI is output to Q.
That is, the interrupt generation line 32 to the CPU0 is made inactive. With the above-described sequence, it is possible to simultaneously execute a series of operations from generation of an interrupt to acceptance and operations related to software instruction exchange with minimum overhead.

Returning to FIG. 1, the CPU 0 in the base processor element (BPE) 1 or the bus 28 of the CPU 1
Or, select any one of 29, CPU0 and CP
The common bus switch 24 that performs bus switching control (bus switch) for outputting as the BPE local bus 12 that can be regarded as the shared bus of U1 is, as described above, the shared bus switch control circuit 22 and the multi-bus controlled by it. A plex bus buffer 23. The bus switch is controlled by CPU0 as a master and CPU1 as a CPU.
4 is simply a shared bus switch including the NOR circuit 83 and the NAND circuit 84 shown in FIG.
It is done by logic. The characteristic bus switch control sequence will be described with reference to the time chart of FIG.

First, the local buses 28 and 2 of the two CPUs
The acquisition right of 9 always exists on each CPU side, and is not infringed by DeHeiss on other buses (A and H in FIG. 2). Shared bus of CPU0 (BPE local bus 1
2) The access request is always active as shown in FIG. 2B, and the shared bus access request of the CPU 1 is always active as needed as shown in I of FIG. That is, except when the CPU 1 has acquired the shared bus, the CPU 0 side always acquires the shared bus. In the example shown in FIG. 2, the CPU 1 sends the shared bus access request 8 at a of I.
7 is output, and in response to this, when the CPU 0 finishes the instruction processing being executed at that time and becomes ready to relinquish the shared bus right, the halt acknowledge 8 is immediately issued at a in FIG. 2D.
2 is output to deactivate the CPU0 shared bus access permission signal 85 (driven by the gate 83) at a in FIG. 2E and abandon the shared bus as shown at a in FIG. 2F. . Further, the CPU0 itself enters the halt state at a in C of FIG.
Shared bus access grant signal 86 (driven by gate 84) of FIG.
CPU1 of the bus switch buffer 23 as shown in FIG.
The side is selected and the right to use the shared bus is transferred to the CPU 1. C
When it is time for PU1 to finish using the shared bus and relinquish the shared bus, the CPU1 shared bus access request 87 is deactivated as indicated by b in I of FIG.
Immediately after that, the CPU0 shared bus access permission signal 85 becomes active at b of FIG.
After the CPU0 side of the buffer 23 is selected and the right to use the shared bus is transferred to the CPU0, the halt acknowledge of the CPU0 is released at b of D of FIG. 2, and the CP is canceled at b of C of FIG.
U0 shifts from the halt state to the working state. 2G
Symbols L and L indicate actual operating states of the CPU0 and the CPU1, respectively. In order to perform the master (CPU0) and slave (CPU1) operations as described above, the CPU0 performs the bus switch while the right to use the shared bus is transferred to the CPU1 (a to F in FIG. 2B). In addition, a short time (b of B of FIG. 2B-b of FIG. 2) in which the electrical and timing characteristics of the bus are adjusted without any contradiction results in a halt state for a total time, which does not work. That is, in terms of the actual work right, the CPU 1 operates as a master. In order to prevent the halt time from becoming too long and hindering the operation of the CPU0, a mode is provided in which the shared bus usage right is transferred to the CPU0 for each data transfer. However, as described below, CPU0
As U, the CPU 1 is used as a background CPU for performing intelligent processing to support the CPU 0, and when a multi-processor configuration is adopted, distributed knowledge of the function distribution structure in base processor element (BPE) units. By adopting the base form, much necessary data can be obtained from the vicinity of itself, and most data communication can be performed by using the dual port RAM (DPR). Therefore, the rate at which knowledge information is exchanged between the base processor elements (BPE) is sufficiently higher than the rate at which the CPU0 exchanges information with other base processor elements (BPE) due to the tightly coupled parallel processing. It is small and the processing power loss of the CPU 0 according to the present invention can be regarded as negligible. Further, when the role of the CPU1 is fixed to perform the backup of the CPU processing and the system management, the operation control right of the CPU0 is assigned to the CPU1.
It can be said that the shared bus control of the present invention is suitable for the local distributed processing as described above. Next, the general operation of the processor of the present invention described above will be described in detail with reference to FIG.

In FIG. 3, it is assumed that the CPU0 performs main control calculation, the CPU1 performs intelligent processing and system management based on knowledge base (distributed type) sensor information, etc. and backs up the CPU0 in the background, and performs local distributed processing. I am assuming. Further, when the multi-processor configuration is adopted, each base processor element (BPE) performs tightly coupled parallel processing in the main and loosely coupled parallel processing in the background together with other base processor elements (BPE). I assume that. Reference numeral 35 shows a processing flow of the CPU 1 along the time axis, and reference numerals 36, 37 and 38 similarly show a processing flow of the CPU 0. The shared resource is a dual port RAM (D) which is a local shared memory between CPU0 and CPU1 in the base processor element (BPE).
PR) and system shared resources on the system bus 14 that are accessible by all base processor elements (BPEs) in a multi-processor configuration.
47, 48, 54 and 59 show communication between the CPU 0 and the DPR, and 46, 53, 56 and 58 show communication between the CPU 1 and the DPR. Similarly, 57 indicates communication between the CPU 0 and the system shared resource, 51 indicates communication between the CPU 1 and the system shared resource, and when observed from the system shared resource side, any of them is regarded as an access from the base processor element (BPE). Be done. In addition, 50 is a CPU0 that uses the interrupt function on the dual port RAM (DPR).
To the CPU 1, and 55 also indicates an interrupt to the CPU 1. Reference numeral 49 indicates a handshake situation of the shared bus access request signal from the CPU1 to the CPU0 and the corresponding shared bus access permission signal from the CPU0, and 52 indicates that the shared bus once acquired by the CPU1 is abandoned. It shows how the usage right is transferred to the CPU 0 again. Reference numerals 88 and 89 indicate access to system shared resources from other BPEs. Reference numerals 90 and 91 indicate that local sensor information, which is external information, is taken in during the processing of the CPU 1 as a part of the knowledge. Similarly, reference numerals 92 and 93 indicate shared sensors shared by other BPEs. It shows that the information is taken in by the CPU0 and the CPU1. Regarding the processing contents of the CPU0 and the CPU1, the CPU0 is the main processing system, and in order to control a part of the intelligent mechanical system, for example, the arm part of the humanoid intelligent robot, together with the CPU0 of the other base processor element (BPE). It is assumed that a large number of necessary control operation tasks are shared so that the degree of parallelism is improved as much as possible, and that high-efficiency tightly coupled parallel processing 36b, 38b is executed, and after requesting processing to an auxiliary processor such as an arithmetic processor. CPU1 as a background processing system when there is a vacant time, a vacant time that occurs during synchronous processing with another base processor element (BPE), and a processing request due to an interrupt from another base processor element BPE or CPU1 and shared resources Jointly with 36
a, 38a performs intelligent processing, system management, etc., and
An intelligent processing system is configured together with the processing 35 of PU1. The intelligent processing system executed by this base processor element (BPE) holds a group of information about a further part of the arm part, for example, a muscle part as a database, and local sensor information is also closely related to it. Is taken in as perceptual information, and based on the local function distributed database constructed by them, the intelligence processing regarding the muscle part is executed, and the whole control calculation executed in the main processing system is backed up.

In the system based on the above assumption, the processing flow of the CPU0 and CPU1 shown in FIG. 3 will be briefly traced. First, the CPU0 and the CPU1 respectively execute the processes 36 and 35 shown in FIG. 3, and the CPU1 immediately needs to communicate with the CPU0, and at 39, writes a communication message in the dual port RAM (DPR) to communicate. An operation 46 of writing the contents into the instruction register to the CPU0 as an instruction is performed. Correspondingly, CPU0
Interrupt 50 occurs, the dual port RAM (DPR) is accessed in the background processing system of the CPU 0, and communication 47 of necessary information is performed. At 40,
CPU0 is a dual-port RAM (DP) that flows shared data between CPUs that does not need handshaking.
R), dual port RAM (DPR)
I read it from. Various sensor information is also processed sequentially by interruption, with the sensor side as the main body,
It is referred to in the program as needed and incorporated as a part of knowledge. Next, since the CPU 1 communicates with another base processor element (BPE), it becomes necessary to communicate with the system shared resource. At 49, the right to use the shared bus (BPE local bus) 12 is acquired, and at 41 At the time point, communication 51 with the system shared memory is performed, and when the communication is completed, the right to use the common bus is transferred to the CPU 0 again at 52. Meanwhile, CPU0 is kept in the halt state 37, 52
When the halt state is released by, the process 38 following the process 36 is continued. After that, at the time of 42, CPU1
And the dual port RAM (DPR) performs shared data draining communication between CPUs, and at 43, handshake data communication with instructions is executed from CPU0 to CPU1 in the same manner as 39. In 44, communication 57 between the CPU 0 and the system shared resource is performed, and the contents of communication include communication related to intelligent processing in the background processing 38a and communication of tightly coupled parallel processing data related to control calculation in the main processing 38b. It is performed, and there is no influence on the processing and operation of the CPU 1 at that time. 45 is C
Dual port RAM (DPR) of PU0 and CPU1
It shows that the drooping communication with the arbiter is being performed at approximately the same time, but the arbiter 60 performs the arbitration control appropriately to perform the communication processing without any hindrance to the mutual processing and operation.

When the intelligent processing system and the control processing system backed up by the intelligent processing system by the local distributed database are realized by the processor of the present invention, most of the intelligent processing is based on the dual port RAM (DPR). CPU in processor element (BPE)
It is sufficient to access the shared resources of the system in order to exchange the processing result and the intelligent processing result of other base processor elements (BPE) once in a while. Therefore, it is natural between the communication nodes in the system. In addition to achieving the best communication throughput, the control processing system and the intelligent processing system can operate almost completely independently in parallel, so that the processing performance can be surely doubled. Further, by adding BPEs, the processing performance of the intelligent processing system and the processing performance of the control processing system increase in proportion to each other, and it is possible to always provide the processing performance in which both are balanced.

According to an embodiment of the present invention, a basic processor element (base processor element: BPE) of a multi-processor system or a single-processor system is composed of two CPUs, Dual port RAM (DPR) with interrupt function
And when observed from the outside by a master / slave operation, it looks like a single CPU and is connected with a common bus that can be used in common by both CPUs, and has a highly independent main processing system and background processing system. 2 C separated
The PU is responsible for each, and local information exchange between the two CPUs is performed via the dual port RAM (DPR).
Communication with the processor element (BPE) is performed via a common bus (BPE local bus) via system shared resources on the system bus, thereby substantially doubling the performance of the BPE.

Further, when a processor of the present invention is used to construct a multi-processor system, the database of the background processing system is functionally distributed to each BPE.
By having it as a unit, most of the background processing system does not need to be closed by local communication in the processor and frequently communicate with other processors, thereby optimizing the communication throughput between communication nodes. Therefore, highly efficient parallel processing can be naturally performed in both the main processing system and the background processing system without significantly affecting the tightly coupled parallel processing executed in the main. Furthermore, by adding the processor of the present invention,
It is always possible to improve the processing capacity in a balanced manner in both the main processing and background processing systems.

[0018]

As described above, according to the present invention, the substantial processing performance of a multi-processor system or a single processor system suitable for general-purpose processing can be efficiently improved in a well-balanced manner. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing an internal structure of a base processor element in a processor of the present invention and a part of a multi-processor system according to the internal structure.

FIG. 2 is a diagram showing a common bus (BPE local) switch sequence between two CPUs in a base processor element which constitutes the present invention.

FIG. 3 2 CPUs in the base processor element
It is a figure which shows the flow of the process between.

FIG. 4 is a basic logic diagram of a shared bus switch that constitutes the present invention.

FIG. 5 is a logic block diagram of a dual port RAM constituting the present invention.

[Explanation of symbols]

 1 Base Processor Element (BPE) 8 System Bus Switch 14 System Bus 15 CPU0 (Master) 16 CPU1 (Slave) 17 DPR Logic 24 Common Bus Switch 32 Instruction Interrupt Line to CPU0 33 Instruction Interrupt to CPU1 Line 73 Flip-flop for interrupt generation to CPU0 74 Flip-flop for interrupt generation to CPU1 85 CPU0 common bus access permission signal 86 CPU1 common bus access permission signal

Claims (2)

[Claims] 1. A processor system for processing information sent via a first and a second common bus, comprising: a first CPU processing information supplied via a first local bus; A second CPU for processing information supplied via the second local bus; and a second CPU for storing information from either the first or second CPU and allowing the other CPU to refer to the information. The memory connected to the first and second CPUs and the first common bus are connected to the first CPU or the second CPU via the first local bus at the request of the first or second CPU.
A first switch connected to the second CPU via the local bus of the second switch, and a second switch connecting the second common bus to the first common bus.
A switch and a processor system including. 2. A processor system for processing information sent via a first and a second common bus, comprising: a first CPU for processing information supplied via a first local bus; A second CPU for processing information supplied via the second local bus; and a second CPU for storing information from either the first or second CPU and allowing the other CPU to refer to the information. A memory connected to the first and second CPUs and a first common bus are always connected to the first CPU via the first local bus, and are requested by the first or second CPU. , The second C via the second local bus
A second switch that connects the first switch that connects the PU and the second common bus to the first common bus.
A switch and a processor system including.