JPH0731661B2 - Processor - Google Patents

Description

The present invention relates to a processor that constitutes a single processor or a multi-processor and is suitable for controlling an intelligent automatic machine.

[Conventional technology]

Conventionally, multi-processor systems have been disclosed in
As shown in Japanese Patent Laid-Open No. 59-208666, it comprises one CPU and memory, another processor element and a common bus switch which operates as a master / slave. Single CP like this
U-based multi-processor element
In the processor system, there is no problem as far as dedicated task processing with less disturbance, but as the processing contents required for the system such as intelligent control processing become sophisticated, database and system status management, database and sensor information It is essential to support a background-based processing system such as a knowledge processing system configuration, multiple interrupt processing, and multi-job function, based on a high-level language on a high-performance operating system that can support real-time multi-tasking and multi-job. It is common to describe and execute those processes.

[Problems to be solved by the invention]

In the above-mentioned conventional multi-processor system, real-time control processing, which is the main factor for speeding up, is also positioned as one of the tasks supported by multi-tasking, so task switches, overheads, and disturbances in parallel processing schedules, etc. At present, it is impossible to perform fine-grained tightly coupled parallel processing. Therefore, a supervisor system often uses a system such as a super minicomputer to separate the intelligent processing system from the control processing system by parallel processing, but the communication between the parallel processing system and the intelligent processing system tends to be sparse. The operating system overhead is required to manage the local internal status of the control processing system, which does not take advantage of the characteristics such as decentralization of intelligent processing that requires overhead and decentralization of system management. There is a problem that it is difficult to increase the processing performance of the intelligent processing system and improve the communication throughput between the two systems according to the expansion of the processing performance. Therefore, especially when the control loop of the control processing system becomes faster, such as in an automatic machine such as an intelligent robot, it is necessary to transfer relatively large data between the intelligent processing system and the control processing system at high speed. Due to the wear structure, the above problem has been a serious problem, and it has been impossible to increase the speed and accuracy of the automatic machine.

An object of the present invention is to effectively implement an intelligent processing system and a control processing system of an intelligent automatic machine such as an intelligent robot,
It is to provide a processor capable of efficiently processing both systems in a well-balanced manner.

[Means for solving problems]

The above-mentioned object of the present invention is a processor for controlling a machine that constitutes a single processor or a multi-processor, and has a local memory in each of the base processor elements constituting the processor,
One of two CPUs that share processing between the intelligent processing system and the control processing system of the machine, dual port RAM that can be accessed from those CPUs, and a common bus that can be used by both CPUs. And a common bus switch circuit for connecting the CPU of

[Action]

The processor of the present invention provides a hardware architecture for operating two CPUs provided in the base processor element as if they were one processor. In addition, paying attention to the high independence of the control processing system and the intelligent processing system based on the database and sensor information, the control processing system is assigned to the main processing system of the main CPU, and the control calculation is performed with other base processor elements It is executed by tightly coupled parallel processing, and processing with strong background factors such as interrupt processing, system management, knowledge processing, etc. is assigned to the main CPU background processing system and background CPU as an intelligent processing system, and main CPU control processing is performed. Back up the system. As a result, task, switch, overhead, and interrupt factors that disturb the parallel processing can be removed as much as possible, and two highly independent processing systems can be operated in parallel with high efficiency. In addition to substantially improving the processing performance of the base processor element by a factor of two, even in a multi-processor system in which multiple base processor elements are combined, the overall processing performance of the conventional processor is twice as high as that of the base processor element. -It is possible to realize well-balanced processing performance expansion of the control processing system and the intelligent processing system in response to the expansion of the processor element.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the processor of the present invention. In this figure, a base processor element (BPE) 1 that constitutes a multi-processor system is shown.
The internal configuration of is composed of two CPUs 15 and 16 (CPU θ and CPU 1), and as a dedicated communication mechanism between these two CPUs 15 and 16, a dual port RAM (DPR) 17 and other base processor elements (BPE) 2 CPUs to communicate
In order to connect to the BPE local bus 12 which is a common bus between two CPUs, a common bus switch 24 consisting of a multi-plexer bus buffer 23 which is switch-controlled by the common bus switch control circuit 22 without inconsistency is provided. CPU15,16
And the base processor element (BPE). Also, two CPU1
5,16 are local memory 18,20 and local I / O1
It has 9,21 etc., and can usually operate independently.
Also, a dual port R that supports communication between CPUs
A feature of AM (DPR) 17 is that it has communication interrupt lines 32 and 33 to the CPUs 15 and 16 of each other, and a communication function between the CPUs 15 and 16 with a small overhead can be mentioned. On the local bus 12 of the base processor element 1, the local memory 6 and the local I / O7 of the base processor element are connected, and a common bus line with other base processor elements is formed. Moreover, system shared memory 9 and system shared I / O1
A system bus switch 8 for connecting to the system bus 14 to which 0 is connected is provided. The system bus switch 8 performs bus arbitration processing related to access to the system bus 14 through the arbitration line 13 so as to use the shared resources on the system bus 14 consistently and with other base processor elements. It is possible to perform parallel processing between the base processor elements by performing the communication processing of.

Figure 5 shows a hardware block diagram of the dual port RAM (DPR) 17, in which the dual port RAM (DPR) 17 can be regarded as a shared memory shared between the two CPUs 15 and 16. Arbiter 60 arbitrating using access request signal and access permission signal of each processor, which indicates access to the dual port RAM (DPR) of two CPUs 15 and 16 by reference numerals 77 to 80, and enable signal 75 from arbiter 60, According to 76, the bus switches 61 and 62 for switching the buses 64 and 65 from the CPU to the internal bus 66 and the memory enable signal 81 and the interrupt control signals 73 and 74 by decoding the address and control lines of the internal bus 66 are output. From the decoder 67 which is generated, and in addition to this, the flip-flops 68 and 69 which are operated by the interrupt control signals 73 and 74 which are generated by the decoder 67 in order to set and reset the interrupt signals 32 and 33 to each CPU. Is making . The CPU-to-CPU communication interrupt function of the characteristic dual port RAM (DPR) is equipped with a register to generate an interrupt to CPUθ and a register to generate an interrupt to CPU1 at a specific address of the dual port RAM (DPR). They are defined as instruction registers to each other's CPUs, and instructions are exchanged and interrupts are generated at the same time. Taking the case where CPU1 transmits an instruction to CPUθ as an example, first, CPU1 sets the instruction attribute that CPUθ wants CPUθ to execute in its own register etc., and then sets it to the instruction register for CPUθ on the dual port RAM (DPR) ( When stored in the interrupt generation register), the decoder 67
Knows that the instruction register to CPU θ has been accessed by monitoring and decoding the internal bus 67 of the dual port RAM (DPR) and sends an instruction register access signal pulse to CPU θ using the access signal 73. And latch the value of signal 70 onto flip-flop 68. In the initial state, since Q is set to H1 and LO is set to LO by the RESET signal 70, HI is output to LO and Q to Q by the above operation.
O Interrupt signal 30 to CPU θ, which is inactive, becomes active to CPU θ.

Next, the CPU θ that received the interrupt returns to the CPU θ to obtain the instruction to be executed in its own interrupt service routine.
When the instruction register for θ is provided and the instructed instruction is provided, the decoder 67 also monitors the access status in the same manner, and the instruction register access signal pulse for CPU θ is flipped using the access signal 73. Output to flop 68, latch HI 70 and output HI to Q. That is, the interrupt generation line 32 to the CPU θ is made inactive. By the above-mentioned sequence, it is possible to simultaneously execute a series of operations from generation of an interrupt to acceptance and operations related to software instruction exchange with a minimum overhead.

Returning to Fig. 1, the bass processor element (BP
E) Select either one of CPUθ or CPU1 bus 28 or 29 in 1 and perform bus switching control (bus switch) to output as BPE local bus 12 that can be regarded as a shared bus between CPUθ and CPU1. The common bus switch 24 is composed of the shared bus switch control circuit 22 and the multiplex bus buffer 23 controlled by the shared bus switch control circuit 22 as described above. The bus switch control is based on CPU θ as the master and C
When PU1 is used as a slave, it is simply carried out by a shared bus switch logic having a NOR circuit 83 and a NAND circuit 84 shown in FIG. The characteristic bus switch control sequence is arranged with the time chart shown in FIG. First, the acquisition rights of the local buses 28 and 29 of the two CPUs are always on the respective CPUs side and are not infringed by devices on other buses. (,). The shared bus (BPE local bus 12) access request of the CPU θ is always active as shown in, and the shared bus access request of the CPU 1 is always active as shown in. That is, except when the CPU 1 acquires the shared bus, the CPU θ side always acquires the shared bus. In the example shown in FIG. 2, the CPU 1 outputs the shared bus access request 87 at a,
In response to this, when the CPU θ finishes the instruction processing being executed at that time and becomes ready to relinquish the shared bus right, immediately output the halt acknowledge 82 with a and the CPU with a
Deactivate the θ shared bus access grant signal 85 (driven by gate 83) and relinquish the shared bus as shown at a. Further, at a, the CPU θ itself enters the halt state, and at the same time, at a, the shared bus access permission signal 86 (driven by the gate 84) of the CPU 1 becomes active, and the bus switch buffer 23 is activated as shown in a. The CPU1 side of is selected, and the right to use the shared bus is transferred to CPU1. When it is time for the CPU1 to finish using the shared bus and abandon the shared bus, the CPU1 shared bus access request 87 is made inactive as shown in b. Immediately after that, the CPUθ shared bus access permission signal 85 becomes active at b, the CPUθ side of the bus switch buffer 23 is selected, and after the shared bus usage right is transferred to CPUθ,
In b, the CPU θ halt acknowledge is released, b
The CPU θ shifts from the halt state to the production state. And indicate the actual operating states of CPU θ and CPU 1, respectively. Master (CPU θ), slave (CPU
1) In order to perform the operation, the CPU θ transfers the shared bus to the CPU 1 (a-b) and for a short time (b) during which the bus switch is performed and the electrical and timing characteristics of the bus are adjusted without contradiction. -It becomes a halt condition for the total time with b) and does not operate. That is, in terms of the production right, the CPU 1 operates like a mask. To prevent the CPU θ from interfering with the halt time being too long,
A mode is provided in which the shared bus usage right is transferred to the CPU θ for each data transfer. However, as will be described later, when the CPU θ is used as a main CPU, the CPU 1 is used as a back ground CPU for performing intelligent processing, etc. in a form supporting the CPU θ, and a multi-processor configuration is adopted, a base processor element ( By adopting the distributed knowledge base form of function distribution structure on a BPU) basis, much necessary data can be obtained close to itself, and most data communication can be performed using dual port RAM (DPR). it can.
Therefore, the rate at which knowledge information is exchanged between base processor elements (BPE) is sufficient compared to the rate at which CPU θ exchanges information with other base processor elements (BPE) due to the tightly coupled parallel processing. Small, according to the invention
The processing power loss of CPU θ can be regarded as negligible. In addition, if the role of CPU1 is fixed to perform the CPU θ back-up and system management,
It is more effective in terms of management to give the CPU 1 the right to control the operation of θ, and it can be said that the shared bus control of the present invention is suitable for the local distributed processing as described above.

Next, the general operation of the processor of the present invention described above will be described in detail with reference to FIG.

In Fig. 3, CPUθ performs the main control calculation, CPU1 performs intelligence processing and system management based on knowledge base (distributed type) and sensor information, etc., and CPUθ backs up in the background, and local distributed processing is performed. I'm assuming. Also, when the multi-processor configuration is adopted, each base processor element (BPE) performs tightly coupled parallel processing in the main together with other base processor elements (BPE), and loosely coupled parallel processing in the background. I assume that. 35 along the time axis
It shows the processing flow of CPU1, 36, 37, 38 are CUP in the same way.
The processing flow of θ is shown. The shared resource is a dual port RAM (DP) which is a local shared memory between CPU θ and CPU1 in the base processor element (BPE).
R) and system shared resources on the system bus 14 that are accessible from all base processor elements (BPEs) in a multi-processor configuration. 47,48,
54,59 indicates communication between CPUθ and DPR, 46,53,56,58 indicates CPU1
And shows communication with DPR. Similarly, 57 indicates the communication between the CPU θ and the system shared resource, 51 indicates the communication between the CPU 1 and the system shared resource, and when observed from the system shared resource side, any of them is regarded as an access from the base processor element (BPE). Be done. Also, 50 is the dual port RAM (D
PR) shows an interrupt to the CPU θ using the interrupt function, and 55 similarly shows an interrupt to the CPU1. 49 for CPU1
Shows the state of handshake of the shared bus access request signal from the CPU to the CPU θ and the corresponding shared bus access permission signal from the CPU θ, 52 indicates the shared bus once acquired by the CPU 1 is abandoned and its use Right again CPU
It shows how to move to θ. 88 and 89 indicate access to system shared resources from other BPEs. 90 and 91 show that local sensor information, which is external information, is taken in during the processing of CPU1 as a part of the knowledge. Similarly, 92 and 93 are shared sensors that are also shared by other BPEs. It shows how the information is taken in by CPUθ, CPU1.
Regarding the processing contents of CPUθ and CPU1, CPUθ is the main processing system and other base processor elements (BPE).
Together with the CPU θ, a large number of control operation tasks necessary for controlling a part of the knowledge machine system, for example, the arm part of the humanoid intelligent robot are shared so as to improve the parallelism as much as possible, and highly efficient tightly coupled parallel processing. Assuming that 36b and 38b are being executed, the free time after requesting processing to an auxiliary processor such as an arithmetic processor, the free time that occurs during synchronization processing with other base processor elements (BPE), and other Bass processor element BPE
When the CPU 1 and the processing request by the interrupt from the shared resource are performed as the background processing system, the intelligent processing shown by 36a and 38a, system management, etc. are performed in cooperation with the CPU 1, and the intelligent processing system is configured together with the processing 35 of the CPU 1. The intelligent processing system executed by this base processor element (BPE) holds a group of information about a further part of the arm part, for example, a muscle part, as a data base.
Sensor information, which is deeply related to it, is also taken in as perceptual information, and based on a local functional distributed database constructed by them, intelligent processing related to muscle parts is executed, and control calculation executed in the main processing system. The whole is supposed to be backed up.

In the system based on the above assumption, the processing flow of CPU θ and CPU 1 shown in FIG. 3 will be briefly followed.
First, the CPU θ and the CPU 1 are executing the processes 36 and 35 shown in FIG. 3, respectively, and the CPU 1 immediately needs communication with the CPU θ and at 39, writes a communication message to the dual port RAM (DPR), The operation 46 of writing the contents of communication as an instruction into the instruction register to the CPU θ is performed. Correspondingly, CP
An interrupt 50 to Uθ occurs, the dual port RAM (DPR) is accessed in the background processing system of the CPUθ, and necessary information communication 47 is performed. At the time of 40, CPU θ was writing shared data between CPUs that do not need to be handshake to a cascading dual port RAM (DPR) or reading from the dual port RAM (DPR). Various sensor information is also taken in as a part of the knowledge by the sensor side being the subject and being sequentially processed by an interrupt, or being referred to in the program as necessary. Next, CPU1 communicates with another base processor element (BPE), which requires communication with system shared resources.
Acquired the right to use 12 common buses (BPE local buses) at 4
At the time of 1, communication 51 with the system shared memory is performed, and when completed, at 52, the right to use the common bus is transferred to the CPU θ again. During that time, the CPU θ is kept in the halt state 37, and when the halt state is released by 52, the process 38 which is a continuation of the process 36.
To continue. After that, at 42, CPU 1 and dual port
The shared data is exchanged between the CPUs by the RAM and (DPR), and at the time of 43, the communication of the handshake data with the instruction from the CPU θ to the CPU 1 is executed similarly to 39. 44
Communication between the CPU θ and the system shared resource is performed, and the communication content includes communication related to intelligent processing in the background processing 38a and communication of tightly coupled parallel processing data related to control calculation in the main processing 38b. In that case, the influence on the processing and operation of the CPU1 is not a problem.
Reference numeral 45 shows that the CPU θ and CPU1 dual-port RAM (DPR) are running at the same time, and the arbiter 60 performs appropriate arbitration control to enable mutual processing and operation. Communication processing is being executed without any support.

When the processor of the present invention realizes the intelligent processing system based on the local distributed database and the control processing system backed up to the above, most of the intelligent processing is performed by the base processor via the dual port RAM (DPR).
It is only necessary to execute it between the CPUs in the element (BPE), and occasionally to access the system shared resource in order to exchange the processing result and the intelligent processing result by other base processor element (BPE). It is possible to realize the best communication throughput between the communication nodes of the above, and the control processing system and the intelligent processing system can operate in parallel almost completely independently, so that the processing performance can be surely doubled. Becomes Further, by adding BPE, the processing performance of the intelligent processing system and the processing performance of the control processing system increase in proportion to each other, and it is possible to always provide the processing performance in which both are balanced.

According to an embodiment of the present invention, a processor element (base processor element: BP) that is the basis of a multi-processor system or a single processor system.
E) is composed of two CPUs, dual port RAM (DPR) with interrupt function for them, and both Cs that look like a single CPU when observed from the outside by the master / slave operation.
Connected to a common bus that can be commonly used from PU, separate the main processing system and background processing system with high independence, and let each two CPUs take charge of each other, exchanging local information between the two CPUs. Communication via the dual port RAM (DPR), and communication with other base processor elements (BPE) in the case of a multi-processor configuration is via a common bus (BPE).
The performance of the BPE is substantially doubled by performing the system shared resource on the system bus through the local bus). Further, in the case of configuring a multi-processor system using the processor of the present invention, by distributing the functions of the database of the background processing system in each BPE unit, most of the background processing system also has a processor inside the processor. It does not have to be closed by local communication and frequently communicate with other processors, which optimizes the communication throughput between communication nodes, which has a great impact on the tightly coupled parallel processing executed in the main. Instead, both the main processing system and the background processing system can naturally perform highly efficient parallel processing. Further, by adding the processor of the present invention, it is possible to always improve the processing capacity in a balanced manner in both the main processing and the background processing system.

Next, an extended application of the basic processor element (BPE) of the present invention to a multi-processor system and a configuration example of an intelligent robot system using the system will be described.
It will be described with reference to the drawings.

A base processor element (BPE) of the present invention is represented by reference numeral 1 in the drawing. Each base processor element 1 is connected to a common bus 14a-14d by a base processor element local bus 12. 99a.99d are bus arbiters corresponding to the common buses 14a-14d, and 13a-13d are corresponding arbitration lines. The common buses 14a to 14c form a shared memory dedicated bus for the corresponding shared memory systems 9a to 9c, respectively. 14d is a shared I / O bus that supports shared I / O. These four common buses usually have access rights to the CPU θ (15 in FIG. 1) in charge of the control processing system in the BPE shown in 1 and the CPU 1 in charge of the intelligent processing system as necessary.
It is used by (16 in Fig. 1).

Therefore, the common buses 14a to 14d can be considered as dedicated buses for the control processing system. CP for each bass processor element
Uθ uses these common buses for communication and performs tightly coupled parallel processing of necessary control operations. 101 is a hardware mechanism for controlling parallel processing (communication controller), and 103 is a hardware mechanism (communications interrupt controller) for controlling interrupts for communication between base processor elements. . The base processor element is provided with a bus switch circuit 102 for supporting the system bus 100 as a dedicated common bus on the side of the intelligent processing system, and a local bus of the CPU 1 in charge of the intelligent processing system. The shared database 107 and various shared sensor interfaces are placed there. Further, a floating point unit (FPU) 104 is provided on the local bus of the CPU 1 which is in charge of the control processing system in order to perform high-speed numerical operation processing. The multi-processor system of this example has a total of 14 base processors.
It is composed of elements, but this system is further modularized, so that multiple modules can be combined with each other,
An external expansion channel 105 directly connected to a hardware communication mechanism such as the internal common buses 14a to 14d and a software intervention type external expansion channel 106 are provided. If the external expansion channel 105 (hardware direct type) is used, the data of the internal shared memories 9a to 9c can be directly referred to from an external module at high speed, and if the external expansion channel 106 (software intervention type) is used, Advanced and flexible communication based on one protocol can be performed with other modules.

By using the base processor element configured in this way, as described above, it is possible to construct a multi-processor system capable of effectively supporting the control processing system and the intelligent processing system. In FIG. 6, a robot system is connected as a control target. Next, this will be described.

The robot system has robot mechanisms 114a and 114b.
And its support unit 111 (including power amplifier, etc.) and robot mechanism 114a, 114b as a sensory organ.
It is composed of sensors 113a and 113b provided in the sensor and a sensor 112 such as a television camera. The multi-processor system of this example performs high-speed coordinate conversion processing, dynamics calculation processing, etc. on the control processing side, and as a result, the necessary commands such as position, speed, and acceleration are sent to the servo on the common I / O bus. The servo unit 111 is transmitted via the interface 110. On the contrary, from the servo unit 111, the current operating state itself of the robot is detected by the sensor 5 such as an encoder, a tachogenerator, an acceleration detector, a motor current detector, etc., and is fed as feedback data via the servo interface 110. Transmitted to multi-processor system. The control processing system of the multi-processor system calculates the next command value to the servo unit 111 by utilizing the feedback data and the commands and data sent from the intelligent processing system. In addition, the intelligent processing system uses two robot mechanisms 11
4a, 114b shared sensor 112 sends data to system bus 100 via shared sensor interface 108, and sensors 113a, 11b specific to robot mechanisms 114a, 114b respectively.
The 3b sends the direct data of the intelligent processing system of each base processor element in charge of each function via the local sensor interfaces 109a and 109b. Based on the information from these sensors 112, 113a, 113b and the shared database 107, the intelligent processing system performs intelligent processing such as sensing, inference, learning, and the necessary processing of these results to the control processing system, such as commands. Backup the processing system.

As described above, according to the embodiments of the present invention, the control processing system performs advanced motion control calculation under the support of advanced intelligence processing, and thus has functions such as sensing, inference, and learning, and high speed. , It is possible to build an intelligent automatic machine control system such as intelligent robot that performs highly accurate motion.

Further, according to the embodiment of the present invention, a control processing system and an intelligent processing system can be separately implemented in a base processor element which constitutes a control device for intelligent automatic machine control such as an intelligent robot, so that processing of both systems can be performed. Capabilities and functions can be expanded in a balanced manner in a single processor environment or a multi-processor environment. In addition, a dual-port RAM dedicated to the local tightly coupled communication between the intelligent processing system and the control processing system in the base processor element.
It is possible to minimize the possibility of disturbing the communication of the control processing system in a multi-processor environment and causing a serious bus network by directly connecting the CPUs in charge of the two systems to each other. ， The communication throughput between each function can be optimized. In addition, a master / slave type bus switch to support a common bus that can be accessed from two CPUs in the basic processor element.
Interface (multi-plexer / bus buffer and common bus / switch control circuit) is provided and dual CPU
By making the basic processor composed of a single processor into a single processor, it is possible to easily connect a plurality of basic processors to each other by a plurality of buses, so that the processing capability and the function can be efficiently and uniformly expanded.

〔The invention's effect〕

According to the present invention, sensing is performed by the control processing system performing advanced and high-load motion control calculation processing such as high-speed control and dynamics control with the support of a sensory device such as a sensor or an intelligent processing system based on a knowledge base. It is possible to realize control of an intelligent automatic machine such as an intelligent robot having functions such as inference and learning and performing high-speed and high-precision motion.

[Brief description of drawings]

FIG. 1 is a diagram showing an internal structure of a base processor element in a processor of the present invention and a part of a multi-processor system based on it, and FIG. 2 is two CPUs in the base processor element constituting the present invention.
Fig. 3 shows a common bus (BPE local bus) switch sequence between two CPUs, Fig. 3 shows a flow of processing between two CPUs in the base processor element, and Fig. 4 shows a shared bus constituting the present invention.・ Basic logic diagram of switch, No.5
FIG. 6 is a logic block diagram of a dual port RAM which constitutes the present invention, FIG. 6 is a diagram showing an example in which another embodiment of the processor of the present invention is applied to an intelligent automatic machine, and FIG.
It is a figure which shows the structure of the processor in the example shown in a figure. 1 ... Bass, Processor Element (BPE), 8
…… System bus switch, 14 …… System bus, 15 …… CPU θ (master) 16 …… CPU1 (slave), 1
7 …… DPR logic, 24 …… Common bus switch, 32 ……
CPUθ instruction interrupt line, 33 …… CPU1 instruction interrupt line, 73 …… CPUθ interrupt generation flip-flop, 74 …… CPU1 interrupt generation flip-flop, 85 …… CPUθ common bus access Permission signal, 86 …… CPU
1 Common bus access permission signal, 99 …… Arbiter, 100 ……
Intelligent processing common bus system, 107 …… shared knowledge base, 108 …… shared sensor interface, 109 …… local sensor interface, 110 …… servo interface, 111 …… servo unit, 112 …… shared sensor, 113 …… Local sensor, 114a, 114b …… Robot mechanism.

Claims (17)

[Claims] 1. A processor for constituting a single processor and controlling a machine, wherein a base processor element constituting the processor is provided with processing of one control system and another control system of the machine. Two CPUs that share each of them, a memory unit that can be respectively accessed from the two CPUs, and a switch unit that connects one of the two CPUs to a common bus that connects to each control system of the machine. A processor characterized by having. 2. The processor according to claim 1, wherein the first CPU, the second CPU, the memory means and the switch means are integrated into a single processor. 3. The processor according to claim 1, further comprising a plurality of the base processor elements, which are modularized. 4. A processor for constituting a single processor and controlling a machine, wherein a base processor element constituting the processor shares the processing with an intelligent processing system and a control processing system of the machine. Two CPUs, a memory means that can be respectively accessed from the two CPUs, and a common bus that connects one of the two CPUs to the intelligent processing system of the machine and a common bus that connects to the control processing system. A processor comprising switch means for connecting to each other. 5. The processor according to claim 4, wherein the switch means always connects one of the two CPUs to one of the common buses. 6. The processor according to claim 4, wherein one of the two CPUs has means for monitoring the operation of the other CPU. 7. A processor according to claim 4, wherein said two CPUs, memory means and switch means are integrated into one chip. 8. A processor for constituting a multiprocessor and controlling a machine, wherein a base processor element constituting the processor has a first CPU in charge of processing of an intelligent processing system of the machine, A second CPU in charge of the processing of the control processing system of the machine, a memory means accessible from the first CPU and the second CPU, and a common bus connecting the first CPU to the intelligent processing system of the machine. And a second switch means for connecting one of the first and second CPUs to a common bus for connecting to the control processing system of the machine. The processor to do. 9. The processor according to claim 8, wherein the second switch means causes the second CPU to be permanently connected to a common bus connected to the control processing system of the machine. 10. A method according to claim 8, wherein the first CPU includes means for monitoring the operation of the second CPU.
The processor according to the paragraph. 11. The first CPU, second CPU, memory means,
9. The processor according to claim 8, wherein the switch means is integrated into a single processor. 12. The processor according to claim 8, comprising a plurality of the base processor elements, which are modularized. 13. A processor for constituting a multiprocessor and controlling a machine, wherein a base processor element constituting the processor has a first CPU in charge of processing of an intelligent processing system of the machine, A second CPU in charge of processing of a control processing system of a machine, a memory means accessible from the first CPU and the second CPU, and the first or second CPU connected to a first common bus And a switch means to form a processor, the first CP of the plurality of base processor elements
U is connected to the second common bus of the intelligent processing system of the machine, and the second CPU of the plurality of processors is connected to the third common bus of the control processing system of the machine via the first common bus. A processor characterized by being connected. 14. The processor according to claim 13, wherein the switch means comprises a switch circuit for permanently connecting the second CPU to a common bus of a control processing system of the machine. 15. The method according to claim 13, wherein the first CPU includes means for monitoring the operation of the second CPU.
The processor according to the paragraph. 16. The first CPU, second CPU, memory means,
14. The processor according to claim 13, wherein the switch means is integrated into a single processor. 17. The processor according to claim 13, comprising a plurality of the base processor elements, which are modularized.