JPH02170261A - Parallel arithmetic unit - Google Patents

Abstract

PURPOSE:To detect a specific subprocessor that is through with its operation by preparing the flags to produce the end signals for each of plural processors showing the end of their operations. CONSTITUTION:An interruption line 100 kept in an active low state is activated and outputted at the time point when all processors finished their arithmetic processes in one of plural modules. Thus it is detected via the line 100 that all processors of a certain module finished their arithmetic processes. In addition, the flags (1)21-(N)29 serving as the end signals showing the end of the arithmetic operation of each processor are connected to a bus 110 connecting the modules in common to each other as the status flags 41-49 set for each corresponding module. Thus it is possible to detect which subprocessor has finished arithmetic process with use of another mainprocessor installed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel computing device that synchronizes a plurality of processors and executes parallel computing.

[Conventional technology]

Conventionally, in a parallel computer system that uses multiple processors to execute operations in parallel, it consists of - main processors and multiple sub-processors, and the sub-processor is There was a parallel computing device that communicated data with the processor.

The end flag in this device may be placed first in a data memory provided independently for each subprocessor, or secondly placed in a data memory possessed by the main processor.

In the first configuration, each sub-processor can write an end flag to a data memory connected to the processor, regardless of the operations of other sub-processors.

The main processor sequentially reads the completion flags of all sub-processors and after confirming that the calculations have been completed, collects the calculation results of each sub-processor and distributes the data for the next calculation.

In the second configuration, each sub-processor writes the end flag to the data memory connected to the main processor, but since it writes to the memory connected to the main processor in common with other sub-processors, there is no communication between the processors. Memory access arbitration is required. The main processor reads the end flags written by each sub-processor, confirms that the calculations have been completed, and then collects the calculation results of each sub-processor and distributes the data for the next calculation.

[Problem to be solved by the invention]

In the first conventional parallel processing device described above, each subprocessor can independently set the end flag.
The main processor must periodically and sequentially read out the end flags of all processors, which reduces processing efficiency on the main processor. Furthermore, in the above-mentioned second conventional parallel processing device, as in the first conventional parallel processing device, the main processor must periodically and sequentially read the end flags of all processors. On the other hand, since each sub-processor writes to the memory connected to the main processor in common with other sub-processors, it is necessary to mediate memory access between sub-processors.
This reduces the processing efficiency of the sub-processor. Furthermore, there are various problems such as the processing of the main processor being stopped during the arbitration period and the data writing period, further reducing the processing efficiency on the main processor.

An object of the present invention is to provide a parallel computing device that solves these problems.

[Means to solve the problem]

The configuration of the parallel processing device of the present invention is such that in a parallel computer system in which a plurality of processors are installed in one module and operations are executed in parallel using the plurality of modules, the plurality of processors and the plurality of processors indicating the completion of the operation are provided. A flag is installed in each processor to generate a termination signal, and a flag is connected to a plurality of the termination signals installed in the same module and installed in each module to output the result of ANDing all the termination signals. The present invention is characterized by comprising: a plurality of AND gates, a bus commonly connected between the respective modules, and an interrupt line connected to all the plurality of AND gates.

[Effect]

The principle operation of the parallel arithmetic device according to the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing the principle operation of the present invention.
> 11, Processor (2>12... Processor (K-1> 14., Processor (K) 15.
The present invention relates to the configuration of a parallel computer system that executes operations in parallel using processors (K+1.>16, . . . processors (N) 1.9).

The plurality of processors according to the present invention each generate a flag (1) 21 and a flag (
2)22. ...Flag (K-1) 24 Flag (K) 25. Flag (Kth) 26. ...Flag (N) 29 is provided. When each processor finishes processing, it activates the end signal. However, for convenience of explanation, positive logic will be used here unless otherwise specified, and active means that the logic level is 1 or H. However, "active low" indicates that negative logic is used, and "active" means that the logic level is O or L.

Among the plurality of processors, the flag (1) 21, which is an end signal indicating the end of the calculation of the first processor (1) 11 included in the first module, module 1, and the second processor (2>12) Flag (2) 22, which is an end signal indicating the end of the calculation, ......The first processor (
K-1) A flag (
K-1>24 is ANDed by the first AND gate 51, and the result is output as the first AND gate output 31. Similarly, the end signals of all the processors included in module 2, which is the second module, are ANDed by AND gates 1 to 52, and the result is output as the first AND gate output 32, etc. Similarly, for all the modules included in the system, the end signals of the processors of the modules are logically ANDed and output as an AND gate output.

On the other hand, all the AND gates 51 and 52
, . . . AND gate 59 is composed of oven collector output or three-state output, and its outputs 31, 32, . . . 39 are commonly connected to interrupt line 1.
Connected to 00. In addition, all of the AND gate outputs are active low, and by configuring the output to become active, that is, low level, when all the corresponding AND gate inputs become active, any output becomes active. At times, interrupt line 100, which is active low, may be active.

According to the configuration of the present invention shown in FIG. 1, the interrupt line 100, which is active low, becomes active when the arithmetic processing of all the processors in any one of the plurality of modules is completed. Output. For this reason, the plurality of processors are made sub-processors,
When applied to a system that realizes parallel processing by exchanging data between separately provided main processors, it is possible to use the interrupt line 100 to detect that all sub-processors in any module have completed arithmetic processing. can.

Furthermore, a flag (1) 21. Flag (2) 22,...
By connecting the flag (N) 29 to the bus 110 that is commonly connected between the modules as status flags 41, 42, . . . 49 for each corresponding module, the main It becomes possible to detect from the processor which subprocessor has completed the calculation.

〔Example〕

Specific embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, a processor (1
) 11, Processor (2) 12... Processor (K-1) 14, Processor (K) 15. Processor (K-1>16,...Processor (N)
19 executes arithmetic processing in parallel with the main processor 10. In the parallel computing device shown in this embodiment, each of the plurality of processors has a flag (1) 21. Flag (2) 22,...
...Flag (K-1) 24, Flag (K) 25 Flag (K-1) 26, ...Flag (N) 29
It is equipped with Each processor activates a termination signal when processing is completed.

Furthermore, independent data memories 61, 62, 64, 65, 66, and 69 are connected to each processor, respectively, and at the same time, the data memories are connected to the main processor 10 via a bus 110. In parallel arithmetic processing using multiple subprocessors, first,
After the main processor 10 confirms that all of the plurality of subprocessors included in a certain module have completed their calculations, the data necessary for the calculation is distributed to the data memory connected to each subprocessor in the module. Ru.

When each sub-processor detects that data has been written to the data memory, it executes arithmetic processing specified in advance for each sub-processor.

When the computation is completed, flags 21 to 29, which are completion signals, are activated to notify the main processor 10 of the completion of the computation. As explained in detail in the operation section above, when the interrupt line 100 becomes active,
When the main processor 10 detects the completion of computations of all sub-processors in any module, it collects the computation results from the data memory of each processor in the corresponding module.

According to the embodiment shown in FIG. 2, when the arithmetic processing of all processors belonging to a certain module among all the plurality of sub-processors is completed, the interrupt line 10 which is active low
0 becomes active and is output. At this time, by connecting the interrupt line 100 to the interrupt input of the main processor 10, the main processor 10 knows that the calculations of all sub-processors on a certain module have finished without sequentially checking the completion signal of each sub-processor. be able to.

According to the configuration shown in the figure, each sub-processor can output the end flag independently of other processors, and a decrease in the processing efficiency of the sub-processors can be avoided.

Furthermore, the main processor does not need to regularly and sequentially check the computation completion status of the sub-processors until an interrupt occurs, and the processing efficiency of the main processor does not decrease.

Furthermore, according to the configuration shown in this embodiment, even when a plurality of modules are executing arithmetic operations in parallel, it is possible to efficiently detect a module that has completed arithmetic processing.

In addition, data can be transferred only to modules that have completed processing to collect calculation results and distribute the data necessary for the next calculation, regardless of the module that is continuing calculation processing. .

The configuration and operation of each block described above can be easily deduced by analogy to those skilled in the art, and further detailed explanation will be omitted.

Although the embodiments of the present invention have been described in detail using a configuration that performs logical AND using positive logic, it is easy to apply the present invention to a device that performs logical sum using negative logic. Also, 1
In addition to devices that perform parallel calculations using one main processor and multiple sub-processors, the present invention can also be applied to devices with multiple main processors, and DMA (DMA) where the main processor does not directly exchange data with the sub-processors. It is clear that the application form of the present invention can be modified, such as application to a parallel processing device using a direct memory access) device.

〔Effect of the invention〕

According to the present invention, it is possible for a plurality of processors to independently output an end signal indicating that arithmetic processing has ended. At this time, there is no need to consider the operations of other processors, and there is no need to arbitrate data output between processors, so the processing efficiency of the multiple processors is not reduced.

In addition, in a configuration in which multiple processors are used as sub-processors and a main processor is provided that synchronizes the entire arithmetic processing, the output of the lower gate obtained by logically ANDing the end signals for each module is connected to the interrupt input of the main processor. As a result, the main processor can efficiently know the completion of calculations of all sub-processors in any module without sequentially checking the completion signal of each sub-processor. The main processor does not need to periodically and sequentially check the computation completion status of the sub-processors until an interrupt occurs, and the processing efficiency of the main processor does not decrease. Furthermore, since each sub-processor does not access the memory on the main processor to write the termination signal, the processing being performed on the main processor is not interrupted.

Furthermore, since it is possible to detect modules that have completed calculation processing, collection of calculation results and distribution of data necessary for the next calculation can be performed only for modules that have completed processing, regardless of modules that are continuing calculation processing. It has a major feature of being able to perform data transfer for various purposes.

From the viewpoint of the scale of required hardware, it is sufficient to provide only common interrupt lines and a bus for data transfer between all modules. Therefore, according to the present invention, a parallel processing device having the above effects can be obtained with a simple device configuration.

According to the present invention described above, a parallel computing device that solves the above-mentioned conventional problems can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle operation of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. 11.12, 14, 15, 16.19... Processor, 21, 22, 24.25, 26.29... Flag,
31, 32.39...AND gate output, 51.52
．． 59...and gate, 61, 62° 64.65,
66.69...Data memory.

Claims (1)

[Claims] In a parallel computer system in which a plurality of processors are installed in one module and operations are executed in parallel using the plurality of modules, the plurality of processors and an end signal installed for each of the plurality of processors indicating the end of the operation are generated. an AND gate connected to a plurality of the termination signals installed in the same module and installed in each module to output the result of ANDing all the termination signals, and an AND gate installed between each module. A parallel arithmetic device comprising a commonly connected bus and an interrupt line connected to all of the plurality of AND gates.