JPH04276851A - Parallel arithmetic unit - Google Patents

Abstract

PURPOSE:To provide a parallel arithmetic unit that allows outputting of a termination signal indicating that each of a plurality of processors terminate arithmetic processing independently without consideration for the operation of another processor and without adjusting work on data output between processors, and that enhances the processing efficiency of a plurality of processors. CONSTITUTION:A plurality of processors 11, 21, and 91 execute arithmetic operation in parallel. Flags 12, 22, and 92 output a first and second flag signals that indicate the termination of arithmetic processors 11, 21, and 91 and arithmetic operation error. Buffers 12, 29, and 99 output data for every first flag signals 18, 28, and 98 to a logical product circuit 9, and inverters 13, 23, and 93 output data for every second flag signals 15, 25, and 95 to an OR circuit 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computing device in which a plurality of processors synchronously execute parallel computing.

0002

[Prior Art] Conventionally, in a parallel computer system that uses multiple processors to execute operations in parallel, it consists of one main processor and multiple sub-processors, and an end flag is set for each of the multiple sub-processors. There was a parallel computing device that communicated data with subprocessors by value. In this device, the end flag is placed in a data memory provided independently for each sub-processor as a first conventional example, and in a data memory possessed by a main processor as a second conventional example. .

In the configuration of the first conventional example, each sub-processor can write an end flag to a data memory connected to the processor, regardless of the operation of other sub-processors. The main processor sequentially reads the completion flags of all sub-processors, and after confirming that the calculations have been completed, collects the calculation results of each sub-processor and distributes the data for the next calculation.

[0004] In the configuration of the second conventional example, each sub-processor writes an end flag to the data memory connected to the main processor, but in common with other sub-processors, it cannot write to the memory connected to the main processor. To do this, memory access arbitration between processors is required. The main processor reads the completion flag written by each sub-processor, confirms the completion of the calculation, and then collects the calculation results of each sub-processor and distributes the data for the next calculation.

[0005]

[Problems to be Solved by the Invention] In the first conventional parallel processing device described above, each sub-processor can independently set the end flag, but the main processor periodically sets the end flag of all processors. Moreover, it is necessary to read out the data sequentially, which reduces processing efficiency on the main processor.

[0006] Furthermore, in the second conventional parallel computing device,
The main processor must periodically and sequentially read the termination flags of all processors, which reduces the processing efficiency on the main processor. In addition, each sub-processor has memory connected to the main processor in common with other sub-processors. In order to write to the subprocessor, memory access arbitration between the subprocessors is required, which reduces the processing efficiency of the subprocessors.

[0007] Furthermore, there is a problem in that the processing of the main processor is stopped during the arbitration period and the data writing period, further reducing the processing efficiency on the main processor.

[0008]

[Means for Solving the Problems] A parallel arithmetic device of the present invention includes a plurality of arithmetic processors that execute arithmetic operations in parallel, and outputs first and second flag signals indicating the state of arithmetic processing of the arithmetic processors. a buffer that outputs each of the first flag signals to the AND circuit, and an inverter that outputs each of the second flag signals to the OR circuit.

[0009]

[Operation] The operation of the parallel computing device of the present invention will be explained with reference to FIG.

Processor (1) 11, Processor (2)
21... In a parallel computer system that executes operations in parallel using processors (N) 91, each of the plurality of processors (1) to (N) is equipped with a flag (1) 11... flag (N) 92. ing. Each flag consists of multiple flag signals, each with its own meaning, and each processor (
1) to (N) activate the flag signal as necessary. However, for convenience of explanation, positive logic will be used here, and active means logic level 1 or H.

Each flag signal is sent to the inverter 1 as necessary.
93, 94 or buffers 19, 29, . . . 99. The inverter and buffer have open collector outputs, and drive the signal line in common with other outputs. The respective signal outputs are connected to common signal lines 103, 104, . . . , 109 for each purpose. Furthermore, inverters 13, 14, 23, 24...93, 9
Signal lines 103, 104... connected to the outputs of inverters 3 and 4 are connected to the inputs of inverters 3 and 4, and
The signal line 109 connected to . . . 99 is connected to the input of the buffer 9.

According to the above configuration, when any one of the flag signals connected to the inverters 13, 23, . H, ie, active. Also, among the flag signals, buffers 19 and 2
9,...The signal line 109 becomes H only when all of the signals connected to 99 are active, that is, at H level.
The output 209 of the buffer 9 becomes H, that is, active. Therefore, among the flag signals for each processor, signals that need to be activated only when all processors activate the signal should be connected to an inverter, and output only when any processor activates the signal. Signals that need to be activated can be connected to buffers.

For convenience of explanation, an example in which one buffer and two inverters are used for each processor has been described here, but any number of buffer inverters may be used.

[0014]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, operations are executed in parallel using processor (1) 11, processor (2) 21, . . . processor (N) 91. Multiple processors (1) to (N
) are respectively flags (1) 12...flags (N) 92
It is equipped with Each flag (1) to (N) is an error detection flag 15, 25, 95, an operation end flag 18, 28,
Consists of 98. Each of the processors (1) to (N) activates the calculation end flags 18, 28, and 98 when the calculation ends, and activates the error detection flags 15, 25, and 95 when an error is detected. However, for convenience of explanation, positive logic will be used here, and active means that the logic level is 1.
or H.

Here, error detection flags 15, 25, 95
are connected to inverters 13, 23, 93, and calculation end flags 18, 28, 98 are connected to buffers 19, 29, . . . 9
Connected to 9. The outputs of the inverters 13, 23, 93 are commonly connected to a signal line 103, and the outputs of the buffers 19, 29, . . . , 99 are commonly connected to a signal line 109.

Signal line 103 is connected to the input of inverter 3, and signal line 109 is connected to the input of buffer 9. The output of the inverter 3 is used as an error output 203 in a higher-order processor, and the output of the buffer 9 is used as an operation completion output 209.

According to the above configuration, when any one of the error detection signals connected to the inverters 13, . Also,
Of the flag signals, the computation end flags connected to the buffers 19, 29, .

[0020] With this arrangement, the computation end output 209 becomes active and output when the computation processing of all the plurality of processors is completed. At this time, the calculation end output 209
By connecting the main processor to the interrupt input, the main processor can know the completion of operations of all processors without sequentially checking the completion signal of each processor.

Furthermore, by similarly connecting the error output 203 to the interrupt input, it is possible to detect the occurrence of an error even if an error occurs in the calculation of any processor. Further, each processor can output a flag independently of other processors, and a decrease in processing efficiency of the processor can be avoided. Furthermore, the main processor does not need to periodically and sequentially check the processor's operation completion status until an interrupt occurs, and the processing efficiency of the main processor does not decrease. Furthermore, when the processor is configured as an independent printer board, the calculation end output 2
09 and the error detection output 203 can be connected as a common bus, and from the viewpoint of the required hardware scale, as an example, assuming that each sub-processor is configured as a single printed circuit board, the embodiment Even though the end signal requires AND and the error signal requires OR, the end signal and error detection signal can be connected as a common bus. Therefore, there are no restrictions on the board insertion position, and there is no need for connections other than the common bus, making connection between the boards very easy.

Further, in a configuration in which a plurality of processors are used as sub-processors and a main processor is separately provided for synchronizing the entire arithmetic processing, by connecting the termination signals of all the sub-processors to the interrupt input of the main processor,
The main processor can know the completion of calculations of all sub-processors without sequentially checking the completion signals of each sub-processor. The main processor does not need to periodically and sequentially check the computation completion status of the sub-processors until an interrupt occurs, and the processing efficiency of the main processor does not decrease. Furthermore, since each sub-processor does not access the memory on the main processor to write the end signal, the processing being performed on the main processor is not interrupted.

[0023]

As described above, the present invention outputs first and second flag signals indicating the state of arithmetic processing of a plurality of arithmetic processors that execute arithmetic operations in parallel, and the buffer outputs the first flag signal. By outputting each signal to the AND circuit and the inverter outputting each second flag signal to the OR circuit, each arithmetic processor does not have to consider the operation of other processors, and arbitration regarding data output between processors is possible. Since no work is required, the processing efficiency of multiple processors can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram for explaining the operation of the present invention.

[Explanation of symbols]

3, 4, 13, 14, 23, 24, 93, 94
Inverter 9, 29, 29, 99 Buffer 11, 21, 9
1 processor

Claims (1)

[Claims] 1. A plurality of arithmetic processors that execute arithmetic operations in parallel; means for outputting first and second flag signals indicating the state of arithmetic processing of the arithmetic processors;
a buffer that outputs each flag signal to an AND circuit;
A parallel arithmetic device comprising: an inverter that outputs an output to an OR circuit for each second flag signal.