BG60791B1 - Multicomputer system - Google Patents

Abstract

The multi-computerized system has parallel physical connections between the processors, which raises effective performance, and the system operates in accordance with the computational model set in the language as a whole. A multicomputer system is comprised of a major computing machine (1) and n processor elements (3) connected to the interface (2) of the main machine (1). The process elements (3) are interconnected by means of a connection subsystem (5), which consists of n identical communication elements (6) each of each processor element (3). The communication elements (6) are connected as peripheral devices to the interfaces (4) of the respective processing elements (3), each of which has parallel communication links (9) consisting of a parallel input channel (7) and a parallel output channel ). The communication links (9) of the respective elements (6) are connected to each other, the number of connections (9) and the way of connection depend on the topology of the multi-system or the connective network realized by the subsystem. Each communication element (6) consists of an interface buffer (10), an internal bus (4), a bus arbiter (11), k sets composed of an input fifo buffer (12), an input channel adapter (13) and an output channel adapter (14), each set corresponding to a separate communication link (9).

Description

1. Field of technology.

The invention relates to a multicomputer system.

2. BACKGROUND OF THE INVENTION

^ · R ...

Parallel computing systems are known, consisting of the same type of processor elements connected to each other by means of an interconnection network. In such systems, the processor elements

are separate subsystems composed of a processor and RAM, which stores programs and data executed (or processed) by the processor element. In some cases, the processor element contains additional functional units - arithmetic (scalar) and / or vector co-processor, communication processor, peripheral controllers, etc. By virtue of these features, the processor elements can be considered as standalone computers, but they function interconnected in the composition of the computing system _and in the context of the problem being solved. That is why such computing systems are sometimes referred to as multicomputer systems ”(ISS).

In a multicomputer system, the solved task is decomposed into sub-tasks (processes) that are distributed between the processing elements and executed in parallel, taking into account the corresponding logical and information links between them. Such a mechanism of operation is adequately described by the computational model known as the Interaction Processor sequence, which is used in one form or another in most of the known ISSs. One of the variants of this model - channel-interacting processes is implemented in the OCCAM language and in the family of microprocessors, the so-called transducers, of Inmos [5].

The information channels connecting the distributed processes are realized using the physical channels (Links), which collectively form the ISS interconnecting network. The structure of this subsystem is described by a graph

of the links whose vertices are identified with the processing elements, and the arcs

- with appropriate physical connections. In the known ISS, several types of graphs have become most widespread: n-dimensional binary cube (hypercube), one-dimensional and two-dimensional lattices. ring and toroidal structures, binary trees, etc. Hypercubes are particularly widely used because of their many advantages, as well as two-dimensional lattices and fertilizers [1-4].

A disadvantage of known systems is the use of consistent physical links, which results in a strong disproportion between the high processing power of processor elements (especially when they contain vector co-processors) and the relatively low data rate between them. IN

as a result, the effective productivity of the ISS decreases - in some cases significantly - as the decrease is greater the greater the relative share of exchange operations in the parallel program implemented. The aforementioned negative effect can be reduced to some extent by appropriately positioning the processes along the processor elements, i. by minimizing interprocessor traffic and by balancing compute and exchange operations in processor elements [3], which, however, significantly complicates ISS programming.

It is an object of the invention to develop an architecture for a multi-computer system with parallel physical links between the processing elements, which would reduce the aforementioned disadvantages.

The system must function In accordance with the computational model laid down

In OCCAM language for possible implementation based on transputer elements.

3. SUMMARY OF THE INVENTION

The object of the invention is solved by a multicomputer system consisting of a main computer and n processor elements that are connected to the interface of the main machine. The processor elements are connected to each other by a connection subsystem composed of n identical communication elements - one for each processor element, wherein the communication elements

elements are connected as peripherals to the interfaces of the respective processor elements. Each of the communication elements has a number of communication links, each consisting of a parallel input channel and a parallel output channel. The Communication Links of the respective elements are interconnected, and the number of Links (of the communication element) and the way of connecting the connections of the respective elements are determined by the topology of the multicomputer system, for example, a hypercube, two-dimensional lattice, fertilizer, binary tree, etc.

The communication element, in turn, consists of an interface buffer,

Inner Bus, Bus Arbitrator, k number of kits made up of Input

FIFO Buffer, Input Channel Adapter and Output Channel Adapter, each set corresponding to a separate communication link. In doing so, the parallel

I-mama Input Channel A connection is connected to the Input of the i-th FIFO buffer whose output is in turn connected to the Input of the i-Input Channel Adapter. The output of the i-th output channel adapter is connected to the parallel output channel of the i-mama communication connection. The input and output channel adapters are connected to the Inner Bus of the communication element, which is accessed by the bus arbitrator. For this purpose the Inputs (on the bus) and the outputs for the permission of the arbitrator are connected to the corresponding outputs and inputs of the channel adapters. The lines on the Inner Bus are connected to the interface buffer of the communication element, and the buffer in turn is connected to the interface of the respective processor element.

The input channel adapter consists of interface buffers for control signals, addresses and data, internal buses for control signals, addresses and data, address decoder, control register, automatic teller, slave register, address register counter, word counter and buffer register. the data. The interface buffers are connected, on the one hand, to the respective Line Types of the Internal Bus of the communication element and, on the other, to the respective Internal Bus of the

adapter. The address register inputs, word counter and slave register are connected to the Inner Data Bus of the adapter. The outputs of the address register are connected to the Internal address bus, and the outputs of the auxiliary register - respectively, to the internal data bus, the outputs of the word counter are connected via a zero combination decoder to one of the

Control inputs. The inputs of the buffer register are connected to the outputs of the corresponding Input FIFO buffer and its outputs to

Internal adapter data bus. Part of the lines of this bus are connected to the corresponding inputs of the control register, and the rest of its inputs are connected to the corresponding outputs of the control automaton; some of the outputs of the same register are connected to the corresponding lines of the Inner control bar, and the other part to the corresponding inputs of the automatic control.

The rest of the inputs and outputs of the control unit are connected to the corresponding signal lines - for control signals and signal-logic conditions, in the context of the algorithm implemented by the machine for the operation of the input channel adapter. The inputs of the address decoder are connected to the internal address bus of the adapter and to the corresponding lines of the internal control bus, and its outputs to the corresponding inputs of the control register, slave register, address register and word counter, which are programmatically accessible.

The output channel adapter consists of interface buffers for control signals, addresses and data, internal buses for control signals, addresses and data, address decoder, control register, control automat, slave register, address register counter, word counter and buffer register. the data. The interface buffers are connected, on the one hand, to the respective line types on the internal bus bar of the communication element and, on the other, to the corresponding internal bus bars of the adapter. The address register inputs, word counter and slave register are connected to the adapter's internal data bus. The exits of

the address register is connected to the internal address bus and the outputs of the slave register - respectively - to the internal data bus; the outputs of the word counter are connected via a zero combination decoder to one of the inputs of the control machine. The inputs of the buffer data register are connected to the internal data bus of the adapter and its outputs to the parallel output channel of the respective communication link. Part of the data bus lines are connected to the corresponding inputs of the control register, and the rest of its inputs are connected to the corresponding outputs of the control automaton; some of the outputs of the same register are connected to the corresponding lines of the internal control bar and the other part to

the corresponding inputs of the control unit. The rest of the inputs and outputs of the control unit are connected to the corresponding signal lines for control signals and signal-logic conditions, in the context of the algorithm implemented by the machine for the operation of the output channel adapter. The inputs of the address decoder are connected to the internal address bus of the adapter and to the corresponding lines of the internal control bus, and its outputs to the corresponding inputs of the control register, slave register, address register and the word counter, which are programmatically accessible.

The advantages of the proposed multicomputer system stem from the use of parallel connections between the processor elements (PE), which eliminates the disproportion between the speed of the calculations in the PE and the data transfer rate between them. In the proposed system, the messaging time between two adjacent elements is an order of magnitude less than that in known systems and is commensurate with the duration of a machine instruction. As a result, the system's productivity is significantly increased and programming is also much easier, as it eliminates to a large extent the need for special measures to minimize communication traffic (in the sense of the requirements ^ mentioned on page 2).

The architecture of the proposed ISS is based on the computational model of Interacting sequential processes (as used in the language

OCCAM). It is characterized by a relatively simple and regular structure, which facilitates the implementation on the basis of serially produced integrated circuits, incl. and microprocessors from the Inmos transputer family. In this case, the serial connections of the transducers can be used as additional (backup) information channels, I / O channels for parallel Data Input / Output, etc.

4. Description of the attached figures.

The invention will be further explained with the accompanying drawings, where:

FIG. 1 illustrates the common organization of a multicomputer system;

FIG. 2 - the organization of the ISS junction subsystem;

FIG. 3 - topology of the connections realized In the connection subsystem, in two common variants - a hypercube (Fig. 3-a.) And a two-dimensional lattice, respectively. tor (Fig. 3b);

FIG. 4 - the structure of the communication element;

FIG. 5 - structure of the input channel adapter;

fie. 6 - structure of the output channel adapter;

FIG. 7 - algorithm of operation of the output channel adapter;

<Leg. 8 - the algorithm of operation of the input channel adapter.

5. Examples of carrying out the invention.

The multicomputer system consists of a mainframe machine 1 and a number of processor elements 3 that are connected to the interface 2 of the mainframe machine 1. The processor elements 3 are connected to each other by a connection subsystem 5 composed of n identical communication elements 6 - one each for each processor element 3, wherein the communication elements 6 are connected as peripherals to the interfaces 4 of the respective processor elements

3.

Each of the communication elements 6 has a k number of parallel communication links 9, each consisting of a parallel input channel 7 and a parallel output channel 8. The communication links 9 of the respective elements 6 are interconnected, the number of connections of the communication element 6 and the method of connecting the respective connections 9 of the elements 6 depend on the topology of the multicomputer system, respectively. of the coupling network realized by the subsystem 5. For example, for the binary p-dimensional cube (Fig. 3-a) k = p = south 2 n, for a two-dimensional lattice, respectively. fertilizer (Fig. 3b) k = 4, for binary trees k = 3 BC The width of the information path w of the input and output parallel channels of the connections 9 is a design parameter, which is determined by both the requirements for higher speed and and the capabilities of the technology used to produce and install circuit modules, the order and number of processors, the connection topology, etc. Depending on the above factors, {8, 16, 32}.

The communication element 6, in turn, consists of an interface buffer 10, an internal bus 4 ', an arbiter of the bus 11, k number of sets consisting of an input FIFO buffer 12, an input channel adapter 13 and an output channel adapter 14, each set corresponding to a separate communication link 9. The parallel input channel 7 of the i-mama link 9 is connected to the input of the i-th FIFO buffers 12, whose output is in turn connected to the input of the i-th input channel adapter 13. The output of the i-th output channel adapter 14 is connected to the parallel output channel 8 of the i-mama com connection 9. Input and output channel adapters respectively. 13 and 14 are connected to the inner busbar 4 'of the communication element 6, access to which is controlled by the bus arbiter 11. For this purpose, the inputs (on the bus) and the outputs for the permission of the arbiter 11 are connected to the corresponding channel outputs and inputs adapters 13 and 14.

The lines on the inner bus 4 'are connected to the interface buffer 10 of the communication element b, and the buffer 10 is in turn connected to the interface 4 of the respective processor element 3.

In the communication element described as such, the channel adapters can be implemented as specialized integrated circuits (see below). FIFO buffers 12 can be implemented based on commercially produced integrated circuitsFIFO memories. They are two-port asymmetric read-only and / or access schemes. recording from the respective ports under the influence of the respective control signals (R, respectively W). The storage part of the scheme is organized as a cyclic buffer, the cells of which are addressed by

at the entrance, respectively. source directory. The pointers are reset using the corresponding signal (reset) and in the process of operation are incremented by the R and W signals at each successive access to the respective ports. The scheme is synchronized with external devices using the Full and Empty flags.

The arbiter 11 should be implemented according to the standard independent-request-rotating-priority arbiter scheme, to ensure that the bus access requests of the channel adapters 13 and 14 are evenly served.

Input channel adapter 13 consists of interface buffers for

control signals 15, addresses 16 and data

17, control signal internal buses 18, addresses 19 and data 20, address decoder

21, control register 22, control machine 23, slave register 24, address register counter 25, word counter 26 and buffer data register 27. Interface buffers 15, 16 and 17 are connected, on the one hand, to the respective types of line the internal bus 4 'of the communication element 6 and, on the other hand, the corresponding internal buses 18, 19 and 20 of the adapter 13. The inputs of the address register 25, the word counter 26 and the slave register 24 are connected to the internal data bus 20 of adapter 13. The outputs of address register 25 are connected to an internal one and address bar 19, outputs of the slave register

24, respectively, to the internal data bus 20, and the outputs of the word counter 26 are connected via a zero combination decoder (not shown in the figure) to one of the inputs of the control automaton 23. The inputs of the data buffer register 27 are connected to the outputs of the respective input FIFO buffer 12 and its outputs to the internal data bus 20 of the adapter 13. Part of the bus lines 20 are connected to the respective inputs of the control register 22, and the other inputs of the register 22 are connected to the corresponding outputs of the steering car at 23. Part of the outputs of the register 22 are connected to the respective lines of the internal control bus 18 and the other part to the corresponding inputs of the control automaton 23. The rest of the inputs and outputs of the control automat 23 are connected to the corresponding signal lines - for control signals and signal-logic conditions, in the context of the automaton 23 algorithm for the operation of the input channel adapter 13 (see. below). In the same context, the purpose of the registers 22, 24, 25,26 and 27 is explained. The inputs of the address decoder 21 are connected to the Internal address bar 19 and the corresponding lines of the internal control bus 18, and its outputs to the corresponding inputs of the controller register 22, slave register 24, address register 25, and word counter 26 that are programmatically accessible.

The output channel adapter 14 consists of interface buffers for control signals 28, addresses 29 and data 30, internal buses for control signals 31, addresses 32 and data 33, address decoder 34, control register 35, control machine 36, slave register 37, address register counter 38, word counter 39 and buffer data register 40. The interface buffers 28, 29 and 30 are connected, on the one hand, to the respective line types on the internal bus 4 'of the communication element 6 and, on the other, to the corresponding internal busbars 31, 32 and 33 of the adapter a 14. The inputs of the address register 38, the word counter 39 and the slave register 37 are connected to the internal data bus 33 of the adapter 14. The outputs of the address register 38 are connected to the internal address bus 32, the outputs of the slave register

37- respectively with the internal data bus 33, and the outputs of the word counter 39 are connected via a zero combination decoder (not shown in the figure) to one of the inputs of the control automatic machine 36. The inputs of the data buffer register 40 are connected to the internal data bus 33 of the adapter 14, and its outputs - to the parallel output channel 8 of the respective communication link

9. Part of the bus lines 33 are connected to the respective inputs of the control register 35, and the other inputs of the register 35 are connected to the corresponding outputs of the control machine 36. Part of the outputs of the register 35 are connected to the corresponding lines of the internal control bus 31 and the other part - with the corresponding inputs of the controller 36. The rest of the inputs and outputs of the controller 36 are connected to the corresponding signal lines - for control signals and signals - logical conditions, in the context of 36, an algorithm for the operation of the output channel adapter 14 (see below). In the same context, the purpose of registers 35, 37, 38, 39 and 40 is explained. The inputs of the address decoder 34 are connected to the internal address bar 32 and the corresponding lines of the internal control bar 31, and its outputs to the corresponding inputs of the controller register 35, slave register 37, address register 38, and word counter 39, which are programmatically accessible.

From the description of the outlet channel adapter 14, it can be seen that in structural terms it is almost identical to the inlet channel adapter 13, except for the intended purpose, respectively. how the buffer registers of the data (27, respectively 40) are connected and the structure of the control machines 23, respectively. 36 that implement different, albeit symmetric, algorithms (see below).

6. Application of the invention. - '',

The functioning of a multicomputer system is determined by the computational model set out in it, defined in the context of the OCCAM language. It consists in the parallel execution of a plurality of interacting computing processes housed in the respective processing elements of a multicomputer system. The interaction of the processes is reduced to a synchronized exchange of messages by the mechanism of the so-called symmetric rendering [5]. For this purpose, operators are used to transmit resp. to receive messages from the Species:

channel! χ, respectively, channel? in,

Indicating the channel through which communication is made between the source process (A) and the receiver process (B). The first operator specifies the variable χ, x is the domain (A) containing the message, respectively. the starting address and the size of the corresponding array In the address space of process A Similarly, the second operator specifies the variable y, y is domain (B), respectively. the starting address and size of the corresponding array B in the address space of process B where the received message is recorded. In the particular case, the message size may be zero, at which

The interaction between processes A and B is reduced to mutual synchronization by rendezvous.

The implementation of the mechanisms discussed above depends essentially on the location of the correspondent processes. If they are located in the same processor element (Node), communication between them is accomplished through a programmatic path and the information channel is implemented as a cell of RAM shared by both processes [5].

When the processes are located in two adjacent Nodes, the interaction between them is carried out by means of a physical channel, which is placed in accordance with the logical channel channel indicated in the transmission operators, respectively. for receiving data, the physical channel is formed by connecting the output channel 7 to the Input channel 8 of the respective communication links 9 of the corresponding nodes 3. In this case, an information path is realized with the following configuration:

{Processor RAM 3 -> Output Channel Adapter 14-> Parallel Output Channel 8 {Source {Parallel Input Channel. Input FIFO Buffer 12 -4 Input Channel Adapter 13—> RAM of the Processor Element ³ ) Receiver whose operation is controlled together with the channel adapters 14 and 13 of the processor elements 3, being respectively the source and receiver of the information.

In this case, the implementation of the channel! x, resp. channel? y, activated in processes A and B (respectively - source and receiver of messages) proceeds in the following sequence:

1. The registers of the output channel adapter 14, respectively. Input channel adapter 13. In particular, the start address of the array x (respectively y) is loaded in the address register 38 (25) and the dimension x is loaded in the word counter 39 (26).

(resp. y). In the auxiliary registers 37 (24) are loaded for temporary storage the directories to the workspace pointers of the processes A or. C, immediately before they are deactivated (See section 3).

2. Transmission operations, respectively. receiving messages by loading the corresponding code combinations In the control registers 35, respectively, 22.

3. Processes A and B are self-locking, ie. go offline. From here on, the control of the data exchange between processes A and B (respectively between the nodes in which A and B are located) is effected through a circuit, using the channel adapters 14 and 13 and the controllers integrated therein.

vending machines 36 and 23, the latter implement channel algorithms for channel operators? x and channel? y, shown respectively in FIG. FIG. 7 and 8. The algorithms mentioned are symmetric and should be considered in conjunction with each other.

The interaction between the channel adapters proceeds in three stages: 1)

Mutual synchronization of adapters; 2) Exchange of the message in the mode of direct access to the memory of the node - source, respectively. a receiver node with intermediate message buffering in the input FIFO buffer 12 of the receiver node; 3)

End of operation signaling.

The execution of the channel procedures begins with the presence of requests respectively for the transmission of a message (Tr = 1) and the reception of a message (Re = l) formed in the control registers 35 and 22 of the channel adapters 14 and 13 at the start of the transmission, resp. . for acceptance. It then proceeds to establishing the readiness for communication on the other side. To do this, the following actions are performed:

- The receiving party first clears the received transmission request (Tr: = 0) and simultaneously fictitiously records data in the receiving party's FIFO buffer 12 (W: = 1). This automatically causes the flag E (empty) to be reset, which causes the algorithm to loop, while E = 0, respectively. pending confirmation on the opposite side (E = 1).

- In the host country, the reset of signal E is first waiting, ie. receiving a transmit readiness signal from the opposite side. IN

the response to this signal is reset to the receive request (Re: = 0) and at the same time a dummy reading is made from FIFO buffer 12, (R: = 1). This results in the restoration of the single value of flag E, which is interpreted as a confirmation signal, respectively. readiness for acceptance.

In this way, a kind of rendezvous between the channel adapters and the 13 is realized, which leads to their synchronization just before the next stage begins (message exchange).

The message exchange starts in the same way in the transmitting and receiving countries - the initial contents of the word counter (DB = 0?) Are checked and at zero meaning, ie when exchanging a blank message, it goes to the end of the procedure (signaling the end of the operation). Otherwise, a request signal is generated on the highway 4 'of the respective communication element 6, which is fed to the respective arbitrator 11, after which the arbitrator's permission to use the highway is waited.

Further, adapters 14 and 13 function differently, realizing two parallel-flowing and complementary processes: 1) Sequential transfer of message words from the memory of the source node to the input FIFO buffer 12 of the receiver node; 2) Sequential transfer of the information words from the FIFO buffer 12 to the host node RAM. Moreover, both processes are executed simultaneously and asynchronously, with the combination of elementary operations of the type: Read source mem, Write FIFO; Read FIFO, Write dest mem. At the same time, synchronization is foreseen, which excludes the possibility of improper interactions with FIFO buffer 12 and, in particular, the recording of information in full FIFO buffer, respectively. read information from an empty buffer. For this purpose, flags F and E (full and empty) are used, whose single (zero) values block (allow) access to the FIFO buffer 12 by the adapters 14 and 13 of the transmitter or receiver, respectively.

In this case, logic is implemented using the additional feature (denoted by A in both algorithms), which enables the motorway 4 'to be released during the time that the adapter 14 (respectively 13) is in the standby state until buffer 12 is still full (F = 1), respectively. blank (E = 1).

The transfer of data from the RAM to the source node in the FIFO buffer 12 and accordingly - from the FIFO buffer 12 to the memory of the host node - is carried out by means of the data buffers 40 (27), address registers - counters 38 (35) and word counters 39 (26) of the respective adapter pair 14 and 13, according to the algorithms shown in FIG. FIG. 7 and 8. They are optimized for performance by appropriately grouping and reconciling the micro-operations included in the cyclic sections. However, this requires that the address register 25 be initialized with the starting address of the receiver array, reduced by 1.

The message transfer ends with resetting the word counter 39 (26), after which the interacting channel adapters 14 and 13 release the system highways 4 'into the respective communication elements 6.

For both adapters, the channel procedure ends by signaling the respective processor for the end of the operation. For this purpose, an interrupt signal is generated, the processing of which is reduced to the reactivation of the respective process. One way (if the system is built with transplants) is to read the process workspace directory from slave register 37 (24) and include it in the list of active processes of the respective processor.

The examinations made illustrate the functioning of one information channel resp., The Interaction between the respective pair of adapters. In the general case, the system operates simultaneously and independently r information channels, r <R, where R is the total number of channels determined by the system topology. This is Possible, Due to the distributed control of the information channels, realized through the control devices 36 (23) of the adapters 14 (13).

and output channels, ⁱⁿ the one processing element, can lead to conflicts in the interaction with RAM of the element, respectively. when using Highway 4 (4 *). These are permitted by the highway arbitrator

11, Included In the communication element 6.

The mechanisms considered provide interaction between processes located in the same node or 8 different but adjacent nodes. In general, the implementation of arbitrary (by nature) parallel algorithms requires the ability to communicate between computational processes located in non-adjacent ones.

Nodes. In multicomputer systems using the computational model of language

OCCAM, such Interaction is programmatically implemented by means of an additional communication layer (so-called harness) in which message routing takes place.

Claims (4)

Claims 1. A multicomputer system consisting of a master computer. and n are the number of processor elements connected to the interface of the main machine _h , the processor elements being interconnected by a coupling subsystem, characterized in that the coupling subsystem (5) consists of n identical communication elements (6) one for each processor element (3), wherein the communication elements (6) are connected as peripherals to the interfaces (4) of the respective processor elements (3), each having a number of parallel communication links ( 9), each consisting of a parallel Input channel (7) and a parallel output channel (8), and the Communication Links (9) of the respective elements (6) are interconnected, with the number of Links (9) of the communication element (6) and the method of connecting the respective Connections (9) of the elements (6) depend on the topology of the multicomputer system, respectively. of the interconnector implemented by the subsystem (5), e.g. hypercube, two-dimensional lattice (fertilizer), binary tree, etc. Multicomputer system according to claim 1, characterized in that the communication element (6) consists of an interface buffer (S), an internal bus (4 '), a bus arbiter (11), k of a number of sets consisting of FIFO input buffer (12), input channel adapter (13) and output channel adapter (14), each set corresponding to a separate communication link (9), wherein the parallel input channel (7) of the i-mom Link (9) ) is connected to the Input of the i-th FIFObuffer (12), whose output is in turn connected to the Input of the i-th Input channel adapter (13), and the output n the i-th output channel adapter 14 is connected to the parallel output channel (8) of the i-mama communication link (9), the input and output channel adapters, respectively. (13 and 14) are connected to the inner bus (4 ') of the communication element (b), the access to which is controlled by the arbitrator (11), for this purpose the inputs (request) (bus) and the outputs for the permission of the arbitrator (11) ) are connected to the corresponding outputs and inputs of the channel adapters (13 and 14), the lines on the internal bus (4 ^ are connected to the interface buffer (10) and the latter is in turn connected to the interface (4) of the respective processor element (3). ). Multicomputer system according to claims 1 and 2, characterized in that the input channel adapter (13) consists of interface buffers for control signals (15), addresses (16) and data (17), internal control bus bars (18), addresses (19) and data (20), address decoder (21), control, register (22), control, machine (23), slave register (24), address register counter (25), counter words (26) and a data buffer (27), wherein the interface buffers (15, 16 and 17) are connected, on the one hand, to the respective types of bus lines ( 4 ') of the communication element (6) and, on the other hand, to the corresponding internal buses (18, 19 and 20), the inputs of the address register (25), the word counter (26) and the auxiliary register (24) are connected to the internal data bus (20), the outputs of the address register (25) are connected to the internal address bus (19), and the outputs of the slave register (24), respectively, to the internal data bus (20), the outputs of the word counter (26) are connected via a zero combination decoder (not shown in the drawing) to one of the inputs of the control machine (23), the inputs b the data register (27) is connected to the outputs of the corresponding input FIFO buffer (12) and its outputs to the internal data bus (20), part of the bus lines (20) are connected to the corresponding inputs of the control register (22) and the other inputs of the register (22) are connected to the corresponding outputs of the automatic control unit (23), part of the outputs of the register (22) are connected to the corresponding lines of the internal control rail (18) and the other part to the corresponding inputs of the control unit (23), the rest of the inputs and outputs of the the control unit (23) is connected to the corresponding signal lines - for control signals and signal-logic conditions, in the context of the algorithm implemented by the machine (23) for the operation of the input channel adapter (13), the inputs of the address decoder (21) are connected with the internal address bar (19) and the corresponding lines of the internal control bar (18) and its outputs with the corresponding inputs of the control register (22), the slave register (24), the address register (25) and the word counter (26) that are programmatically accessible. Multicomputer system according to claims 1 and 2, characterized in that the output channel adapter (14) consists of interface buffers of the control signals (28), addresses (29) and data (30), internal buses for the control signals ( 31), addresses (32) and data (PZ), address decoder (34), control register (35), automatic control (36), slave register (37), address register counter (38), word counter (39) ) and a buffer data register (40), wherein the interface buffers (28), (29) and (30) are connected, on the one hand, to the respective types of bus lines and (4 ') of the communication element (6) and, on the other hand, to the respective internal buses (31, 32 and 33), the inputs of the address register (38), the word counter (39) and the slave register (37) are connected to the Internal data bus (33), the outputs of the address register (38) are connected to the internal address bus (32), the outputs of the slave register (37) respectively, to the Internal data bus (33), and the outputs of the counter of words (39) are connected via a zero combination decoder (not shown in the drawing) to one of the inputs of the control machine (36), the inputs n the data buffer register (40) is connected to the internal data bus (33) and its outputs to the parallel output channel (8) of the respective communication link (9), part of the bus lines (33) are connected to the corresponding the inputs of the control register (35), and the other inputs of the register (35) are connected to the corresponding outputs of the control automaton (36), some of the outputs of the register (35) are connected to the corresponding lines of the internal control bus (31), and the other part - with the corresponding inputs of the automatic control unit (36), the remaining hours The inputs and outputs of the control unit (36) are connected to the corresponding signal lines-for control signals and signal-logical conditions. In the context of the algorithm implemented by the machine (36) for the operation of the output channel adapter (14), the inputs of the address the decoder (34) is coupled to the internal address bus (32) and the corresponding lines of the internal control bus (31) and its outputs to the corresponding inputs of the control register (34), the slave register (37), the address register (38) and the word counter (39), which are prog multi-accessible.