JPH04133155A - Digital computer - Google Patents

Abstract

PURPOSE:To improve the processing speed by providing a bus arbitrating/ selecting circuit which is provided with at least two data buses, and does not permit an access request signal at the time when the data buses are both being used, in a system provided with plural central processors, a shared memory and an input/output device. CONSTITUTION:A master CPU 1, a slave CPU 2, a shared memory 3 and an input/output device 4 are connected each other to common data bus (B) 14 through bus buffers 5 - 8, and connected to a common data bus (A) 13 through bus buffers 9 - 12. A bus arbitrating/selecting circuit 15 receives an access request signal of the CPUs 1, 2, and outputs a gate signal for activating two of the bus buffers 5 - 8 or two of the bus buffers 9 - 12 in order to realize to give and receive data. In such a way, a simultaneous access of the CPUs 1, 2, the memory 3 and the input/output device 14 can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital computer that is equipped with at least two central processing units and performs calculation processing.

(Prior Art) In recent years, there has been a remarkable improvement in the processing power of digital computers, and the processing speed of their central processing units, which are their main components, is increasing year by year. However, in fields that require a huge amount of calculations, such as fields that require complex scientific and technological calculations, or structural analysis, a single central processing unit is still not sufficient to achieve the necessary computational power. The current situation is that this is not the case. Therefore, parallel processing using a plurality of central processing units is generally performed as an easy method to improve the arithmetic processing capacity of a digital computer.

FIG. 3 is a diagram illustrating such a conventional parallel processing method. The figure shows a case where there are two central processing units to simplify the explanation, and 1 is a main central processing unit (hereinafter referred to as a mask CPU), and 2 is a subordinate central processing unit (hereinafter referred to as a slave CPU).

Further, 3 is the master CPUI and the slave CPU
2, the shared memory accessed by the two CPs
Stores U's programs and data. Further, 4 is an input/output device such as a keyboard, which is accessed by the masks CPt, il and the slave CPU 2. The mask CPU 2, slave CPU 2, shared memory 3, and input/output device 4 are mutually connected to a common data bus 20 via bidirectional three-state data bus buffers 16, 17, 18, and 19. Note that the bidirectional three-state data bus buffers 16, 17, 18, and 19 are as described above.
The influence of the common data bus 20 activated for data transfer between any two of the master CPU 2, the slave CPU 2, the shared memory 3, and the input/output device 4 is
This is set up so that it does not extend to anything unrelated to the exchange of data. Reference numeral 21 denotes an arbitration circuit to which access request signals from each of the master CPU I and slave CPU 2 are input, and in order to realize data transfer, one of the two-way three-state data bus buffers 16, 17, 18, and 19 is input. Gate signals for activating the two are output, and if the access request signal described above is generated at the same time, arbitration is performed to grant access permission in chronological order.

The digital computer configured as described above operates as follows. Figure 4 shows the mask CPUI and slave CPU2.
FIG. 5 is a timing chart of the processing of a series of closed programs (hereinafter referred to as tasks). A gate signal for activating any two of the bus buffers 16, 17, 18 and 19 as required, and an access end signal for notifying the CPU that has output the access request signal that the access has ended. It represents timing.

First, as shown in FIG. 4, the master CPU 1 executes, for example, task 1 among the programs stored in the shared memory 3. At this time, the slave CPU 2 also executes the program stored in the shared memory 3. Running. This is the state of waiting for a task request. This is normally a state of waiting for a request from the master CPUI, and is waiting for an instruction to be stored at a specific address in the shared memory 3.

In order to have the slave CPU 2 execute a certain closed program (task 2 in this case), the master CPU 2 stores the start address of the task 2 and necessary parameters in the shared memory 2.
After storing the instruction in a predetermined area in the shared memory 3, the execution request instruction is written as a task request to the instruction storage address in the shared memory 3. Thereafter, the slave CPU 2 accesses the shared memory 3 in order to execute the requested task 2, and also accesses the input/output device 4 as necessary within task 2. During this time, the master CPUI executes the subsequent process (task 3).

That is, at this point, two CPUs 2 and 2 process task 2 and task 3 in parallel.

When the execution of task 2 is finished, the slave CPU 2 notifies the master CPU 2 of this through an interrupt.
The system returns to the request waiting state. Similarly, task 4 and task 5 are executed, and then the master CPUI executes task 6. Here, master CPUI, slave CPU2,
Since the shared memory 3 and the input/output device 4 are connected by one common data bus 20, this common data bus 20
It is necessary to arbitrate which CPU should use the .

Therefore, as shown in FIG. 5, the arbitration circuit 21 inputs, for example, an access request signal to the shared memory 3 of the master CPU 1 (FIG. 5(a)b), and when it accepts this, it transmits the gate signal in both directions. The signal is supplied to the state data bus buffers 16 and 18 to activate them (portion (b) in the same figure).

When the access by the master CPU 1 is completed, the arbitration circuit 21 supplies a service end signal to the master CPU ((c) c), thereby ending the access of the mask CPU 1 to the shared memory 3 ((a) ) 2) During this period, for example, even if an access request signal to the input/output device 4 of the slave CPU 2 is supplied to the arbitration circuit 21 (same, (cl)
e), the user is forced to wait until the common data bus 20 used for access by the master CPUI is released (see (b)). and common data bus 20
After the common data bus 2 is released, the arbitration circuit 21 outputs a gate signal for activating the bidirectional three-state data bus buffers 17 and 19.
The access of the slave CPU 2 to the input/output device 4 is realized through the CPU 0, and the access of the slave CPU 2 is completed in the same way as in the case of the master CPU. The arbitration circuit 21 operates as described above.

Manage the use of the common data bus 20.

(Problem to be solved by the invention) As described above, in the above conventional configuration, all the constituent elements are
For example, mask CP
When UI uses shared memory 3, slave C
Even if the PU 2 tries to use the input/output device 4, it has a big problem in processing because it is forced to wait.

An object of the present invention is to provide a digital computer that eliminates the conventional processing problems of digital computers as described above.

(Means for Solving the Problems) The present invention achieves the above object by providing a plurality of central processing units, a shared memory commonly used by the central processing units,
In a digital computer equipped with an input/output device controlled by the central processing unit, which includes at least two data buses, when the central processing unit accesses the input/output device or the shared memory, any of the above data buses is used. This is achieved by a digital computer equipped with a data bus arbitration selection circuit that does not allow access request signals until one of the data buses becomes free.

(Function) With the above-described configuration, the present invention allows the bus arbitration selection circuit to arbitrate so as to actively use the vacant shared data bus, so that the CPU is more efficient than the conventional configuration.
This eliminates the need for computers to wait due to bus contention, resulting in a digital computer capable of faster parallel processing.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of a digital computer according to an embodiment of the present invention, in which 5 to I2 are bidirectional 3-state data bus buffers, 13 is a first common data bus (
A), 14 is a second common data bus (B), 15 is a bus arbitration selection circuit, and the explanation of other symbols refers to the explanation of FIG. 3.

The present invention thus provides mask CPUI, slave CP
U2, shared memory 3, and input/output device 4 are mutually bidirectional 3
It is connected to the second common data bus (B) 14 via a state data bus buffer 5°6.7.8, which also has a bidirectional three-state data bus buffer 9. to, 11.
12 to a first common data bus (AH3), where a bidirectional three-state data bus buffer 5
, 6, 7, 8, 9, 10, and 11.12 are activated to exchange data between any two of the master CPU 2, slave CPU 2, shared memory 3, and input/output device 4. The common data bus (AH
This is to prevent the influence of 3 and the common data bus (B) 14 from affecting anything unrelated to data exchange. Reference numeral 15 designates the bidirectional 3-state data bus buffer 5 to which access request signals from the master CPU I and slave CPU 2 are input, and to realize data transfer.
, 6, 7.8, or the bidirectional three-state data bus buffer 9.10. This is a bus arbitration selection circuit that outputs a gate signal to activate any two of the common data buses (A) and (B). If access request signals are generated from other CPUs at the same time, arbitration is performed for the unused common data bus, permission to use it is output, and multiple CPUs waiting here are
Arbitration is performed for the PU to use the earlier available common data bus of the common data bus (A) 13 and the common data bus (B) 14.

The digital computer configured as described above operates as follows.

Here, the flow of program execution is the same as that shown in FIG. 4 as in the conventional example. In addition, FIG. 2 shows each of the above-mentioned CPUs.
an access request signal from the bidirectional three-state data bus buffer 5, which is output from the bus arbitration selection circuit 15;
Gate signals and access request signals for activating any two of the bidirectional three-state data bus buffers 9.10.11.12 or any two of the bidirectional three-state data bus buffers 9.10.11.12. 12 is a timing chart of an access end signal for notifying the CPU that outputs the access that the access has ended. Now, if the slave CPU 2 accesses the input/output device 4 while the master CPUI is accessing the shared memory 3, the mask CPtJ1. Slave CPU2. The shared memory 3 and the input/output device 4 share a common data bus (A).

(B) Since they are connected by two buses, there is no need to arbitrate which CPU will use the bus. Therefore, as shown in FIG. 2, the bus arbitration selection circuit 15 receives, for example, an access request signal from the master CPUI to the shared memory 3 and accepts it (as shown in FIG. 2(a)).
B), common data bus (A) 13 and common data bus (
Since neither B) 14 is used, for example, the common data bus (A) 13 is selected and a gate signal is supplied to the bidirectional 3-state data bus buffers 9 and 11 to activate them. b) mouth). This allows the master CPUI to access the shared memory 3 via the common data bus (A) 13. and master CPUI
When the access is completed, the arbitration circuit 21 supplies a service end signal to the master CPL 71 ((c) c),
The access of the master CPUI to the shared memory 3 is terminated ((b) 2, (C) e). And during the above
For example, when an access request signal to the input/output device 4 of the slave CPU 2 is supplied to the bus arbitration selection circuit 15 (
To d), the common data bus (B) 14 which is not used at that time is selected, and the bus arbitration selection circuit 15 outputs a gate signal for activating the bidirectional 3-state data bus buffers 6 and 8. (ibid., (e) g). In this way, the master C via the common data bus (B) 14
Access to the shared memory 3 of the PUI is performed.

As described above, in the present invention, the bus arbitration selection circuit 15 controls the access operation between the mask CPUI and the shared memory 3 via the common data bus (A) 13 and the common data bus (B) 1.
This realizes simultaneous access operation between the slave CPU 2 and the input/output device 4 via the slave CPU 2 and the input/output device 4.

As described above, according to this embodiment, by providing a bus selection arbitration circuit and two common data buses in a digital computer, data bus contention can be suppressed and faster parallel processing without waiting time can be achieved. be able to.

Although this embodiment uses one master CPU and one slave CPU, it is also possible to use a plurality of slave CPUs.

(Effects of the Invention) As is clear from the above explanation, the present invention enables simultaneous access from multiple CPUs by providing a bus selection arbitration circuit and multiple shared data buses in a digital computer. Since it has the effect of realizing high-speed parallel circuits due to its processing capacity, it can be used to achieve useful effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
The figure is a timing diagram showing the operation of Fig. 1, Fig. 3 is a configuration block diagram of a conventional example, Fig. 4 is a flow chart explaining the operation of Fig. 3, and Fig. 5 is a diagram showing the timing of Fig. 4. be. 1...Master CPU, 2...Slave CPU
, 3... shared memory, 4... input/output device,
5, 6, 7, 8, 9, 10, 11°12, 16.17.
18.19... Bidirectional 3-state data bus buffer, 13... Common data bus (A), 14... Common data bus (B), I5... Bus arbitration selection circuit,
20...Common data bus, 21...Arbitration circuit. Patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] A digital computer equipped with a plurality of central processing units, a shared memory commonly used by the central processing units, and an input/output device controlled by the central processing unit, the digital computer having at least two data buses, the input/output device or if shared memory is accessed by the central processing unit,
A digital computer comprising a data bus arbitration selection circuit that does not allow access request signals until one of the data buses becomes free when all of the data buses are in use.