JP3039918B2 - Processor system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention
A multiprocessor system or multiprocessor
It relates to a suitable processor system. 2. Description of the Related Art Conventionally, a multi-processor system
Is disclosed in, for example, JP-A-59-208666.
Like one CPU and memory, the other processor element
Bus and switches that operate as master and slave
Become. Such a single CPU processor element
In a multi-processor system consisting of
No problem as far as dedicated task processing with little disturbance is concerned
Is required for systems such as intelligent control processing
As contents become more sophisticated, databases and system
Status management, knowledge based on database and sensor information
Processing system configuration, multiple interrupt processing, multi-job function
It is necessary to provide background processing support.
Real-time multi-tasking, multi-job
On a high-end operating system that can support
Writing and executing those processes in a high-level language is one thing.
General. [0003] The above-described conventional multi-device
・ Mainly for high speed in processor systems
Real-time control processing is supported by multi-tasking.
Task is one of the tasks
Switch overhead and parallel processing schedule
Is that fine-grained parallel processing cannot be performed due to
It is the current situation. Therefore, the supervisor system
Parallel processing of intelligent processing system by super minicomputer etc.
In many cases, the system is separated from the control processing system.
Communication between the column processing system and the intelligent processing system tends to be sparse.
And manage the local internal status of each processor.
Requires operating system overhead
Characteristics such as decentralized intelligent processing and decentralized system management
Will not be utilized, resulting in a substantial decrease in price / performance ratio.
And according to the expansion of the processing performance of the control processing system
Of processing performance of intelligent processing system and communication through between two systems
There is a problem that it is difficult to improve the put. Therefore,
When the speed of the control loop of the control system increases,
Relatively large data is exchanged with the control processing system at high speed
And the above-mentioned problems are significant
And the price / performance ratio will be significantly reduced.
You. [0004] An object of the present invention is to provide a mask suitable for general-purpose processing.
Multi-processor or single-processor systems
System's substantial processing performance in a well-balanced and efficient manner
It is an object of the present invention to provide a processor capable of causing the processor to operate. [0005] The present invention provides a common bus,
A first processor for processing information and a second processor for processing information;
Two processors, the first processor and the second processor.
Switch for switching to the processor and connecting to the common bus.
Switch means, the first processor and the second processor.
Memory means connected between the
And the second processor are the first processor or the second processor.
Store information from one of the processors and the other processor.
Provided to enable the information to be referenced by the
A processor system characterized by the above is disclosed. the above
According to the invention, local information between two processors
The exchange is performed by two processors without going through a common bus.
Can be performed through the intervening memory means
Therefore, contention on the common bus is reduced. Also, when exchanging information
And the two processors store information in memory means.
Do not bind the other processor to
To improve information processing speed
be able to. Also, a main process such as a control operation,
Backup of main processing, for example, system management
Is separated from background processing such as
Assigns main processing to the processor and transfers to the second processor.
You may want to assign a background process. Background
Processing is mostly local to the two processors.
Closed by communication, especially improved information processing speed
Can be made. The present invention comprises a first common bus and a first common bus.
Resources shared by multiple common buses and multiple
Unit and the second common corresponding to each processor unit
Bus and each second common bus in parallel with the first common bus
Connection of each second common bus for selecting whether or not to connect
A first switch provided on the system, and a first switch
A control line for carrying ON / OFF signals and more
And each of the processor units includes a first row.
First CPU for processing information supplied via Calvas
And process information supplied via the second local bus.
A second CPU, and one of the first and second CPUs.
Stores the information from the other CPU and the other CPU can refer to the information
Connected to the first and second CPUs.
The memory and the first or second CPU request the first
CPU and self-processor via local bus
Connection to the second common bus corresponding to the unit or the second row
A second CPU and this second common bus
And a second switch for connecting the
Disclose a sessa system. Further, the present invention provides the first common
Buses and shared resources leading to the first common bus
Compatible with each processor unit
A second common bus, and each second common bus to a first common bus.
Each second to select whether to connect to the bus in parallel or not
A first switch provided on a shared bus route of
Control line for applying the ON / OFF signal of the switch
And each of the above processor units
Processes information provided via the first local bus.
Supplied through a first CPU and a second local bus.
A second CPU for processing information stored in the first and second CPUs;
The information from one of the PUs is stored and the other CPU stores the information.
The first and second CPUs for enabling information to be referred to
Connected to the memory and the first local bus at all times
Via the second CPU and its own processor unit
Connection with the common bus of the first or second CPU.
Upon request, the second local bus
A second switch for connecting the CPU to the common bus
And a processor system including the following. [0006] The present invention provides a first common bus and a first common bus.
Shared resources connected to the bus and multiple processor units
And a second common bus corresponding to each processor unit
And connecting each second common bus in parallel to the first common bus.
Route of each second common bus for selecting whether or not to run
First switches provided above and ON of each first switch
And a control line for carrying a / OFF signal.
And each of the processor units has a first local
A first CPU for processing information supplied via the bus,
Processing information supplied via the second local bus
2 CPUs and one of the first and second CPUs.
And store the other information so that the other CPU can refer to the information.
Memo connected to the first and second CPUs for storing
And the second CPU normally via the first local bus
Connection with the second common bus corresponding to the own processor unit
Connection, and the second or
Via the local bus of the second CPU and the common bus.
And a second switch for connection with the switch.
In the processor unit, the first and second switches are
Via the first local bus to the first and second common buses.
Processor unit when connected via the
In the example, the first CPU is connected to the first and second common buses and the first CPU.
Control operation of shared resources via the local bus of
The second CPU is used for intelligent processing and system management of the first CPU.
Processor that performs background processing such as
Disclose the system. FIG. 1 is a block diagram of a processor according to the present invention.
Two CPUs provided in the processor element
Hardware architecture that works like a processor
Provide a tua. In addition, control processing system and database
Focus on high independence of intelligent processing system based on sensor information
To assign a control processing system to the main processing system of the main CPU.
Control operation etc. with other base processor elements
It is executed by tightly coupled parallel processing with
Strength of background elements such as system management and knowledge processing
Background processing of the main CPU as an intelligent processing system
Command processing system and background CPU,
Back up the control processing system of the main CPU. in addition
Therefore, task switch overhead and parallel processing
As much as possible,
Two processing systems can be operated in parallel with high efficiency
Therefore, by adding the processing performance of the two units,
To improve the processing performance of the Sessa element by a factor of two
Combining multiple base processor elements
Twice that of conventional multi-processor systems
Overall processing performance and base processor elements
The balance between the control processing system and the intelligent processing system in response to expansion
And enhanced processing performance. Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Will be explained. FIG. 1 shows the configuration of the processor of the present invention.
So, in this figure, the multi-processor system
Base processor element (BPE)
1 has two CPUs 15 and 16 (CPU 0 and
CPU 1), and the CPU 15
Port RAM (DPR) 1 as a communication mechanism for
7 and other base processor elements (BPE)
One of the two CPUs to communicate with
To the BPE local bus 12 which is a common bus between
Conflict caused by the common bus switch control circuit 22
Multiplexed bus buffer switch controlled
A common bus switch 24 comprising a
Between U15,16 and base processor element
(BPE). Ma
In addition, the two CPUs 15 and 16 each have a local memory.
It has Mori 18, 20 and local I / O 19, 21, etc.
Usually, they can operate independently. Also, between CPUs
Dual port RAM (DPR) that supports communication
The feature of 17 is for communication between the CPUs 15 and 16 of each other.
It has interrupt lines 32 and 33,
Communication function between CPU 15 and 16 with low overhead
Can be mentioned. Base processor element
Base processor E on the local bus 12 of
Local memory 6 and local I / O 7 are connected
As well as other base processor elements
Configure a common bus line for the
System 9 to which the system 9 and the system shared I / O 10 are connected.
System bus switch 8 for connecting to
Have been killed. This system bus switch 8 is
Access to the system bus 14 by the
Bus arbitration process for access
Use shared resources on the bus 14 or use other base
Performs communication processing with the Sessa element and
Parallel processing can be performed between the processor elements.
ing. FIG. 5 shows a dual port RAM (DPR).
Figure 17 shows the hardware block diagram of
The dual port RAM (DPR) 17 has two C
Considered as a shared memory shared between PUs 15 and 16
And dual port RA of two CPUs 15 and 16
Access to M (DPR) is indicated by reference numerals 77 to 80.
Using the access request signal and access permission signal of the processor
Arbiter 60 and mediator from arbiter 60
Buses 64, 6 from the CPU according to the
A bus switch 61 for switching 5 to an internal bus 66;
62 and the address and control lines of the internal bus 66 are decoded.
A memory enable signal 81, an interrupt control signal 73,
74 and a CPU 67
To set and reset interrupt signals 32 and 33 to
Control signals 73 and 7 generated by the decoder 67
4 flip flops 68, 69 etc.
Consists of Characteristic dual port RAM (DP
R) The interrupt function for CPU communication is a dual port
Interrupt to CPU0 at a specific address in RAM (DPR)
Registers that generate and registers that generate interrupts to CPU1
And provide them to each other's CPU at the same time.
Instruction register to send and receive instructions and interrupt
And generation are performed simultaneously. CPU1 transmits instructions to CPU0
For example, when CPU 1 executes CPU 1
Set the instruction attribute to be set in its own register, etc.
To the CPU0 on the dual port RAM (DPR)
Instruction register (interrupt generation register)
The decoder 67 accesses the instruction register to CPU0.
The inside of the dual port RAM (DPR)
CPU knows by monitoring and decoding bus 67
Access signal for instruction register access signal pulse to 0
No. 73 and send the flip-flop 68
The value of the inverted output (ie, Q bar; the same applies hereinafter) signal 70
Switch. The initial state is set by the RESET signal 72.
Q is set to HI and the inverted output of Q is set to LO.
In the above operation, LO is output to Q and HI is output to the inverted output of Q
Interrupt signal to CPU0 that is active
30 becomes active for CPU0. Next, the CPU 0 that has accepted the interrupt
Instructions to be executed in the interrupt service routine
Refer again to the instruction register to CPU0 to obtain
When the specified instruction is read, the decoder
67 monitors the access status and issues a command to CPU0.
Command register access signal pulse to access signal 73
Output to the flip flop 68 and use HI
The inverted output 70 of a certain Q is latched and HI is output to Q.
That is, the interrupt generation line 32 to the CPU 0 is deactivated.
Live. Generate a series of interrupts by the above sequence
Operations from raw to acceptance and software-based command transfer
Related operations simultaneously and with minimal overhead
can do. Returning to FIG. 1, the base processor element
Bus 28 of CPU0 or CPU1 in the client (BPE) 1
Or 29 is selected, and CPU0 and CP are selected.
A BPE local bus 12 which can be regarded as a shared bus of U1
Bus switching control (bus switch) for output
The common bus switch 24 is connected to the shared bus as described above.
A switch control circuit 22 and a switch controlled by the switch control circuit 22
And a multiplex bus buffer 23. So
The bus switch control of CPU0 is the master, CPU1
In the case where is a slave, the NOR circuit shown in FIG.
83, a shared bus switch including a NAND circuit 84
Performed by logic. Its characteristic bus switch
The control sequence will be described with reference to the time chart of FIG.
You. First, the local buses 28, 2 of the two CPUs
The right to acquire 9 is always on each CPU side,
Is not infringed by Dehaisu (Fig. 2
A, H). CPU0 shared bus (BPE local bus 1
2) The access request is always active as shown in FIG.
The shared bus access request of CPU 1 is
2 always active as needed as shown in I
You. That is, except when the CPU 1 has acquired the shared bus
, The CPU0 always acquires the shared bus. In FIG.
In the example shown in FIG.
7 is output, and CPU 0 executes at that time
Command processing is completed and the shared bus right can be relinquished.
Halt acknowledgment 8 in a of FIG.
2 is output and the CPU0 shared bus access is
Access permission signal 85 (driven by gate 83)
Activate and share as shown in FIG.
Abandon the existing bus. Also, the CPU 0 itself is denoted by a in FIG.
Enters the halt state, and at the same time, the CPU 1
The shared bus access permission signal 86 (by the gate 84)
Drive) becomes active and a of K in FIG.
The CPU 1 of the bus switch buffer 23 as shown in FIG.
Is selected, and the right to use the shared bus is transferred to the CPU 1. C
Even if PU1 finishes using the shared bus and abandons the shared bus
When a good time arrives, CPU1 shared bus access request
Deactivate 87 as shown at Ib in FIG.
Then, immediately at CPU b shared bus access at b in FIG.
Switch 85 becomes active and the bus switch
CPU0 side of buffer 23 is selected and shared with CPU0
After the right to use the bus is transferred, the CPU 0 e
Acknowledgment is released, and CP
U0 shifts from the halt state to the actual operation state. G in FIG.
And L indicate the actual operating states of CPU0 and CPU1, respectively.
are doing. Master (CPU0) and slave
CPU0 performs a CPU (CPU1) operation.
While the right to use the shared bus has been transferred (a-F in FIG. 2F).
b) perform the bus switch and the electrical and timing of the bus
For a short period of time (FIG. 2F)
The halt state is reached for the total time of b) and b), and no actual operation is performed.
No. That is, in terms of the working right, the CPU 1 is more like a master.
Will work. Halt time is too long
One data transfer so that the operation of CPU0 is not hindered.
A mode to transfer the right to use the shared bus to CPU0
I have. However, as described later, CPU 0 is
U is a backgrou that performs intelligent processing etc.
Used in support of CPU0 as a command CPU, and
When a multi-processor configuration is used, the base
Distribution of function distribution structure per server element (BPE)
By adopting the knowledge base format, many necessary data
Data will be available near you, and most data communications
Is to use dual port RAM (DPR)
Can be. Therefore, the base processor element
The rate at which knowledge information is exchanged between (BPE)
Other base processor elements for tightly coupled parallel processing
Small enough compared to the rate at which information is exchanged with
And the processing power loss of CPU0 according to the present invention is very small.
Can be considered as In addition, CPU processing
The role of the CPU 1 as performing backup and system management
When the percentage is fixed, the operation control right of CPU0 is assigned to CPU1.
Is more effective in terms of management, etc.
Is suitable for local distributed processing as described above.
It can be said that. Next, the above-described processor of the present invention
The general operation will be described in detail with reference to FIG. FIG. 3 shows that the CPU 0 performs a main control operation.
CPU 1 is based on knowledge base (distributed) sensor information, etc.
CPU0 to perform intelligent processing and system management
Backup in a round, local distributed processing
It is assumed that In addition, multi-processor architecture
Configuration, each base processor element
(BPE) is another base processor element
(BPE) and tightly-coupled parallel processing in the main, back
In the ground, it is assumed that loosely coupled parallel processing is performed.
You. 35 shows a processing flow of the CPU 1 along the time axis.
Similarly, 36, 37, and 38 correspond to the processing flow of CPU0.
This is shown. Shared resources include the base processor
Between CPU0 and CPU1 in the SA element (BPE)
Dual port RAM (D
PR) and all bases in a multi-processor configuration.
Accessible from the processor element (BPE)
There is a system shared resource on the active system bus 14.
47, 48, 54, 59 communicate between CPU0 and DPR
, And 46, 53, 56, and 58 correspond to the CPU 1 and the DPR.
Shows communication. Similarly, 57 is CPU0 and system
Shared resources, 51: communication between CPU 1 and system shared resources
It is necessary to observe from the system shared resource side
Again, from the base processor element (BPE)
Access. Also, 50 is a dual port
CPU0 using interrupt function on RAM (DPR)
Indicates an interrupt to CPU1, and 55 indicates an interrupt to CPU1 in the same manner.
Only shows. 49 is a shared bus from CPU1 to CPU0.
Access request signal and the corresponding CPU 0
Handshake with shared bus access permission signal
52, which is obtained once by the CPU 1
Shared bus is abandoned and its right to use transfers to CPU 0 again
It shows the situation. 88 and 89 are systems from other BPEs.
Indicates access to system shared resources. 90, 91
External world information during processing by CPU 1 as part of knowledge
Show how local sensor information is captured
Similarly, 92 and 93 are also shared by other BPEs.
CPU0 and CPU1 capture the shared sensor information
Is shown. Processing of CPU0 and CPU1
Regarding the contents, CPU0 is the main processing system and other bases.
Processor element (BPE) CPU0 and
Part of the intelligent mechanical system, for example, humanoid robot
Numerous controls needed to control the arm of the kit
Divide computational tasks so that parallelism is improved as much as possible.
Execution of tightly coupled parallel processing 36b, 38b with high efficiency
To an auxiliary processor such as an arithmetic processor.
Free time after requesting another processor or other base processor
. Empty time that occurs during synchronization processing with the element (BPE)
And other base processor elements BPE,
At the time of processing request by interruption from CPU1 and shared resources
36 in cooperation with CPU1 as a background processing system
a, performs intelligent processing and system management shown in 38a, and
An intelligent processing system is configured together with the processing 35 of PU1. This
Executed in the base processor element (BPE)
Intelligent processing system is a part of the arm,
Information on muscle parts is stored as a database.
Local sensor information is closely related to it.
Are captured as perceptual information, and
Muscle based on local function distributed database
Executes intelligent processing related to the minute and is executed by the main processing system.
To back up the entire control operation
You. In a system based on the above assumptions,
Thus, the processing flow of CPU0 and CPU1 shown in FIG.
Just follow. First, CPU0 and CPU1 respectively
The CPU 36 executes the processes 36 and 35 shown in FIG.
Immediately needed to communicate with CPU0,
Write communication message to dual port RAM (DPR)
Command register to CPU0
An operation 46 for writing to is performed. Correspondingly, CPU0
Interrupt 50 occurs and CPU0 background
Dual port RAM (DPR) is accessed in the processing system
Communication 47 of necessary information is performed. At the time of 40,
CPU0 is used between CPUs that do not need to perform handshaking.
Dual port RAM (DP
R) or dual port RAM (DPR)
Or read from. Various sensor information is also sent
The server side becomes the main body, and it is processed sequentially by interruption,
It is referred to in the program as needed, and
It is taken in as a part. Next, the CPU 1 executes another base program.
System to communicate with the processor element (BPE).
The need to communicate with the system shared resources arises and the shared bus at 49
(BPE local bus) Acquire the right to use 12 and 41
At this point, communication 51 with the system shared memory is performed, and
At 52, the right to use the common bus is transferred to CPU 0 again.
You. During that time, CPU0 is kept in the halt state 37 and 52
When the halt state is released by the
Processing 38 is continued. Thereafter, at the time of 42, the CPU 1
And dual port RAM (DPR) for shared data between CPUs
Data communication is performed.
Communication of handshake data with instructions from CPU to CPU1
Is performed in the same manner as 39. At 44, CPU 0
Communication 57 with the system shared resource is performed,
Is used for intelligent processing in the background processing 38a.
Communication in the main processing 38b,
Communication of tightly coupled parallel processing data
There is no effect on the processing or operation of the CPU 1. 45 is C
Dual port RAM (DPR) for PU0 and CPU1
This shows that the flow communication is being performed at approximately the same time.
Arbitration by the arbiter 60
Support for each other's processing and operations
The communication process is being executed without any trouble. As described above, the local distributed database
Intelligent processing system and control backed up by it
When the processing system is realized by the processor of the present invention,
Intelligent processing through dual port RAM (DPR)
CPU in base processor element (BPE)
In between, and sometimes the result or other base
・ Intelligent processing by processor element (BPE)
Access system shared resources to exchange results
Only naturally, between the communication nodes in the system.
The best communication throughput can be achieved,
Therefore, the control processing system and the intelligent processing system are almost completely independent
Column operation enables reliable doubling of processing performance
It works. In addition, by adding BPE, intelligent processing system
Processing performance and control processing system performance increase in proportion
And always provide balanced processing performance.
Can be. According to an embodiment of the present invention, a multiple
Based on a processor system or a single processor system
Book processor element (base processor
・ Element: BPE) is composed of two CPUs.
Dual port RAM (DPR) with interrupt function
And external observation by master / slave operation
Common to both CPUs that look like a single CPU
Connected with common bus available for highly independent main
Separating the processing system from the background processing system
PU is assigned to each, and the localization between two CPUs
Information exchange via dual port RAM (DPR)
Other bases in a multi-processor configuration.
Communication with the processor element (BPE) is a common bus
(BPE local bus) through the system bus
The performance of BPE can be achieved through system shared resources.
Qualitatively doubled. In addition, using the processor of the present invention,
When configuring a multiprocessor system,
The functions of the window processing system are decentralized and each BPE
By having it in units, it can be used in background processing systems.
Most are closed by local communication within the processor.
You don't need to communicate frequently with other processors,
More optimized communication throughput between communication nodes
Because of the tight coupling parallel processing being executed in the main
Main processing system and background without affecting
Naturally high-efficiency parallel processing in both processing systems
Can be. Further, by adding the processor of the present invention,
Always scatter in both main processing and background processing
And improved processing capacity. As described above, according to the present invention, a general
Multi-processor system suitable for general processing or
Balance the substantial processing performance of a single processor system
It can be improved well and efficiently. According to the present invention,
This reduces contention on the common bus and provides two
When exchanging information between report processing means, each information processing means
Store and read information to and from the memory means
This can be performed without restricting the information processing means. Subordinate
This improves communication throughput and improves information processing speed.
The top is planned.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an internal configuration of a base processor element in a processor of the present invention and a part of a multi-processor system based on the internal configuration. FIG. 2 is a diagram showing a common bus (BPE local) switch sequence between two CPUs in a base processor element constituting the present invention. FIG. 3 shows two CPUs in a base processor element
It is a figure showing the flow of processing between. FIG. 4 is a basic logic diagram of a shared bus switch constituting the present invention. FIG. 5 is a logic block diagram of a dual port RAM constituting the present invention. [Description of Signs] 1 Base processor element (BPE) 8 System bus switch 14 System bus 15 CPU0 (master) 16 CPU1 (slave) 17 DPR logic 24 Common bus switch 32 Instruction interrupt line 33 to CPU0 Instruction interrupt line 73 for CPU1 Flip-flop 74 for generating an interrupt to CPU0 Flip-flop 85 for generating an interrupt to CPU1 85 CPU0 common bus access permission signal 86 CPU1 common bus access permission signal

Continuation of front page       (56) References JP-A-57-174747 (JP, A)                 JP-A-60-254358 (JP, A)                 JP-A-60-173655 (JP, A)                 JP-A-58-211271 (JP, A)                 JP-A-53-93746 (JP, A)                 JP-A-60-33643 (JP, A)                 JP-A-57-130136 (JP, A)                 JP-A-59-220821 (JP, A)                 JP-A-59-167730 (JP, A)                 JP-A-61-11876 (JP, A)                 JP-A-57-162056 (JP, A)                 JP-A-58-211271 (JP, A)                 JP-A-51-54753 (JP, A)                 JP-A-54-50329 (JP, A)                 JP-A-56-145494 (JP, A)                 JP-A-57-136203 (JP, A)                 JP-A-57-152065 (JP, A)                 JP-A-60-120484 (JP, A)                 US Patent 4,495,569 (US, A)

Claims (1)

(57) [Claims] A bus to which a shared resource is connected; a first CPU for processing coast information; a second CPU for processing coast information; switching between the first CPU and the second CPU to connect to the bus A switch for storing and reading information between the first CPU and the second CPU; and a switch provided between the first CPU and the second CPU; An arbiter for arbitrating a bus cycle from the first CPU to the memory and a bus cycle from the second CPU to the memory; and the switch for performing switching control of the switch and arbitration control of the arbiter. And arbiter first and second C
Means for inputting a signal from the PU; and a processor system comprising: 2. A shared bus to which a shared resource is connected; a first CPU for processing information; a second CPU for processing information; a first local bus connected to the first CPU; A second local bus connected to the switch, a switch for switching between the first and second local buses and connecting to the shared bus, and a switch configured independently of the second local bus and connected to the first CPU. A third local bus, a fourth local bus configured independently of the first local bus, and connected to the second CPU; and a third local bus connected to the third and fourth local buses. 1st, 2nd
A memory that enables storing and reading of information between the first CPU and the second CPU; and a first CPU that is provided between the first CPU and the second CPU and that is provided on a third local bus. And an arbiter for arbitrating a bus cycle from the second CPU to the memory and a bus cycle from the second CPU to the memory on a fourth local bus; and performing switching control of the switch and arbitration control of the arbiter. To the switch and the arbiter.
Means for inputting a signal from the PU, the processor system comprising: 3. 3. The processor system according to claim 2, further comprising a second switch provided between the switch and the shared bus for selecting whether or not to connect the switch to the shared bus. 4. 3. The method according to claim 2, wherein the first processor constitutes a main processing system for performing a control operation, and the second processor constitutes a background processing system for backing up the main processing system. A processor system as described. 5. A shared bus to which a shared resource is connected; a first CPU for processing information; a second CPU for processing coast information; a first local bus connected to the first CPU; and the second CPU And a connection between the first local bus and the shared bus is always selected, and a second local bus and the shared bus are connected in response to a request input signal of the first or second CPU. A switch for selecting a connection with the first local bus, a third local bus connected to the first CPU, and a switch independent of the second local bus, and a third local bus connected to the first CPU. A fourth local bus connected to the second CPU; and first and second local buses connected between the third and fourth local buses.
A memory that enables storing and reading of information between the first CPU and the second CPU; and a first CPU that is provided between the first CPU and the second CPU and that is provided on a third local bus. And an arbiter for arbitrating a bus cycle from the second CPU to the memory and a bus cycle from the second CPU to the memory on a fourth local bus; and performing switching control of the switch and arbitration control of the arbiter. To the switch and the arbiter.
Means for inputting a signal from the PU; and a processor system comprising: 6. 6. The processor system according to claim 5, further comprising a second switch provided between the switch and the shared bus for selecting whether or not to connect the switch to the shared bus. 7. 6. The apparatus according to claim 5, wherein the first processor constitutes a main processing system for performing a control operation, and the second processor constitutes a background processing system for backing up the main processing system. A processor system as described.