JPS5887645A - Correspondence system between computers - Google Patents

Correspondence system between computers

Info

Publication number
JPS5887645A
JPS5887645A JP18541081A JP18541081A JPS5887645A JP S5887645 A JPS5887645 A JP S5887645A JP 18541081 A JP18541081 A JP 18541081A JP 18541081 A JP18541081 A JP 18541081A JP S5887645 A JPS5887645 A JP S5887645A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
computers
information
flag
set
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18541081A
Inventor
Tomihisa Hatano
Keiichi Nakane
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox

Abstract

PURPOSE:To perform the correspondence between computers when a failure occurs on a linkage bus between computers, by providing a periodic timer for each computer, and using a common memory between computers as an information exchange area. CONSTITUTION:An information transmission module 14 and an information reception module 15 are provided for a computer 3 at transmission side and a computer 4 at reception side, and the modules 14, 15 are connected to an exchange area 11 in a common memory 1 between the computers. One or both the computers 3, 4 are provided with a periodic timer 5, and the exchange area in the memory 1 is provided with an M flag 111 representing the presence/absence of information. The information is written in the exchange area 11 at the module 14 to set the flag 111. Further, the module 15 is started with the interruption set in the timer 5, the flag 111 is discriminated, the information in the area 11 is read out when the flag 111 is set, the flag 111 is finally set off, allowing to make the correspondence possible between the computers 3 and 4.
JP18541081A 1981-11-20 1981-11-20 Correspondence system between computers Pending JPS5887645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18541081A JPS5887645A (en) 1981-11-20 1981-11-20 Correspondence system between computers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18541081A JPS5887645A (en) 1981-11-20 1981-11-20 Correspondence system between computers

Publications (1)

Publication Number Publication Date
JPS5887645A true true JPS5887645A (en) 1983-05-25

Family

ID=16170298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18541081A Pending JPS5887645A (en) 1981-11-20 1981-11-20 Correspondence system between computers

Country Status (1)

Country Link
JP (1) JPS5887645A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320652A (en) * 1986-07-15 1988-01-28 Fujitsu Ltd Processor synchronizing system
JPH01142836A (en) * 1987-11-30 1989-06-05 Toshiba Corp Debugging system for parallel processing system
JPH02288941A (en) * 1988-05-20 1990-11-28 Fuji Electric Co Ltd Method for setting and changing system data on plural processors
JPH0353318A (en) * 1989-07-21 1991-03-07 Nec Corp Two-port memory
JPH09198355A (en) * 1997-03-07 1997-07-31 Hitachi Ltd Processor system
US5968150A (en) * 1986-03-12 1999-10-19 Hitachi, Ltd. Processor element having a plurality of CPUs for use in a multiple processor system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968150A (en) * 1986-03-12 1999-10-19 Hitachi, Ltd. Processor element having a plurality of CPUs for use in a multiple processor system
JPS6320652A (en) * 1986-07-15 1988-01-28 Fujitsu Ltd Processor synchronizing system
JPH01142836A (en) * 1987-11-30 1989-06-05 Toshiba Corp Debugging system for parallel processing system
JPH02288941A (en) * 1988-05-20 1990-11-28 Fuji Electric Co Ltd Method for setting and changing system data on plural processors
JPH0353318A (en) * 1989-07-21 1991-03-07 Nec Corp Two-port memory
JPH09198355A (en) * 1997-03-07 1997-07-31 Hitachi Ltd Processor system

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