JPS5887645A - Correspondence system between computers - Google Patents

Correspondence system between computers

Info

Publication number
JPS5887645A
JPS5887645A JP18541081A JP18541081A JPS5887645A JP S5887645 A JPS5887645 A JP S5887645A JP 18541081 A JP18541081 A JP 18541081A JP 18541081 A JP18541081 A JP 18541081A JP S5887645 A JPS5887645 A JP S5887645A
Authority
JP
Japan
Prior art keywords
information
computers
computer
module
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18541081A
Other languages
Japanese (ja)
Inventor
Tomihisa Hatano
富久 幡野
Keiichi Nakane
啓一 中根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18541081A priority Critical patent/JPS5887645A/en
Publication of JPS5887645A publication Critical patent/JPS5887645A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox

Abstract

PURPOSE:To perform the correspondence between computers when a failure occurs on a linkage bus between computers, by providing a periodic timer for each computer, and using a common memory between computers as an information exchange area. CONSTITUTION:An information transmission module 14 and an information reception module 15 are provided for a computer 3 at transmission side and a computer 4 at reception side, and the modules 14, 15 are connected to an exchange area 11 in a common memory 1 between the computers. One or both the computers 3, 4 are provided with a periodic timer 5, and the exchange area in the memory 1 is provided with an M flag 111 representing the presence/absence of information. The information is written in the exchange area 11 at the module 14 to set the flag 111. Further, the module 15 is started with the interruption set in the timer 5, the flag 111 is discriminated, the information in the area 11 is read out when the flag 111 is set, the flag 111 is finally set off, allowing to make the correspondence possible between the computers 3 and 4.

Description

【発明の詳細な説明】 (1)  発明の利用分野 本発明は、頷航台の!′を算機から構成される似合It
算機システムにおいて、各計算機が互いに情報を父供す
る。針Jl磯機関信方式に圓する。
[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention is directed to a nodding platform! ′ is composed of a calculator.
In a computer system, each computer provides information to each other. Converged on the needle Jl Iso engine communication system.

(2)  従来技術 複合#F鼻礪システムでは、一般に、与えられた菓t!
II%たとえばti算機の相互監視やプロセス制御など
の業務をいくつかに分割し、それらt’*aの計算機が
少しずつ分担して処理する構成をとる。
(2) In the prior art composite #F nose system, in general, given t!
II% For example, tasks such as mutual monitoring of ti computers and process control are divided into several parts, and these t'*a computers take part in the processing little by little.

このよりな計算機システムでは、各計算機が分担しfc
栗業務逐行してiくうえで、互いに情報を交快しなけれ
ばならないといつxiit況が発生する。
In this simple computer system, each computer shares fc
When we have to exchange information with each other as we go about our business, an oxidation situation occurs.

谷i1′t′J4機が互いに情報を交換するためには、
情報の交換エリアと、送tMiI111が情報を交換エ
リアに書き込んだことを受tinに通知する損耗が必要
である。
In order for the 4 Tani i1't'J machines to exchange information with each other,
There is a need for an exchange area for information and a wear that notifies the receiver that the sending MiI 111 has written information to the exchange area.

従来技何では、J111図のように、計算機3,4を、
ltt′I!#機閾共有メモリ1とtl−鼻慎間りンケ
ージパス2で縮合し、rrs績間共肩メモリ1円に情報
交換エリア11を&逃、計算機間リンケージバス2に割
込み憬1llt具伽し、これらt−便って針鼻機閲交信
を行なっていた。
In the conventional technique, as shown in figure J111, computers 3 and 4 are
ltt'I! Condenses the # machine threshold shared memory 1 and TL-Hana Shinma linkage path 2, transfers the information exchange area 11 to the rrs shared memory 1 yen, interrupts the inter-computer linkage bus 2, and connects these. T-bin was carrying out communications using a needle-nose machine.

すなわち、送IjIi411針算a13は情報を交換エ
リア11に膏き込み、つぎに#鼻機関リンケージバス2
を軸出して受信側計算*4に割込みをかける。
That is, the sending IjIi411 calculation a13 inserts the information into the exchange area 11, and then the #nose engine linkage bus 2
, and interrupts the calculation on the receiving side*4.

受信側計算fa4は、この割込+を受付けた時。Receiving side calculation fa4 receives this interrupt +.

悄@At−変洪エリフ11から絖み出す。Yu@At-Starts from Henko Elif 11.

この方式は、比較的簡単に、システムt−傅處する計X
機の台aを拡張できるという置所を持ってイ、6カ、−
77、#8flk間リンケージパス2に[Fが発生じた
一m合、 tie磯閲交洒が不可能となシ。
This method is relatively simple and can be used to
It has a place where the machine's stand a can be expanded.
77, If [F occurs in the linkage path 2 between #8 flk, tie crossing is not possible.

情報交換の門番によっては、システムダウンを引き起こ
すことかめるとい9危険性を持っている。
Depending on the gatekeeper of information exchange, there is a risk that the system may go down.

したがって、超高膚頼性を費求するシステムでは、 t
iJ1機間りンケージバス2を2x化する方式がとられ
ているが、そのために、システム規模のわシには南画な
システムとなることがある。
Therefore, in a system requiring ultra-high reliability, t
A system has been adopted in which the linkage bus 2 between iJ aircraft is converted to 2x, but this may result in a system that is unsatisfactory in terms of system scale.

ここに、計′j#機関リンケージパスの障害に備え。Here, prepare for failure of the total engine linkage path.

その割込み機構の安価な代替手段が望まnている。An inexpensive alternative to that interrupt mechanism is desired.

また、当初から計算機間リンケージバスの割込み機Sを
便うCよどの尚速性を散水せずに、単純にtiJI機間
共有メモリだけt−使って、in機閾父信の機能を具備
することを散水するシステムも少なくない。
In addition, without giving away the speediness of C, which uses the interrupt machine S of the inter-machine linkage bus from the beginning, it simply uses the tiJI inter-machine shared memory and provides the in-machine threshold communication function. There are also many systems that sprinkle water.

(3)  発明の目的 本発明は、計算機間共有メモリと、各々の計算機が既に
具備しているハードウェア′?t、fII用して、送t
i111411#tJ1:機3が1W報を計算機関共有
メモリ内の交換エリアIIK振き込んだことt−慣用す
るタイミ/グt、受tg情針算機4に発生名せることに
よシ、tt鼻機間リンケージバス2を1j!9場合よシ
は性能は劣ってもよいが、情報交換の機能を維持できる
ようにすることを目的とする。
(3) Purpose of the Invention The present invention provides a shared memory between computers and hardware that each computer is already equipped with. t, use fII, send t
i111411#tJ1: Machine 3 transferred the 1W information to the exchange area IIK in the computing institution shared memory t-Used timing/tag t, received tg information Calculator 4 by giving the occurrence name, tt 1j nose linkage bus 2! Although the performance may be inferior in case of 9, the purpose is to maintain the function of information exchange.

(4)発明の緬括lll!明 g2凶に示した複合tis機システムでは、谷計31!
−に周期タイマをAi#iiシている。この図では見や
すくするために、受0111411iiitJ1機4に
だけに周期タイマ5を衆示しである。
(4) A collection of inventions! With the composite TI system shown in Akira G2Ko, the total is 31!
- A periodic timer is set at Ai#ii. In this figure, for ease of viewing, the periodic timer 5 is shown only in the receiver 0111411iiitJ1 machine 4.

送償両耐鼻礪3は慣権込瘍モジュール14を秋って率に
情報を交換エリア11へ書き込む。
The remittance resistant nose 3 writes information to the exchange area 11 in response to the custom complication module 14.

一方、受信1lll針J1機4は周期タイマ5金利用し
て、慣截受信七ジュール15により情報交換エリア11
を探索するタイミングを発生させる。
On the other hand, the receiving 1llll hand J1 machine 4 uses the periodic timer 5 and the information exchange area 11 according to the customary receiving 7 joules 15.
Generate the timing to explore.

周期タイマ5の割込手が一足間隔で発生するように′!
F埋しておき、その割込みが発生ずる九びに情報受信モ
ジュール15が情報交換エリア11を探索し、もし情報
が★き込まれていたならはそCを絖み出す。
The interrupt of periodic timer 5 will be generated at one foot interval'!
The information receiving module 15 searches the information exchange area 11 every time the interrupt occurs, and if the information has been written, the information receiving module 15 finds the information C.

情報交換エリアの探索周期を許容乾固に納まるように設
足しておき、ti算機間父濡を維持できることを保障す
る。
The search cycle of the information exchange area is set so as to fall within the allowable dryness range, thereby ensuring that the data exchange area can be kept within the allowable dryness range.

(51WJMガ 以下1本発明を夫m例を参照して旺細に祝明する。(51WJMga The present invention will be described in detail below with reference to several examples.

第3図に情報送置モジュール14.慣権受信モジュール
15の詳#lを示す。
FIG. 3 shows the information sending module 14. Details #l of the customary reception module 15 are shown.

1′11報の5e供は、従来方式と同様に計算機関共有
メモリl内の交換エリア11を便って竹なう。情報交換
エリアには、情報の有無を嶽わすM7.Fグ111ft
具備する。
The 5e information of the 1'11 information is sent via the exchange area 11 in the computing engine shared memory 1, as in the conventional system. In the information exchange area, there is an M7. Fgu 111ft
Be equipped.

債権送信モジュール14は、情報を交換エリア11へ簀
き込+、Mフラグ111t−ONする。
The debt transmission module 14 stores the information in the exchange area 11 and turns on the M flag 111t.

−刀、情報受信モジュール15は、周期タイマ50割込
みで起動される。まず、次回のタイマ割込みを発生させ
るために周期タイマ5に周期時間をセットする。つぎに
、Mフラグ1llt−判定する。MフラグがONの1合
はには、交懺エリア11に情報が★き込まれているので
、七fLt交換エリアから絖み出し、そして処理する。
- The information receiving module 15 is activated by a periodic timer 50 interrupt. First, a cycle time is set in the cycle timer 5 in order to generate the next timer interrupt. Next, the M flag 1llt- is determined. If the M flag is ON, the information has been written into the exchange area 11, so it is extracted from the 7fLt exchange area and processed.

戚後にMフラグをOFFする。以上の手職で情報交換を
行なう。
After the connection, turn off the M flag. Information is exchanged through the above-mentioned crafts.

藁4図、第5図に、従来の方式と本発明の方式との切換
え割#を示す。
Figures 4 and 5 show switching rates between the conventional method and the method of the present invention.

jttJ!愼閲共有メモリ1円に、計算機間り/ケージ
バス2が正常に動作するか否かを示すBK7ラグ112
を具備する。BKフラグがOF F、の状態は、ttx
礪間リンケージバス2が正常にIIJ作することを示す
。この場合に、従来方式のIti真機間共有メモリ1と
計算機関リンケージバス2を使う畦鼻機閾父堵を行なう
。すなわち送信モジュール12と、受傷モジュール13
が動作する。
jttJ! BK7 lag 112 indicating whether or not the inter-computer/cage bus 2 is operating normally for 1 yen of shared memory
Equipped with. When the BK flag is OFF, the state is ttx.
This shows that the Ikuma linkage bus 2 is working normally. In this case, a conventional method for establishing a ridge-nose machine threshold using the inter-machine shared memory 1 and the computer linkage bus 2 is performed. That is, the transmitting module 12 and the injury module 13
works.

このとき1周期タイマ50割行みが一足間隔で発生し、
受旧モジュール15も動作するが、第3図に示すようv
c、Mフラグ111がOFF状態なので、受信モジュー
ル15の動作は無効になってVhる。
At this time, 50 interrupts of the 1-cycle timer occur at intervals of one foot,
The old module 15 also operates, but as shown in FIG.
c. Since the M flag 111 is in the OFF state, the operation of the receiving module 15 is disabled and becomes Vh.

一方、BK7ラグ112かONの状態は、tin機間機
関ケージバス2が故嘩して−ることt示す。
On the other hand, the ON status of BK7 lug 112 indicates that the intermachine engine cage bus 2 has malfunctioned.

この(転)台は1本発明Vこ係わる針其礪間父堵を行な
う。すなわち込はモジュール14と5党偽モジュール1
5が動作する。
This (transfer) table performs the needle cutting process related to the present invention. In other words, it includes module 14 and 5 party fake module 1
5 works.

このように1便禾方式と本発明の方式との切供えをBK
フラグ112で何なう。
In this way, the BK
What's going on with flag 112?

第5図に示すように、送信モジュール12が1、X(1
其機関リンケージバス)を起動した時。
As shown in FIG.
When the engine linkage bus) is started.

LXが正常に動作しないならは、LXvJMモジュール
16が励11シ、BK7ラグ112をONし。
If the LX does not operate normally, the LXvJM module 16 turns on the BK7 lug 112.

Mフラグ111をONする。そうするととりこよって、
受信子ジュール15の動作が肩効となシ、LX陣否%生
時の送部TV11報が受信−肘算慨に受傷さt″Lる。
Turn on the M flag 111. Then I became fascinated,
If the operation of the receiver module 15 is affected, the transmitter TV 11 report when the LX team is active is affected by the receiver calculation.

こjL以後の肘其愼間父濱は、送置モジュール14と受
1dモジュール15で行なわれる。
After this jL, the sending and receiving module 14 and the receiving 1d module 15 perform the transfer.

また、1s、機関リンケージバス2の障害が回復した時
には、LX回復モジュール17が動作して。
Further, when the fault in the engine linkage bus 2 is recovered in 1s, the LX recovery module 17 operates.

BKフラグ112をOFFする。そうすることによって
、本発明の1t−x機関交信は停止し、再び従事  1
r′;i′I 米寿式の、fts磯間機関が丸まる。
Turn off the BK flag 112. By doing so, the 1t-x engine communication of the present invention is stopped and re-engaged.
r';i'I The FTS Isoma engine is rolled up in the Yoneju style.

以上の手HLで従来方式のバックアップを行なう。Backup using the conventional method is performed using the above manual HL.

(6)まとめ 以上睨央したごとく本発明によれば、嶺曾針算機システ
ムにおいて、%酊JL磯を結合する社真機関共有メモリ
と、個々のrrFs磯が具備している周期タイマを使用
して%肘算磯閾交匿が行なえる。
(6) Summary As summarized above, according to the present invention, in the Reisobin computer system, the shared memory of the machine engine that connects the %JL iso and the periodic timer provided in each rrFs iso are used. % elbow calculation iso threshold intersection can be performed.

したがって、計s、fIA間リンケージバスを具備しな
い安価な複合its機システムにおけるi!tJ!磯闇
父信方式、あるいは、iti鼻機間機関ケージバスを具
備するシステムにおいて、それのバックアップ力式とし
て、本Afiの方式を応用できる。
Therefore, i!S, i! tJ! The present Afi method can be applied as a backup power method for a system equipped with the Isoyami Father Shin method or an iti nose intermachine engine cage bus.

【図面の簡単な説明】[Brief explanation of the drawing]

帛l凶は便米の耐鼻機関交旧を示すブロック図。 第2図は本発明の−*IMfIlを示すブロック図、第
3図は第2図中のtW報送旧モジュール14.悄権受信
モジュール15の詳細図、帛4凶、纂5凶は本発明の方
式と従来の方式との切供え制#會示す辷デ     +
      ?) /IJ      l        μ−vJ Z 
 図 13  図 亀 第 4 図 ′vJ  s  図
The block diagram is a block diagram showing the old version of the nose-resistant machine exchange. FIG. 2 is a block diagram showing -*IMfIl of the present invention, and FIG. 3 is a block diagram showing the tW sending old module 14. Detailed diagrams of the right-of-way reception module 15, Figures 4 and 5 show the comparison between the system of the present invention and the conventional system.
? ) /IJ l μ−vJ Z
Figure 13 Figure 4 Figure 'vJ s Figure

Claims (1)

【特許請求の範囲】 1、a数の訂3!慎が計算機関共有メモリを介して結合
もれるように構成されている複合計算機システムにおい
て、個々の計算機に周期タイマを具備し、tt算礪間共
脣メモリを情@父侠エリアとして便い、受部II!li
t鼻機は周期タイマを便って一定間隔でタイマ割込みt
″兄生せ、このタイミングで込fi!側計算機が情報交
換エリアに情報t″膏き込んだか否かを探索し、もし畳
き込んでめったならばそれt−vtみ出すことによって
。 情報交換を行なう耐算機間交信方式。
[Claims] 1. Correction of a number 3! In a compound computer system configured so that the computer can be connected via the computer shared memory, each computer is equipped with a periodic timer, and the shared memory between the computers is used as the love@patriarchy area. Ukebu II! li
The nose machine uses a periodic timer to interrupt the timer at regular intervals.
At this timing, search to see if the computer on the side has injected information t'' into the information exchange area, and if it rarely occurs after convolution, then extract it tvt. A communication method between computers that exchanges information.
JP18541081A 1981-11-20 1981-11-20 Correspondence system between computers Pending JPS5887645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18541081A JPS5887645A (en) 1981-11-20 1981-11-20 Correspondence system between computers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18541081A JPS5887645A (en) 1981-11-20 1981-11-20 Correspondence system between computers

Publications (1)

Publication Number Publication Date
JPS5887645A true JPS5887645A (en) 1983-05-25

Family

ID=16170298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18541081A Pending JPS5887645A (en) 1981-11-20 1981-11-20 Correspondence system between computers

Country Status (1)

Country Link
JP (1) JPS5887645A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320652A (en) * 1986-07-15 1988-01-28 Fujitsu Ltd Processor synchronizing system
JPH01142836A (en) * 1987-11-30 1989-06-05 Toshiba Corp Debugging system for parallel processing system
JPH02288941A (en) * 1988-05-20 1990-11-28 Fuji Electric Co Ltd Method for setting and changing system data on plural processors
JPH0353318A (en) * 1989-07-21 1991-03-07 Nec Corp Two-port memory
JPH09198355A (en) * 1997-03-07 1997-07-31 Hitachi Ltd Processor system
US5968150A (en) * 1986-03-12 1999-10-19 Hitachi, Ltd. Processor element having a plurality of CPUs for use in a multiple processor system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968150A (en) * 1986-03-12 1999-10-19 Hitachi, Ltd. Processor element having a plurality of CPUs for use in a multiple processor system
JPS6320652A (en) * 1986-07-15 1988-01-28 Fujitsu Ltd Processor synchronizing system
JPH01142836A (en) * 1987-11-30 1989-06-05 Toshiba Corp Debugging system for parallel processing system
JPH02288941A (en) * 1988-05-20 1990-11-28 Fuji Electric Co Ltd Method for setting and changing system data on plural processors
JPH0353318A (en) * 1989-07-21 1991-03-07 Nec Corp Two-port memory
JPH09198355A (en) * 1997-03-07 1997-07-31 Hitachi Ltd Processor system

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