JPH01142836A - Debugging system for parallel processing system - Google Patents

Abstract

PURPOSE:To reduce the difficulty of debugging by providing each processor with a break instruction for writing contents in a flag and a check point instruction for referring the contents of the flag and deciding whether the execution of the program is to be stopped or not. CONSTITUTION:In order to stop the whole system when a program A for a specific processor is to execute an instruction set up on a certain address, a break instruction 13 is set up in the address. On the other hand, check point instructions 14 are set up on positions to be stopped in programs B, C for other processors. When the specific processor executes the break instruction, a flag 15 is set up, the processor is stopped, and when other processors execute the check point instructions thereafter, the processors are stopped. Consequently, all the processors constituting a parallel processing system to be asynchronously processed can be stopped at a fixed position, so that the debugging of programs can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a debugging method for a parallel processing system composed of a plurality of processor numbers.

(Prior Art) When depacking a program, it is important to have a function to stop the program at a specific position and check the contents of memory. However, in an environment where multiple processors operate asynchronously, debugging becomes difficult because stopping a specific processor does not stop other processors. Also, when stopping a specific processor, a method of forcibly stopping other processors can be considered, but if processors operate asynchronously, fζ is a method in which the program in the stopped processor is forcibly stopped. Since the location differs each time the program is executed and is not constant, the contents of the memory are not constant, making debugging difficult.

(Problems to be Solved by the Invention) As described above, the conventional debugging method for parallel processing systems has the drawback that even when all processors are stopped at the same time, the stopping position of each program is not constant.

Therefore, the present invention aims to reduce the difficulty of debugging in a parallel processing system. When a specific processor stops, other processors are stopped at a fixed position. Keep the content constant
The purpose is to maintain this.

[Structure of the invention]

(Means for Solving the Problems) In the present invention, all the processors constituting the parallel processing system are provided with a flag that can be written to and read from, and a break instruction to write the contents of this flag and the contents of this flag are provided. By providing each processor with a check point instruction that refers to the check point instruction and determines whether to stop program execution, it is possible to stop a parallel processing system that operates asynchronously at a fixed position.

(Operation) When a program of a specific processor executes an instruction at a certain address, a break instruction is set at that address in order to stop the entire system. Also, programs of other processors are stopped. che in a good position
Set the ck point instruction. When a particular processor executes a break instruction, a flag is set and that processor stops. Further, if any other processor executes a check point instruction thereafter, the process will stop. Therefore, the entire system can be stopped in a constant state.

(Example) Hereinafter, one example of the present invention will be described. FIG. 1 is a system configuration diagram of one embodiment of the present invention.

As shown in the figure, a flag 2 is provided that can be accessed by a plurality of processors 1.

FIG. 2 is a diagram showing the execution process when three programs AIO, B1t, and C12 are placed on different processors. In the figure, break command 13 is set at a specific position in program A, and program B
, a check point instruction 14 is set in C. Further, the flag 15 has an initial value y, and when the flag becomes I, the entire system is stopped. This will be explained below with reference to FIG.

Start programs A, B, and C at the same time in the initial state. An arrow 16 in the figure indicates the position of the program currently being executed.

In state 1, program B checks point l
It has reached 171. However, since the flag is y, program B does not stop at this stage and moves to the next instruction f.

In state 2, program A has reached break 13. As a result, 11 flags are set, and program A
stops. However, programs B and C continue to execute.

In state 3, Progera AB is check point
Since it reaches 21g and the flag is 1, it stops at this position. Similarly, in state 4, program C runs check
It reaches kpoint3 20) and stops at this position because the flag is 1. As a result, all three programs have stopped.

Next, a second embodiment of the present invention will be explained.

FIG. 3 is a system configuration diagram of the second embodiment.

Here, each of the plurality of processors 1 is provided with a flag 2. FIG. 4 is a diagram showing the execution process when three programs AIO, Bl 1 and C12 are respectively placed on different processors in the second embodiment.

Again, break command 13 is set at a specific position in program A, and in programs B and C, f is c.
A heck point instruction 14 is set. Also, flags A, B, and C15 are initial values, and the flag is 1.
When this happens, the entire system is stopped.

The same explanation will be given below with reference to FIG.

Start programs A, B, and C at the same time in the initial state. An arrow 16 in the figure indicates the position of the program currently being executed.

In state 1, Progera AB is check point 1
It has reached 17. However, since flag B is OFF, program B does not stop at this stage and moves to the next instruction f.

In state 2, program A has reached breck 18 f. As a result, the flags of all processors are set, and program A is stopped. However, program B
C continues execution.

In state 3, program B checks the check point
2191 is reached and flag B is 1, so it stops at this position. Similarly, in state 4, program C runs check
It reaches kpoint 320 and stops at this position because flag C is 1. As a result, all three programs have stopped.

Furthermore, by extending this method to include n bits of flags, program termination can be flexibly controlled. For example, both the break command and the check point command have arguments. When the break instruction is executed, the value of this argument is set to a flag.

When the check point instruction is executed,
It can be expanded to compare the value of the argument with the flag and stop only when the value of the flag is greater than the value of the argument. Alternatively, the process may be stopped only when the value of the argument of the check point instruction and the value of the flag match. Furthermore, the processor referred to here is an abstract concept, and one processor may correspond to one processing device, or a plurality of processors may correspond to processes on one processing device.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, all the processors that make up a parallel processing system that operates asynchronously can be stopped at a fixed position, making it easier to debug programs. .

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram of the first embodiment of the present invention;
The figure shows the execution process of the first embodiment of the present invention, Figure 3 is a system configuration diagram of the second embodiment of the invention, and Figure 4 shows the execution process of the second embodiment of the invention. FIG.

Claims (2)

[Claims] (1) In a parallel processing system composed of a plurality of processors, a flag that can be read and written by each processor, a means for stopping program execution of the processor when a processor writes information to the flag, and other things. A debugging method for a parallel processing system, comprising means for reading the flag information for each processor and stopping the program accordingly. (2) A debugging method for a parallel processing system according to claim 1, wherein the flag is provided for each processor.