JPH09196998A - Measuring apparatus for output resistance of driver ic - Google Patents
Measuring apparatus for output resistance of driver icInfo
- Publication number
- JPH09196998A JPH09196998A JP8027329A JP2732996A JPH09196998A JP H09196998 A JPH09196998 A JP H09196998A JP 8027329 A JP8027329 A JP 8027329A JP 2732996 A JP2732996 A JP 2732996A JP H09196998 A JPH09196998 A JP H09196998A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- dut
- output
- driver
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/08—Measuring resistance by measuring both voltage and current
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、例えばＬＣＤ
（液晶）ドライバＩＣやバブルジェットプリンタドライ
バＩＣのような多数出力ピンを有するドライバＩＣの出
力抵抗を測定する出力抵抗測定器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD, for example.
The present invention relates to an output resistance measuring device for measuring the output resistance of a driver IC having multiple output pins such as a (liquid crystal) driver IC and a bubble jet printer driver IC.
【０００２】[0002]
【従来の技術】図３に多数ピンを有するドライバＩＣ１
０の一例を示す。ピン数は種類により異なるが、１６０
ピンから３００ピンの物が多い。電源端子ＶDDやＶEEに
電圧電源を接続し、グランド端子ＧＮＤを接地してＩＣ
を駆動させる。複数の入力端子ＩＮｉ（ｉ＝１〜ｎ）に
は、外部からの制御信号により出力ピン名とその出力電
圧が指令される。例えば、出力電圧値は８ビットの信号
で２５６階調で指令される。多数の出力ピンＯＵＴｉ
（ｉ＝１〜ｍ）からはその指令された出力ピンから指定
された一定電圧値を外部の負荷に供給する。2. Description of the Related Art FIG. 3 shows a driver IC 1 having a large number of pins.
An example of 0 is shown. The number of pins depends on the type, but 160
There are many things with 300 to 300 pins. Connect a voltage power supply to the power supply terminals V DD and V EE and ground the ground terminal GND to the IC
Drive. An output pin name and its output voltage are commanded to the plurality of input terminals INi (i = 1 to n) by a control signal from the outside. For example, the output voltage value is an 8-bit signal and is instructed in 256 gradations. Many output pins OUTi
From (i = 1 to m), the specified constant voltage value is supplied from the commanded output pin to the external load.
【０００３】この多数ピンを有するドライバＩＣ（以下
「ＤＵＴ」という）１０の多数の出力ピンＯＵＴｉは、
制御信号により指令された電圧電流を正しく負荷に供給
しなければならない。そして出力抵抗もスペック通りで
ある必要がある。そこで従来からＤＵＴ１０の製造過程
や製造後あるいは受入検査で、個々のＤＵＴ１０の出力
電圧、出力電流や出力抵抗の測定をして、そのＤＵＴ１
０の良否を検査している。A large number of output pins OUTi of the driver IC (hereinafter referred to as "DUT") 10 having a large number of pins are
The voltage and current commanded by the control signal must be correctly supplied to the load. And the output resistance must also be as specified. Therefore, conventionally, the output voltage, the output current, and the output resistance of each DUT 10 are measured during the manufacturing process of the DUT 10, after the manufacturing, or in the acceptance inspection, and the DUT 1 is measured.
The quality of 0 is inspected.
【０００４】図４に従来の検査の方式を示す。ＤＣ測定
ユニット１５は定電流源を内蔵する電圧測定器である。
そして任意値の定電流をスイッチを通して吐き出すこと
も吸い込むこともできるので、ＤＵＴ１０の出力電圧Ｖ
O も出力電流ＩL も、また出力抵抗ＲO も測定すること
ができる。出力抵抗ＲO は出力電圧値ＶO と負荷電圧値
ＶM の差電圧を負荷電流値ＩLで除した値である。数式
で示すと、ＲO ＝（ＶO −ＶM ）／ＩL となる。負荷電
圧値ＶM は電圧測定器で測定する。FIG. 4 shows a conventional inspection method. The DC measuring unit 15 is a voltage measuring device with a built-in constant current source.
Since a constant current of an arbitrary value can be discharged or drawn through the switch, the output voltage V of the DUT 10
Both O, the output current I L and the output resistance R O can be measured. The output resistance R O is a value obtained by dividing the difference voltage between the output voltage value V O and the load voltage value V M by the load current value I L. When shown in a formula, the R O = (V O -V M ) / I L. The load voltage value V M is measured with a voltage measuring device.
【０００５】図４（Ａ）は、ＤＵＴ１０の多数の出力ピ
ンＯＵＴｉの出力電圧を電流印加電圧測定モードで、１
つのＤＣ測定ユニット１５でもって、１ピンづつ切替な
がら試験するという方法である。ＤＣ測定ユニット１５
が１つであるので、安価であるが、測定時間が掛かり過
ぎて遅すぎる。FIG. 4A shows the output voltage of a large number of output pins OUTi of the DUT 10 in the current applied voltage measurement mode.
This is a method in which one DC measurement unit 15 is tested while switching one pin at a time. DC measurement unit 15
Since it is one, it is inexpensive, but the measurement time is too long and too slow.
【０００６】図４（Ｂ）は、ＤＣ測定ユニット１５をＮ
ｃｈ（チャンネル）分設けてＮｃｈを電流印加電圧測定
モードでもって同時に測定し、Ｎピン毎に切り替えて測
定するものである。測定時間は図４（Ａ）に比べて１／
Ｎとなるが、ＮｃｈのＤＣ測定ユニット１５ｊ（ｊ＝１
〜Ｎ）を必要とするので高価となる。FIG. 4B shows the DC measurement unit 15 with N
The number of channels (channels) is provided and N channels are simultaneously measured in the current applied voltage measurement mode, and the measurement is performed by switching every N pins. Measurement time is 1 / compared to Fig. 4 (A)
N, but the Nch DC measurement unit 15j (j = 1
.About.N) are required, it is expensive.
【０００７】図４（Ｃ）は、ＤＵＴ１０の全出力ピンＯ
ＵＴｉ（ｉ＝１〜ｍ）分のＤＣ測定ユニット１５ｉを有
して電流印加電圧測定モードで全出力ピンＯＵＴｉを一
度で試験するものである。よって、測定時間は非常に高
速になるが、ＤＣ測定ユニット１５を全出力ピンＯＵＴ
ｉ分設けるので価格も非常に高価となる。FIG. 4C shows all output pins O of the DUT 10.
It has a DC measurement unit 15i for UTi (i = 1 to m) and tests all the output pins OUTi at once in the current applied voltage measurement mode. Therefore, although the measurement time becomes very fast, the DC measurement unit 15 is connected to all output pins OUT.
Since i minutes are provided, the price becomes very expensive.
【０００８】図４（Ｄ）は、ＤＵＴ１０の全出力ピンＯ
ＵＴｉ（ｉ＝１〜ｍ）に対してそれぞれ接続するプログ
ラマブルロードＰＬ２０ｉを用意し、ＤＵＴ１０のそれ
ぞれの出力ピンは高速スキャナ１６のそれぞれの入力端
子に接続される。ＤＵＴ１０への印加電流はＰＬ２０ｉ
が行い、電圧測定は高速スキャナ１６を通して１台の電
圧測定器１７で行う。電圧測定器１７側には電流が流れ
ないために高速スキャナを使用できるのである。この方
式は比較的高速に試験でき、しかも比較的安価である。FIG. 4D shows all output pins O of the DUT 10.
A programmable load PL20i to be connected to UTi (i = 1 to m) is prepared, and each output pin of the DUT 10 is connected to each input terminal of the high speed scanner 16. The applied current to the DUT 10 is PL20i
The voltage measurement is performed by the single voltage measuring device 17 through the high-speed scanner 16. Since no current flows on the voltage measuring device 17 side, a high speed scanner can be used. This method can be tested at relatively high speed and is relatively inexpensive.
【０００９】プログラマブルロードＰＬ２０は図５に示
しているように、ダイオードブリッジと、ＩＬＬとＩＬ
Ｈの２つの定電流源と、ＶＴのスレッショルド電圧源で
構成されている。ダイオードブリッジであるからＤＵＴ
１０に接続されている一端ａの電圧はＶＴに接続されて
いる他端ｂの電圧と等しい。従ってスレショルド電圧源
ＶＴの電圧を可変することにより、ＤＵＴ１０側の一端
ａの電圧を可変することができる。The programmable load PL20 includes a diode bridge, ILL and IL, as shown in FIG.
It is composed of two H constant current sources and a VT threshold voltage source. DUT because it is a diode bridge
The voltage at one end a connected to 10 is equal to the voltage at the other end b connected to VT. Therefore, by changing the voltage of the threshold voltage source VT, the voltage of the one end a on the DUT 10 side can be changed.
【００１０】ＤＵＴ１０の出力レベルを、仮にＨ（ハ
イ）レベルＶOHと、Ｌ（ロウ）レベルＶOLとし、ＶＴの
電圧値をその中間値、つまりＶＴ＝（ＶOH＋ＶOL）／
２、に設定すると、ＤＵＴ１０の出力レベルがＨレベル
のときには出力ピンから負荷電流ＩＬＨがＰＬ２０に流
れ出る。逆に出力レベレがＬレベルのときにはＰＬ２０
側からＤＵＴ１０側に負荷電流ＩＬＬが流れ込む。負荷
電流ＩＬＨ及びＩＬＬはスペックシート中の値を選択し
一定負荷電流ＩＬＨあるいはＩＬＬを流している。The output level of the DUT 10 is assumed to be H (high) level VOH and L (low) level VOL, and the voltage value of VT is an intermediate value thereof, that is, VT = (VOH + VOL) /
When set to 2, when the output level of the DUT 10 is H level, the load current ILH flows out from the output pin to the PL 20. Conversely, when the output level is L level, PL20
Side, the load current ILL flows into the DUT 10 side. For the load currents ILH and ILL, the values in the spec sheet are selected and the constant load current ILH or ILL is passed.
【００１１】[0011]
【発明が解決しようとする課題】従来のドライバＩＣの
出力抵抗の測定方式は、上述のように、図４（Ａ）から
図４（Ｄ）のものであった。どの測定方式でも出力抵抗
の測定はでき、その値はＤＵＴの種類によって異なるが
約３００Ωから数キロΩであって、一般的に数百Ω程度
である。ところが、それぞれの測定方式での測定値には
再現性があるが、方式を変更するとその測定値が異なる
ことが多かった。As described above, the conventional method of measuring the output resistance of the driver IC is that shown in FIGS. 4 (A) to 4 (D). The output resistance can be measured by any measurement method, and the value is about 300 Ω to several kilo Ω, which is generally about several hundred Ω, although it varies depending on the type of DUT. However, although the measurement values of each measurement method have reproducibility, the measurement values were often different when the method was changed.
【００１２】測定方法は、いずれも全ての出力ピンＯＵ
Ｔｉから一定電圧を出力するようにしてスイッチで切り
替えて測定したり、同時測定を行っている。出力抵抗値
の測定方式による測定値の差は±１００Ω程度もあっ
た。これでは出力抵抗値に測定方式を付記する必要があ
り、不便であり、しかも不正確である。The measuring method is all output pins OU.
A constant voltage is output from Ti, and a switch is used to perform measurement or simultaneous measurement is performed. The difference between the measured values of the output resistance measurement method was about ± 100Ω. This is inconvenient and inaccurate because it is necessary to add a measurement method to the output resistance value.
【００１３】その原因はＤＵＴ１０の種類や設計にもよ
るが、各出力ピンの電源と出力抵抗が独立したものでは
なく、出力部門のいくつかのブロック内では相互に関連
を持ち、干渉していることが判明した。ここで干渉と
は、インダクタンスやキャパシタンスによる電磁誘導等
の干渉のみではなく、分圧抵抗回路等の繋がり方による
干渉が大きいと判断される。そして、上述の測定方式で
は図４（Ａ）の方式が出力ピン間で干渉が無く、正しく
測定できることが判った。従って、図４（Ｂ）から図４
（Ｄ）までの測定方式では測定値に補正値を付加する必
要があった。The cause depends on the type and design of the DUT 10, but the power supply and the output resistance of each output pin are not independent, and in some blocks of the output department, they are mutually related and interfere with each other. It has been found. Here, it is determined that the interference is not only interference such as electromagnetic induction due to inductance and capacitance, but also interference due to the way in which the voltage dividing resistance circuit is connected. Then, it was found that in the above-mentioned measurement method, the method of FIG. 4 (A) has no interference between the output pins and can perform correct measurement. Therefore, from FIG. 4 (B) to FIG.
In the measuring methods up to (D), it was necessary to add a correction value to the measured value.
【００１４】この発明は、従来測定方式を検討し、図４
（Ａ）の測定結果と同じ値を得るために図４（Ｄ）の方
式を改良し、出力ピン間の干渉を無くし、高精度に、高
速にしかも比較的安価に構成できるドライバＩＣの出力
抵抗測定器を提供するものである。In the present invention, the conventional measurement method is examined, and FIG.
In order to obtain the same value as the measurement result of (A), the method of FIG. 4 (D) is improved, interference between output pins is eliminated, and the output resistance of the driver IC can be configured with high accuracy, high speed, and relatively inexpensively. A measuring instrument is provided.
【００１５】[0015]
【課題を解決するための手段】上記目的を達成するため
に、本発明は従来測定方式の図４（Ｄ）の回路方式を検
討し、実験を重ね、高速スキャナを利用して電圧測定器
は１台で、高精度に、比較的高速で測定できるようにし
たものである。In order to achieve the above object, the present invention examines the circuit system of FIG. 4 (D) which is a conventional measuring system, repeats experiments, and uses a high-speed scanner to determine a voltage measuring device. This is a device that enables high-accuracy measurement at a relatively high speed.
【００１６】この回路方式は、ＤＵＴ内部の電流の干渉
を打ち消すようにプログラマブルロードＰＬのスレッシ
ョルド電圧源を２系統設けるようにし、１系統のスレッ
ショルド電圧ＶＴ１はＤＵＴの出力電圧よりも一定電圧
高くし、他の系統のＶＴ２は逆に一定電圧低くし、その
ＶＴ１とＶＴ２の電圧系のＰＬをＤＵＴの出力ピンの配
列に交互に、あるいは２つ毎に、あるいは３つ毎に配列
設置して、ＰＬからＤＵＴ内部に電流を流し込みあるい
は引き込んでＤＵＴ内部の電流の干渉を打ち消すように
した。In this circuit system, two threshold voltage sources of the programmable load PL are provided so as to cancel the interference of the current inside the DUT, and the threshold voltage VT1 of one system is made constant higher than the output voltage of the DUT. On the contrary, the VT2 of the other system is lowered by a constant voltage, and the PLs of the VT1 and VT2 voltage systems are alternately arranged in the arrangement of the output pins of the DUT, or arranged every two or three, and the PL is arranged. Therefore, a current is caused to flow in or out of the DUT to cancel the interference of the current inside the DUT.
【００１７】ＤＵＴ内部の回路構成は種類により、ある
いは製造会社により設計が異なっている。ＤＵＴ内部の
電圧源と出力ピンとが１対１に対応して出力抵抗が一定
の場合もあるが、出力ピンをいくつかのブロックに分割
し１ブロックで１つの電圧源の電圧を分圧して複数の出
力ピンに対応しているのものが多い。回路方式はさまざ
まである。従って、どのような回路方式であっても再現
性のある測定値を求めるには、ＤＵＴ内部の電流バラン
スをとるのがよい。The circuit configuration inside the DUT differs in design depending on the type or manufacturing company. There is a case where the voltage resistance inside the DUT and the output pin correspond to each other in a one-to-one manner and the output resistance is constant, but the output pin is divided into several blocks, and the voltage of one voltage source is divided by one block to obtain a plurality of voltages. Many are compatible with the output pin of. There are various circuit systems. Therefore, in order to obtain a reproducible measurement value with any circuit method, it is preferable to balance the current inside the DUT.
【００１８】そこで、出力抵抗の測定において、ＤＵＴ
から一定の電流を引き出し、また同量の電流を与えてや
るとＤＵＴ内部の電流分布に干渉が生ぜず、正確な出力
抵抗測定ができることがわかった。これも１ブロック毎
に同量の電流の出し入れがあるのが望ましい。そこでＤ
ＵＴの出力ピンの配列順に、交互に出し入れを行うか、
２ピン毎に行うか、あるいは複数ピン毎に行ってもよい
が、１ブロックの出力ピン数が不明確であるので、１ピ
ン毎に交互に行うのが望ましい。Therefore, in measuring the output resistance, the DUT
It was found that when a constant current was drawn from the device and the same amount of current was applied, the current distribution inside the DUT did not interfere, and accurate output resistance measurement was possible. Also in this case, it is desirable that the same amount of current be supplied and output for each block. So D
Whether to take in and out alternately in the order of arrangement of the UT output pins,
It may be performed every two pins or every plural pins, but it is desirable to alternately perform every one pin because the number of output pins in one block is unclear.
【００１９】[0019]
【発明の実施の形態】第１の発明は、ＤＵＴの各出力ピ
ンＯＵＴｉ（ｉ＝１〜ｍ）に対応する入力端子を有する
高速スキャナと、その高速スキャナの各入力端子の電圧
を順次測定する電圧測定器と、上記ＤＵＴの各出力ピン
ＯＵＴｉと上記高速スキャナの各入力端子にそれぞれ設
置された２系統のプログラムロードＰＬ群で構成されて
いる。BEST MODE FOR CARRYING OUT THE INVENTION A first aspect of the present invention is a high-speed scanner having an input terminal corresponding to each output pin OUTi (i = 1 to m) of a DUT, and a voltage at each input terminal of the high-speed scanner is sequentially measured. It is composed of a voltage measuring device and two groups of program load PL groups respectively installed at the output pins OUTi of the DUT and the input terminals of the high-speed scanner.
【００２０】その２系統のプログラムロードＰＬ群と
は、スレッショルド電圧源の電圧がＤＵＴの出力電圧よ
りも一定電圧高いＶＴ１群と一定電圧低いＶＴ２群の２
系統の電圧を設定できるプログラムロードＰＬ群であ
る。そして、一定電圧高いＶＴ１群からは一定負荷電流
をＰＬからＤＵＴに流し込む。また一定電圧低いＶＴ２
群はＤＵＴから一定負荷電流を吸い込む。ＤＵＴが流し
出す負荷電流と吸い込む負荷電流が等しいとＤＵＴ内部
では電流のバランスがとれて、干渉は無くなる。従来の
ＰＬのスレッショルド電圧源は、ＤＵＴのＨレベルとＬ
レベルの中間にしかスレショルド電圧を設定できなかっ
たので全ピンからの電流の垂れ流しか吸い込みしかでき
ずに干渉を生じていたのである。The two groups of program load PL groups are a VT1 group in which the voltage of the threshold voltage source is higher than the DUT output voltage by a constant voltage and a VT2 group in which the voltage is lower than the DUT output voltage.
It is a program load PL group that can set the voltage of the system. Then, a constant load current is fed from PL to the DUT from the VT1 group having a high constant voltage. In addition, VT2 with low constant voltage
The swarm draws a constant load current from the DUT. If the load current discharged by the DUT and the load current absorbed by the DUT are equal, the current is balanced inside the DUT, and the interference is eliminated. Conventional PL threshold voltage sources are DUT H level and L
Since the threshold voltage could be set only in the middle of the level, only the drooping current from all pins could be absorbed, causing interference.
【００２１】第２の発明は、第１の発明におけるスレッ
ショルド電圧源の配列をＶＴ１とＶＴ２とを交互に配列
した構成に限定したＰＬ群で成っている。ＤＵＴの設計
がどうなっているのか、いくつのブロックに分けられて
いるのか一般にはわからない。そこでＶＴ１とＶＴ２と
を１つ置きに交互に配列する構成がＤＵＴ内部の電流バ
ランスをとるのにもっとも良い構成である。The second invention comprises a PL group in which the arrangement of the threshold voltage sources in the first invention is limited to a configuration in which VT1 and VT2 are alternately arranged. It is generally unknown how the DUT is designed and how many blocks it is divided into. Therefore, a configuration in which every other VT1 and VT2 are alternately arranged is the best configuration for balancing the current inside the DUT.
【００２２】第３の発明は、ＤＵＴのカタログで２種類
以上の異なる出力抵抗を有するＤＵＴの出力抵抗の測定
器である。電位差が同じであって抵抗値が異なると、そ
の抵抗に流れる電流値は抵抗値に反比例して変化するに
は公知である。従って出力抵抗値が異なる出力段を有す
るＤＵＴの測定ではＰＬの定電流源も２系統以上の定電
流源を有する必要がある。以下実施例について説明す
る。A third aspect of the present invention is an output resistance measuring instrument of a DUT having two or more different output resistances in the DUT catalog. It is known that when the potential difference is the same and the resistance value is different, the current value flowing through the resistance changes in inverse proportion to the resistance value. Therefore, in the measurement of a DUT having output stages having different output resistance values, the PL constant current source also needs to have two or more constant current sources. Hereinafter, embodiments will be described.
【００２３】[0023]
【実施例】図１には本発明の一実施例の構成図を、図２
には他の実施例の構成図を示す。図４、図５と対応する
部分には同一符号を付す。図１について説明する。ＤＵ
Ｔ１０の出力段は電圧源１１ｉ（ｉ＝１〜ｍ）から出力
抵抗１２ｉを通して出力ピンに接続されている。各出力
ピンはそれぞれ高速スキャナ１６の入力端子と接続さ
れ、高速スキャナ１６では各入力端子の電圧をスキャン
してその電圧値を電圧測定器１７で順次読み込んでい
る。1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 9 shows a configuration diagram of another embodiment. The parts corresponding to those in FIGS. 4 and 5 are designated by the same reference numerals. FIG. 1 will be described. DU
The output stage of T10 is connected to the output pin from the voltage source 11i (i = 1 to m) through the output resistor 12i. Each output pin is connected to an input terminal of the high speed scanner 16, and the high speed scanner 16 scans the voltage of each input terminal and sequentially reads the voltage value by the voltage measuring device 17.
【００２４】複数のプログラマブルロード２０ｉは、Ｄ
ＵＴ１０の出力ピンと高速スキャナ１６の入力端子の間
にそれぞれ設置されて接続されている。プログラマブル
ロード２０の構成は前述の図５の通りである。そしてス
レッショルド電圧源ＶＴはＶＴ１群とＶＴ２群とがあ
り、図１においてはＶＴ１とＶＴ２とがＤＵＴ１０の出
力ピンの配列に対して交互に設置されている。従って、
ＶＴ１のＰＬ２０からはＤＵＴ１０側に一定負荷電流が
流れ出し、ＶＴ２のＰＬ２０には一定負荷電流が流れ込
む。The plurality of programmable loads 20i are D
They are installed and connected between the output pin of the UT 10 and the input terminal of the high speed scanner 16, respectively. The configuration of the programmable load 20 is as shown in FIG. The threshold voltage source VT has a VT1 group and a VT2 group, and in FIG. 1, VT1 and VT2 are alternately arranged with respect to the arrangement of the output pins of the DUT 10. Therefore,
A constant load current flows from the PL20 of the VT1 to the DUT10 side, and a constant load current flows into the PL20 of the VT2.
【００２５】ＤＵＴ１０において、吸い込む一定負荷電
流と吐き出す一定負荷電流が同量であると、ＤＵＴ１０
内部において電流バランスがとれて、干渉が無くなり、
出力抵抗値は高精度に、再現性よく、高速に測定するこ
とができる。In the DUT 10, if the constant load current drawn in and the constant load current discharged are the same, the DUT 10
The current is balanced inside and there is no interference,
The output resistance value can be measured with high accuracy, good reproducibility, and high speed.
【００２６】図２には、カタログ上で２種類以上の異な
る出力抵抗を有するＤＵＴ１０の測定の構成図を示す。
図１と異なる点は、プログラマブルロードＰＬ２０の定
電流源を２系統有することである。つまり、ＩＬＬ１と
ＩＬＨ１の組の定電流源を有するＰＬ２０とＩＬＬ２と
ＩＬＨ２との組の定電流源を有するＰＬ２０とが存在
し、ＤＵＴ１０の出力抵抗が異なっても適切な一定負荷
電流を供給することができる構成となっている。FIG. 2 shows a measurement configuration diagram of the DUT 10 having two or more different output resistances on the catalog.
The difference from FIG. 1 is that the programmable load PL20 has two constant current sources. That is, there is a PL20 having a constant current source of a set of ILL1 and ILH1 and a PL20 having a constant current source of a set of ILL2 and ILH2, and an appropriate constant load current is supplied even if the output resistance of the DUT 10 is different. It is configured to be able to.
【００２７】[0027]
【発明の効果】以上詳細に説明したように、この発明
は、ＬＣＤドライバＩＣやバブルジェットプリンタドラ
イバＩＣのように多数ピンを有するドライバＩＣの出力
抵抗を測定する測定器において、高精度に、再現性がよ
く、比較的高速に、比較的安価に構成することができ
る。As described in detail above, the present invention can be reproduced with high accuracy in a measuring instrument for measuring the output resistance of a driver IC having a large number of pins such as an LCD driver IC and a bubble jet printer driver IC. It has good performance and can be constructed at a relatively high speed and at a relatively low cost.
【００２８】従って、テストコストも安価にでき、しか
も益々出力ピン数が多くなっている現状において、その
利用価値は高く、技術的効果は大である。Therefore, under the present circumstances where the test cost can be reduced and the number of output pins is increasing more and more, its utility value is high and the technical effect is great.
【図１】本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.
【図２】本発明の他の実施例の構成図である。FIG. 2 is a configuration diagram of another embodiment of the present invention.
【図３】ＤＵＴ１０を説明するための一例のＤＵＴ１０
の外観図である。FIG. 3 is an example DUT 10 for explaining the DUT 10.
FIG.
【図４】図４（Ａ）から図４（Ｄ）は、従来のＤＵＴ１
０の出力抵抗を測定するための構成図である。FIG. 4A to FIG. 4D are conventional DUT1s.
It is a block diagram for measuring the output resistance of 0.
【図５】ＰＬ２０の一例の構成図である。FIG. 5 is a configuration diagram of an example of a PL20.
１０ ＤＵＴ（多数ピンを有するドライバＩＣ） １１ｉ 電圧源 １２ｉ 出力抵抗 １５ｉ ＤＣ測定ユニット １６ 高速スキャナ １７ 電圧測定器 ２０ｉ ＰＬ（プログラマブルロード） ＶＴ スレッショルド電圧源 10 DUT (driver IC having many pins) 11i voltage source 12i output resistance 15i DC measuring unit 16 high-speed scanner 17 voltage measuring device 20i PL (programmable load) VT threshold voltage source
Claims (3)
るＤＵＴ（１０）の直流特性を測定する出力抵抗測定器
において、 ＤＵＴ（１０）の各出力ピンＯＵＴｉにそれぞれ接続す
る入力端子を有する高速スキャナ（１６）と、 上記高速スキャナ（１６）の各入力端子の電圧を順次測
定する電圧測定器（１７）と、 上記ＤＵＴ（１０）の各出力ピンＯＵＴｉと上記高速ス
キャナ（１６）の各入力端子との間にそれぞれ設置さ
れ、スレッショルド電圧がＤＵＴ（１０）の出力電圧よ
りも一定電圧高い電圧を設定できるスレッショルド電圧
源ＶＴ１群と一定電圧低い電圧を設定できるスレッショ
ルド電圧源ＶＴ２群との２系統の電圧を設定できるプロ
グラムロードＰＬ（２０ｉ）群と、 を具備することを特徴とするドライバＩＣの出力抵抗測
定器。1. An output resistance measuring instrument for measuring a DC characteristic of a DUT (10) which is a driver IC having a large number of output pins, comprising: a high-speed scanner having an input terminal connected to each output pin OUTi of the DUT (10). 16), a voltage measuring device (17) for sequentially measuring the voltage of each input terminal of the high speed scanner (16), each output pin OUTi of the DUT (10) and each input terminal of the high speed scanner (16). And a threshold voltage source VT1 group capable of setting a voltage whose threshold voltage is higher than the output voltage of the DUT (10) by a constant voltage and a threshold voltage source VT2 group capable of setting a lower voltage by a constant voltage. Output load measuring instrument for driver IC, comprising:
（２０ｉ）群は、スレッショルド電圧源ＶＴ１とＶＴ２
とがＤＵＴ１０の各出力ピンＯＵＴｉの配列順に交互に
配列されている２系統のプログラムロードＰＬ（２０
ｉ）群であることを特徴とするドライバＩＣの出力抵抗
測定器。2. The program load PL according to claim 1.
The group (20i) includes threshold voltage sources VT1 and VT2.
And program load PL (20) in which and are alternately arranged in the order of arrangement of the output pins OUTi of the DUT 10.
i) An output resistance measuring device of a driver IC, which is a group.
（２０ｉ）群は、定電流源ＩＬＬ及びＩＬＨが出力電流
の異なる２系統（ＩＬＬ１、ＩＬＨ１とＩＬＬ２、ＩＬ
Ｈ２）以上の定電流源を有しているプログラムロードＰ
Ｌ（２０ｉ）群であることを特徴とするドライバＩＣの
出力抵抗測定器。3. The program load PL according to claim 1.
In the group (20i), the constant current sources ILL and ILH are two systems (ILL1, ILH1 and ILL2, IL) having different output currents.
H2) Program load P having a constant current source above
An output resistance measuring device for a driver IC, which is an L (20i) group.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02732996A JP3638697B2 (en) | 1996-01-22 | 1996-01-22 | Driver IC output resistance measuring instrument |
| TW085114963A TW315417B (en) | 1996-01-22 | 1996-12-04 | |
| CN97102239A CN1115565C (en) | 1996-01-22 | 1997-01-15 | Output resistance tester for driver integrated circuit and testing method thereof |
| KR1019970000971A KR100248918B1 (en) | 1996-01-22 | 1997-01-15 | Device and method for measuring output resistance of driver ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02732996A JP3638697B2 (en) | 1996-01-22 | 1996-01-22 | Driver IC output resistance measuring instrument |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09196998A true JPH09196998A (en) | 1997-07-31 |
| JP3638697B2 JP3638697B2 (en) | 2005-04-13 |
Family
ID=12218040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02732996A Expired - Fee Related JP3638697B2 (en) | 1996-01-22 | 1996-01-22 | Driver IC output resistance measuring instrument |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3638697B2 (en) |
| KR (1) | KR100248918B1 (en) |
| CN (1) | CN1115565C (en) |
| TW (1) | TW315417B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003057284A (en) * | 2001-08-10 | 2003-02-26 | Advantest Corp | Apparatus and method of testing semiconductor |
| JP2005265756A (en) * | 2004-03-22 | 2005-09-29 | Yokogawa Electric Corp | Ic tester |
| KR100815537B1 (en) * | 2005-10-11 | 2008-03-20 | 요코가와 덴키 가부시키가이샤 | Ic tester |
| JP2008107173A (en) * | 2006-10-25 | 2008-05-08 | Yokogawa Electric Corp | Ic tester |
| TWI793179B (en) * | 2017-09-27 | 2023-02-21 | 日商日本電產理德股份有限公司 | Resistance measuring device, substrate inspection device, and resistance measuring method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6940301B2 (en) * | 2003-12-12 | 2005-09-06 | Au Optronics Corporation | Test pad array for contact resistance measuring of ACF bonds on a liquid crystal display panel |
-
1996
- 1996-01-22 JP JP02732996A patent/JP3638697B2/en not_active Expired - Fee Related
- 1996-12-04 TW TW085114963A patent/TW315417B/zh not_active IP Right Cessation
-
1997
- 1997-01-15 CN CN97102239A patent/CN1115565C/en not_active Expired - Fee Related
- 1997-01-15 KR KR1019970000971A patent/KR100248918B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003057284A (en) * | 2001-08-10 | 2003-02-26 | Advantest Corp | Apparatus and method of testing semiconductor |
| JP2005265756A (en) * | 2004-03-22 | 2005-09-29 | Yokogawa Electric Corp | Ic tester |
| KR100815537B1 (en) * | 2005-10-11 | 2008-03-20 | 요코가와 덴키 가부시키가이샤 | Ic tester |
| JP2008107173A (en) * | 2006-10-25 | 2008-05-08 | Yokogawa Electric Corp | Ic tester |
| TWI793179B (en) * | 2017-09-27 | 2023-02-21 | 日商日本電產理德股份有限公司 | Resistance measuring device, substrate inspection device, and resistance measuring method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1164649A (en) | 1997-11-12 |
| TW315417B (en) | 1997-09-11 |
| CN1115565C (en) | 2003-07-23 |
| KR100248918B1 (en) | 2000-03-15 |
| KR970059759A (en) | 1997-08-12 |
| JP3638697B2 (en) | 2005-04-13 |
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