CN1164649A - Output resistance tester for driver integrated circuit and testing method thereof - Google Patents
Output resistance tester for driver integrated circuit and testing method thereof Download PDFInfo
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- CN1164649A CN1164649A CN97102239A CN97102239A CN1164649A CN 1164649 A CN1164649 A CN 1164649A CN 97102239 A CN97102239 A CN 97102239A CN 97102239 A CN97102239 A CN 97102239A CN 1164649 A CN1164649 A CN 1164649A
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- output resistance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/08—Measuring resistance by measuring both voltage and current
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides an output impedance tester for testing the output impedance of a drive IC which is provided with a plurality of tube legs, with high precision, high speed and low price, as well as the testing method. A high-speed scanner is used to receive output voltages of a plurality of output tube legs from a DUT and a voltage tester is used to test the voltage successively to evaluate the output impedance. A programmable load PL which is arranged between the output tube legs and the input terminals is structured to set the voltages of two systems of VT1 group and VT2 group of threshold voltage sources which are respectively one constant voltage higher and one constant voltage lower than the output voltage. The programmable load PL group releases constant load current in the VT1 group and absorbs the constant load current in the VT2 group.
Description
The present invention relates to such as output resistance tester and method of testing thereof that the output resistance of the driver IC that a plurality of efferent duct legs are arranged of LCD (liquid crystal) driver IC and bubble-jet printer (bubble jet printer) driver IC and so on is tested.
Shown in Fig. 3 is the example that the driver IC 10 of a plurality of pipe legs is arranged.Though pipe leg number is different because of kind, having much is 160 pipe leg to 300 pipe legs.Supply voltage is linked power supply terminal V
DDOr the like go up and ground terminal GND ground connection come drive IC.On a plurality of input terminal INi (i=1-n), add control signal from the outside, and send the order of efferent duct leg name and output voltage thereof by this control signal.Such as output voltage values is 8 a signal, the order that can send 256 grades.The efferent duct leg that receives order from a plurality of efferent duct leg OUTi (i=1-m) supplies to the specified constant voltage values of order in the outside load.
There are a plurality of efferent duct leg OUTi of the driver IC (below be referred to as " DUT ") 10 of this a plurality of pipe legs must be correctly to supply with electric current and voltage by the control signal appointment to load.And output resistance also must requirement up to specification.So always will test output voltage, output current and the output resistance of each DUT10 to check whether this DUT10 is qualified in the manufacture process of DUT10 or after making or in the warehouse-in inspection.
Fig. 4 shows existing test mode.
DC test cell 15 is voltage testers of built-in constant current source.Also can suck the constant current of arbitrary value owing to spuing, so can set output current I by switch
L, can measure the output voltage V of DUT10
O, can measure output resistance R again
OOutput resistance R
OIt is the output voltage V when non-loaded
OMagnitude of voltage V when load is arranged
MDifference by load current I
LThe value of removing.Be R if be formulated then to become
O=(V
O-V
M)/I
LLoad voltage value V
MMeasure by voltage tester.
Fig. 4 (A) is with adding electric current voltage determination pattern, test the method for output voltage of the individual efferent duct leg OUTi of majority of DUT10 while switching with a DC test cell 15, one next pipe legs.Because DC test cell 15 has only one, so though cost is low, spended time and too slow too.
Fig. 4 (B) is provided with Nch (n road) DC test cell 15 and tests the test that the switching of every N pipe leg is once tested with adding electric current voltage tester pattern simultaneously.Test duration and Fig. 4 (A) are though than becoming 1/N.But owing to need the DC test cell 15j (j=1-N) of Nch, so the cost height.
Fig. 4 (C) be have DUT10 whole efferent duct leg OUTi (i=1-m) amount so a plurality of DC test cell 15i and add the method for testing that electric current voltage tester pattern is once tested whole efferent duct leg OUTi.So, the very high speed though the test duration becomes, because the so a plurality of DC test cells 15 of amount of whole efferent duct leg OUTi will be set, so price also becomes height extremely.
Fig. 4 (D) has prepared the programmable load PL20i that will connect respectively to whole efferent duct leg OUTi (i=1-m) of DUT10.Each efferent duct leg of DUT10 is then linked on the input terminal separately of high speed scanner 16.PL20i adds electric current to DUT10, and voltage determination is undertaken by high speed scanner 16 with a voltage tester 17.Because electric current is not to voltage tester 17 1 effluents, so can use high speed scanner.This mode can be tested more at high speed and be relatively more cheap.
Programmable load PL20 as shown in Figure 5, by diode bridge, two constant current source ILL and ILH, threshold voltage source VT constitutes.Owing to be diode bridge, equate with the voltage of linking the other end b on the VT so be connected to the voltage of the end a on the DUT10.Thereby employing makes the way of the voltage variable of threshold voltage source VT.Just can make the voltage variable of an end a of DUT10 one side.
Suppose the output level of DUT10 is set at H (height) level V
OHAnd L (low) level V
OL, the magnitude of voltage of VT hypothesis is decided to be its intermediate value, i.e. VT=(V
OH+ V
OL)/2, then when the output level of DUT10 was the H level, load current ILH flowed to PL20 from the efferent duct leg.Conversely, when output level was the L level, load current ILL was from PL20 one side inflow DUT10 one side.Load current ILH and ILL select the value in the instructions, make and his like persevering fixed load current ILH or ILL.
The mensuration mode of the output impedance of already existing driver ICs as mentioned above, is the mode from Fig. 4 (A) to Fig. 4 (D).Though no matter which kind of test mode all can measure output resistance, its value, be approximately 300 Ω-thousands of Ω, be generally about hundreds of Ω with because of the kind of DUT is different.Yet though with the measured measured value of test mode separately repeatability is arranged, when change mensuration mode, its measured value is scarcely the same.
Method of testing, though any all be to make from the constant voltage of whole efferent duct leg OUTi output, switch or measure simultaneously with switch.But the difference that sometimes can make measured value because of the difference of the test mode of output resistance is for about ± 100 Ω.Therefore will be on output resistance affix test mode, both inconvenience and become and be incorrect measured value.
Its reason is also different because of kind or the design of DUT10, but knows: the power supply of each efferent duct leg and output resistance are not independent, but connection thereby phase mutual interference are arranged in several pieces of output mutually.Said here interference has come to understand to be not only the interference of electromagnetic induction of producing of inductance or electric capacity or the like, and the interference that produces because of the method for attachment of divider resistance circuit is big.So, can know in above-mentioned test mode that the mode of Fig. 4 (A) is not disturbed, so can correctly measure between the efferent duct leg.Thereby, from Fig. 4 (B) to the test mode of Fig. 4 (D), must add modified value to measured value.
The present invention discusses existing test mode, in order to obtain the identical value of test result with Fig. 4 (A), mode to Fig. 4 (D) improves, provide a kind of interference that can eliminate between the pipe leg, the output resistance tester of the driver IC that can constitute accurately, at high speed and more cheaply.
In addition, in order to obtain the identical value of test result with Fig. 4 (A), also improved test mode, provide a kind of can eliminate interference between the efferent duct leg, can be accurately, at high speed and the output resistance method of testing of the driver IC that can constitute more cheaply.
The present invention is that the circuit mode of a kind of Fig. 4 (D) to existing test mode is discussed, and experimentizes repeatedly, utilizes high speed scanner to do to become and makes with 1 voltage tester, just can be accurately and the proving installation to test than higher speed.
Also the ground method of testing improves in addition, and a kind of interference that can eliminate between the efferent duct leg is provided, and can constitute accurately the method for the output resistance of test driver IC at high speed.
At first, the output resistance tester to driver IC describes.
This circuit mode does to become the threshold voltage source of the programmable load PL that 2 systems are set to eliminate the current interference of DUT inside, and make the threshold voltage VT1 of a system than the high constant voltage of output voltage of DUT, make low conversely constant voltage of VT2 of another system, and the PL of the electrical voltage system of this VT1 and VT2 for the arrangement of the efferent duct leg of DUT alternatively or per two ground or per three ground arrange, make by PL to the inner inflow current of DUT or introduce the interference of electric current with the electric current of offsetting DUT inside.
The circuit of DUT inside constitute because of kind or because of manufacturing firm's different designs also different.1 pair 1 ground of the voltage source of DUT inside and efferent duct leg is corresponding and output resistance is constant sometimes, but most applications is that the efferent duct leg is divided into several pieces, and in 1 piece the voltage of 1 voltage source is carried out dividing potential drop and make it corresponding with a plurality of efferent duct legs.Circuit mode is diversified.Therefore,, seek out the measured value of repeatability, the DUT internal current is made even weighing apparatus just no matter be which type of circuit mode.
So learn, in the mensuration of output resistance, when from DUT, drawing constant electric current and give electric current with amount, just can measure correct output resistance and can not produce and disturb to the electric current composition of DUT inside.This method it is desirable to also will have for each piece the inflow and outflow of the electric current of equivalent.Therefore, though can alternatively carry out inflow and outflow or per two pipe legs carry out inflow and outflow for putting in order of the efferent duct leg of DUT, perhaps every a plurality of pipe leg carries out inflow and outflow, but because the efferent duct leg number of a piece is indefinite, alternatively carries out so it is desirable to each pipe leg.
The 1st aspect of the present invention is by the high speed scanner that has with each efferent duct leg OUTi (i=1-m) corresponding input end of DUT, and the voltage tester that the voltage of each input terminal of this high speed scanner is measured, the programmable load PL group that is arranged at 2 systems on each input terminal of each the efferent duct leg OUTi of above-mentioned DUT and above-mentioned high speed scanner respectively constitute in turn.
The programmable load PL group of so-called this 2 system, but be the programmable load PL group of setting voltage of these two systems of VT2 group of the VT1 group of the high constant voltage of output voltage of voltage ratio DUT in threshold voltage source and a low constant voltage.So, the VT1 group of a high constant voltage flows into constant load current from PL to DUT, and the VT2 group of a low constant voltage then sucks the constant load electric current from DUT.If the load current that DUT flows out equates with the load current of suction then in DUT internal current balance, the interference disappearance.Because the threshold voltage source of existing P L can only be set in threshold voltage the centre of H level and the L level of DUT, disturb so can only suck from the electric current thereby the generation of all pipe legs.
The 2nd aspect of the present invention makes VT1 and VT2 alternatively arrange formation PL group with the arrangement in the threshold voltage source in the 1st aspect is defined as.What kind of the design of DUT is, is divided into what pieces, generally do not know.So the formation that VT1 and VT2 are arranged alternately alternately is a kind of best formation for the current balance type that makes DUT inside.
The 3rd aspect of the present invention is a kind of output resistance tester that has the DUT of two or more different output resistances on the instructions of DUT.Well-known if potential difference (PD) is identical the resistance value difference, then current value that flows in this resistance and resistance value change inversely.Therefore, in the mensuration of the DUT with the different output stage of output resistance, the constant current source of PL also must have the above constant current source of 2 systems.
Secondly, the output resistance method of testing to driver IC describes.
At first, threshold voltage is set at programmable load usefulness than the VT1 of the also high constant voltage of output voltage of DUT, in addition, the VT2 of a low constant voltage is set at programmable load uses.
Secondly, the PL of VT1 is linked on the purpose pipe leg.Again VT1 and VT2 are at random linked on remaining pipe leg.But the sum that will make VT1 group is total consistent with VT2 group's.In this state, measure the output resistance of purpose pipe leg.
Similarly, the PL of VT2 is linked on the purpose pipe leg.Again VT1 and VT2 are at random linked on other the pipe leg.But the sum that makes VT2 group is total consistent with VT1 group's.In this state, measure the output resistance of purpose pipe leg.
Secondly, purpose pipe leg is assigned to another pipe leg and changes and repeat above-mentioned each determination step.Carry out this process repeatedly all purpose pipe legs are measured output resistance.
By adopting the way of the output resistance of measuring driver IC in this wise, because the constant load electric current that absorbs in DUT10 is an equivalent with the constant load electric current that spues, thus DUT10 internal current balance, disturb disappearance, output resistance can be accurately, repeatability well, test at high speed.
In addition, also can measure with same step with the DC determination unit of built-in constant current source without PL.
Fig. 1 is the pie graph of one embodiment of the present of invention.
Fig. 2 is the pie graph of another embodiment of the present invention.
Fig. 3 is the outside drawing of DUT10 that is used to illustrate the example of DUT.
Fig. 4 (A)-Fig. 4 (D) is the existing pie graph that is used for testing the output resistance of DUT10.
Fig. 5 is the pie graph of the example of PL20.
The process flow diagram of Fig. 6 shows an embodiment of method of testing of the present invention.
The process flow diagram of Fig. 7 shows an embodiment of another method of testing of the present invention.
Figure 1 illustrates the pie graph of one embodiment of the present of invention, figure 2 illustrates the pie graph of another embodiment.To giving identical label with the corresponding part of Fig. 4, Fig. 5.
Fig. 1 is described.The output stage of DUT10 is linked voltage source 11i on the efferent duct leg by output resistance 12i (i=1-m).Each efferent duct leg is connected with the input terminal of high speed scanner 16 respectively, in high speed scanner 16, each input terminal is scanned and reads in its magnitude of voltage in turn with voltage tester 17.
Between the efferent duct leg that most programmable load 20i are arranged at DUT10 respectively and the input terminal of high speed scanner 16 and be connected.The formation of programmable load 20 such as above-mentioned shown in Figure 5.Threshold voltage source VT has VT1 group and VT2 group, and in Fig. 1, VT1 and VT2 are provided with arrangement alternately for the efferent duct leg of DUT10.Therefore, the PL20 from VT1 goes out the constant load electric current to DUT10 one effluent.PL20 to VT2 flows into the constant load electric current.
In DUT10, when the constant load electric current that sucks is equivalent with the constant load electric current that spues, the balance that obtains at the internal current of DUT10, disturbs and disappear.So can be accurately, repeatability tests output resistance well, at high speed.
Figure 2 illustrates the pie graph of the test of the DUT10 that two or more different output resistances is arranged in instructions.Be that with the difference of Fig. 1 programmable load PL20 has the constant current source of 2 systems.That is, exist ILL1 and ILH1 so one group constant current source PL20 and so PL20 of constant current source of one group of ILL2 and ILH2 is arranged, even become the formation that also can supply with suitable constant load electric current for the output resistance difference of DUT10.
The process flow diagram of Fig. 6 shows an embodiment of method of testing of the present invention.
At first, threshold voltage is set at programmable load with (step 101) than the VT1 of the high constant voltage of output voltage of DUT.
Secondly, threshold voltage is set at programmable load with (step 102) than the VT2 of the low constant voltage of output voltage of DUT.
Secondly, the PL of VT1 is connected on the purpose pipe leg.Then, VT2 and VT1 are at random linked on other the pipe leg.But the sum that makes VT1 group is total consistent with VT2 group's.In this state, measure the output resistance (step 103) of purpose pipe leg.
Once more, the PL of VT2 is connected on the purpose pipe leg.Then, VT1 and VT2 are at random linked on other the pipe leg.But the sum that makes VT2 group is total consistent with VT1 group's.In this state, measure the output resistance (step 104) of purpose pipe leg.Then, purpose pipe leg is assigned to another pipe leg changes, 103-104 measures with above-mentioned steps.Repeat said process, to whole purpose pipe leg test output resistances (step 105).
By adopting the way of the output resistance of test driver IC in this wise, because in DUT10, the constant load electric current that sucks is an equivalent with the constant load electric current that spues, so in DUT10 internal current balance, eliminated interference, and can be accurately, repeatability is tested output resistance well at high speed.
Fig. 7 is the process flow diagram of another embodiment of explanation method of testing of the present invention.
In the present embodiment, corresponding with the situation of testing with the DC test cell of built-in constant current source.In other words, what illustrate is and Fig. 4 (B) that the hardware of Fig. 4 (C) constitutes the situation of testing accordingly.
At first, the VT1 of threshold voltage than the high constant voltage of output voltage of DUT is set on the DC test cell (step 201).
Secondly, the VT2 of threshold voltage than the low constant voltage of output voltage of DUT is set on the DC test cell (step 202).
Secondly, VT1 is linked on the purpose pipe leg.Next, VT2 and VT1 are at random linked on other the pipe leg.But the sum that will make VT1 group is total consistent with VT2 group's.In this state, the output resistance (step 203) of test purpose pipe leg.
Secondly, VT2 is linked on the purpose pipe leg.Next, VT1 and VT2 are at random linked on other the pipe leg.But VT2 group's sum will make it consistent with VT1 group's sum.In this state, the output resistance (step 204) of test purpose pipe leg.
Secondly, change to and purpose pipe leg is distributed to another pipe leg repeat above-mentioned testing procedure 203-204.Repeat this process repeatedly, to all purpose pipe leg test output resistances (step 205).
By adopting the way of the output resistance of test driver IC in this wise, because in DUT10, the constant load electric current that sucks is an equivalent with the constant load electric current that spues, so be able to balance at the DUT10 internal current, eliminated interference, thus can be accurately, repeatability tests output resistance well, at high speed.
As above explaining, the present invention can be accurately in the testing tool that the output resistances of driver IC that most pipe legs are arranged as lcd driver IC and bubble-jet printer driver IC are tested, and repeatability well, more at high speed, constitute more cheaply.
Therefore, test value also can be cheap, and under the increasing present situation of efferent duct leg, and its value height, technical effect are big.
Claims (5)
1. the output resistance tester of a driver IC is to have in the output resistance tester of the DC characteristic of the DUT (10) of the driver IC of most efferent duct legs in test itself, it is characterized in that:
The high speed scanner (16) that the input terminal that each efferent duct leg OUTi of being connected respectively to DUT (10) gets on is arranged;
Test the voltage tester (17) of voltage of each input terminal of above-mentioned high speed scanner (16) in turn;
Between can each input terminal to each the efferent duct leg OUTi that is arranged at above-mentioned DUT (10) respectively and above-mentioned high speed scanner (16), and can threshold voltage set than the threshold voltage VT1 group of the high constant voltage of output voltage of DUT (10) with can set programmable load PL (20i) group that sets of the voltage of these two systems of threshold voltage source VT2 group of a low constant voltage.
2. the output resistance tester of the described driver IC of claim 1 is characterized in that: described programmable load PL (20i) group is programmable load PL (20i) group of 2 systems that threshold voltage source VT1 and VT2 are alternately arranged according to putting in order of each efferent duct leg OTUi of DUT10.
3. the output resistance tester of the described driver IC of claim 1 is characterized in that: described programmable load PL (20i) group is programmable load PL (20i) group with the above constant current supply of the output current of constant current supply ILL and ILH 2 systems (ILL1, ILH1 and ILL2, ILH2) inequality.
4. the output resistance method of testing of a driver IC is being to have in the output resistance method of testing that the DC characteristic of DUT (10) of the driver IC of most efferent duct legs tests itself, it is characterized in that:
At first, threshold voltage is set at programmable load with (step 101) than the VT1 of the high constant voltage of output voltage of DUT,
Secondly, threshold voltage is set at programmable load with (step 102) than the VT2 of the low constant voltage of output voltage of DUT,
Secondly, the PL of VT1 is linked on the purpose pipe leg, VT2 and VT1 are at random linked on other the pipe leg, still, make the total consistent of VT1 group's sum and VT2 group, the output resistance (step 103) of test purpose pipe leg under this state,
Secondly, the PL of VT2 is linked on the purpose pipe leg, VT1 and VT2 are at random linked on other the pipe leg, still, make the total consistent of VT2 group's sum and VT1 group, the output resistance (step 104) of test purpose pipe leg under this state,
Secondly, change purpose pipe leg is assigned to another pipe leg, repeat above-mentioned testing procedure (103-104), and repeat this process repeatedly, to all purpose pipe leg test output resistances (step 105),
Adopting above-mentioned step, in DUT (10), is under the state of equivalent the output resistance of driver IC to be tested at constant load electric current that sucks and the constant load electric current that spues.
5. the output resistance method of testing of a driver IC is being to have in the output resistance method of testing that the DC characteristic of DUT (10) of the driver IC of most efferent duct legs tests itself, it is characterized in that:
At first, the VT1 than the high constant voltage of output voltage of DUT is set on the DC test cell (step 201) threshold voltage,
Secondly, the VT2 than the low constant voltage of output voltage of DUT is set on the DC test cell (step 202) threshold voltage,
Secondly, VT1 is linked on the purpose pipe leg, VT2 and VT1 are at random linked on other the pipe leg, but the sum that makes VT1 group and VT2 group's is total consistent, the output resistance (step 203) of test purpose pipe leg under this state,
Secondly, VT2 is linked on the purpose pipe leg, VT1 and VT2 are at random linked on other the pipe leg, the sum that still makes VT2 group is total consistent with VT1 group's, the output resistance (step 204) of test purpose pipe leg under this state,
Secondly, change purpose pipe leg is assigned to another pipe leg, repeats above-mentioned testing procedure (203-204), repeat this process repeatedly, to all purpose pipe leg test output resistances (step 205),
Adopt above-mentioned steps, in DUT (10).It at constant load electric current that sucks and the constant load electric current that spues the output resistance of test driver IC under the state of equivalent.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02732996A JP3638697B2 (en) | 1996-01-22 | 1996-01-22 | Driver IC output resistance measuring instrument |
| JP27329/96 | 1996-01-22 | ||
| JP27329/1996 | 1996-01-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1164649A true CN1164649A (en) | 1997-11-12 |
| CN1115565C CN1115565C (en) | 2003-07-23 |
Family
ID=12218040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97102239A Expired - Fee Related CN1115565C (en) | 1996-01-22 | 1997-01-15 | Output resistance tester for driver integrated circuit and testing method thereof |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3638697B2 (en) |
| KR (1) | KR100248918B1 (en) |
| CN (1) | CN1115565C (en) |
| TW (1) | TW315417B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100390548C (en) * | 2003-12-12 | 2008-05-28 | 友达光电股份有限公司 | Method for measuring contact impedance of joint point of liquid crystal display panel and the liquid crystal display panel |
| CN109557376A (en) * | 2017-09-27 | 2019-04-02 | 日本电产理德股份有限公司 | Resistance measurement device, base board checking device and resistance measurement method |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5046448B2 (en) * | 2001-08-10 | 2012-10-10 | 株式会社アドバンテスト | Semiconductor test apparatus and test method thereof |
| JP2005265756A (en) * | 2004-03-22 | 2005-09-29 | Yokogawa Electric Corp | Ic tester |
| JP4596264B2 (en) * | 2005-10-11 | 2010-12-08 | 横河電機株式会社 | IC tester |
| JP5028953B2 (en) * | 2006-10-25 | 2012-09-19 | 横河電機株式会社 | IC tester |
-
1996
- 1996-01-22 JP JP02732996A patent/JP3638697B2/en not_active Expired - Fee Related
- 1996-12-04 TW TW085114963A patent/TW315417B/zh not_active IP Right Cessation
-
1997
- 1997-01-15 KR KR1019970000971A patent/KR100248918B1/en not_active IP Right Cessation
- 1997-01-15 CN CN97102239A patent/CN1115565C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100390548C (en) * | 2003-12-12 | 2008-05-28 | 友达光电股份有限公司 | Method for measuring contact impedance of joint point of liquid crystal display panel and the liquid crystal display panel |
| CN109557376A (en) * | 2017-09-27 | 2019-04-02 | 日本电产理德股份有限公司 | Resistance measurement device, base board checking device and resistance measurement method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09196998A (en) | 1997-07-31 |
| KR970059759A (en) | 1997-08-12 |
| CN1115565C (en) | 2003-07-23 |
| JP3638697B2 (en) | 2005-04-13 |
| KR100248918B1 (en) | 2000-03-15 |
| TW315417B (en) | 1997-09-11 |
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