JP2008107173A - Ic tester - Google Patents

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JP2008107173A
JP2008107173A JP2006289383A JP2006289383A JP2008107173A JP 2008107173 A JP2008107173 A JP 2008107173A JP 2006289383 A JP2006289383 A JP 2006289383A JP 2006289383 A JP2006289383 A JP 2006289383A JP 2008107173 A JP2008107173 A JP 2008107173A
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output
voltage
tester
output pin
level
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JP5028953B2 (en
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Koichiro Kurihara
孝一郎 栗原
Shingo Morita
慎吾 森田
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Yokogawa Electric Corp
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Yokogawa Electric Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/1659—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 to indicate that the value is within or outside a predetermined range of values (window)
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels

Abstract

<P>PROBLEM TO BE SOLVED: To realize an IC tester capable of shortening the inspection time by making the number of measurement time into once at the test mode of L level and H level, without having to use expensive current-impressing/high voltage measurement means. <P>SOLUTION: The IC tester for inspecting the output resistance value of each output pin of the under testing device equipped with a plurality of output pins is provided with reference resistors, connected to each output pin, a reference voltage impressing means for impressing the prescribed reference voltage via these reference resistors, and a voltage measurement means for measuring the voltage generated at each output pin. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、複数の出力ピンを有する被試験デバイスの前記各出力ピンの出力抵抗値を検査するＩＣテスタに関するものである。   The present invention relates to an IC tester for inspecting an output resistance value of each output pin of a device under test having a plurality of output pins.

ＩＣテスタは、被試験デバイス（以下、ＤＵＴ：Device Under Testと略す）、例えばＩＣ，ＬＳＩ等に試験パターンを与え、ＤＵＴの出力と期待値とを比較し、ＤＵＴの良否判定を行うものである。   The IC tester gives a test pattern to a device under test (hereinafter abbreviated as DUT: Device Under Test), for example, IC, LSI, etc., compares the output of the DUT with an expected value, and determines whether the DUT is good or bad. .

ＤＵＴが、複数の出力ピンを有するプラズマディスプレイドライバ等では、このようなロジックテストに加えて、各出力ピンの出力抵抗値を検査する、ＤＣテストが実行される。ＤＣテストを行うＩＣテスタについては、特許文献１に技術開示がある。   In a plasma display driver or the like in which the DUT has a plurality of output pins, in addition to such a logic test, a DC test for inspecting the output resistance value of each output pin is executed. Regarding an IC tester that performs a DC test, Patent Document 1 discloses a technical disclosure.

図３は、特許文献１に従来例（図７）として開示されているＩＣテスタの構成例を示す機能ブロック図である。プラズマディスプレイドライバであるＤＵＴ１は、所定の電源電圧Ｖｃｃが給電され、テスタ制御手段２からの出力レベル切り換え指令により、各出力ピンの電圧が、０〜１０Ｖ程度の低電圧（以下、Ｌレベル）及び５０〜１００Ｖ程度の高電圧（以下、Ｈレベル）の２種類の出力レベルに切り換えられる。   FIG. 3 is a functional block diagram showing a configuration example of an IC tester disclosed in Patent Document 1 as a conventional example (FIG. 7). The DUT 1 which is a plasma display driver is supplied with a predetermined power supply voltage Vcc, and in response to an output level switching command from the tester control means 2, the voltage of each output pin is set to a low voltage of about 0 to 10 V (hereinafter referred to as L level) and The output level is switched to two output levels of high voltage (hereinafter referred to as H level) of about 50 to 100V.

ＤＵＴ１は、ｎ個のドライバＱ１，Ｑ２，…Ｑｎ−１，Ｑｎで構成され、各ドライバの出力抵抗Ｒａ１，Ｒａ２，…Ｒａｎ−１，Ｒａｎは、出力レベルがＬレベルかＨレベルかにより変化し、各出力ピンＰ１，Ｐ２，…Ｐｎ−１，Ｐｎに接続される負荷（プラズマディスプレイパネル）に適切な駆動電圧と電流を供給する。   The DUT 1 is composed of n drivers Q1, Q2,... Qn-1, Qn, and the output resistances Ra1, Ra2, ... Ran-1, Ran of each driver vary depending on whether the output level is L level or H level. .., Pn−1, Pn are supplied with appropriate drive voltages and currents to loads (plasma display panels) connected to the output pins P1, P2,.

Ｌレベルテストモードでの出力抵抗検査は、低電圧測定手段３により実行される。このモードでは、高電圧測定手段４を各出力ピンＰ１，Ｐ２，…Ｐｎ−１，Ｐｎに接続するマルチプレクサ５の接点Ｓ１，Ｓ２，…Ｓｎ−１，Ｓｎが、テスタ制御手段２からの切り換え指令で全てオフに制御され、高電圧測定手段４が切り離されている。   The output resistance test in the L level test mode is executed by the low voltage measuring means 3. In this mode, the contacts S1, S2,... Sn-1, Sn of the multiplexer 5 that connects the high voltage measuring means 4 to the output pins P1, P2,... Pn-1, Pn are switched from the tester control means 2. All are controlled to be off and the high voltage measuring means 4 is disconnected.

低電圧測定手段３は、ＤＵＴ１の各出力ピンＰ１，Ｐ２，…Ｐｎ−１，Ｐｎに所定の定電流を供給すると共に、各出力ピンに発生する電圧Ｖｉ１，Ｖｉ２，…Ｖｉｎ−１，Ｖｉｎを同時に測定する電流印加／低電圧測定器３１，３２，…３ｎ−１，３ｎで構成される。テスタ制御手段２は、各出力ピンの電圧測定値を取得する。   The low voltage measuring means 3 supplies a predetermined constant current to each output pin P1, P2,... Pn-1, Pn of the DUT 1 and supplies voltages Vi1, Vi2,. It is composed of current application / low voltage measuring devices 31, 32,. The tester control means 2 acquires the voltage measurement value of each output pin.

ＬレベルにおけるドライバＱ１，Ｑ２，…Ｑｎ−１，Ｑｎの電圧Ｖａ１，Ｖａ２，…Ｖａｎ−１，Ｖａｎは既知であるから、出力抵抗に定電流を供給したときの各出力ピンの電圧Ｖｉ１，Ｖｉ２，…Ｖｉｎ−１，Ｖｉｎを測定することで、出力抵抗Ｒａ１，Ｒａ２，…Ｒａｎ−１，Ｒａｎの値を算出することは容易である。   Since the voltages Va1, Va2,..., Van-1 and Van of the drivers Q1, Q2,..., Qn-1 and Qn at the L level are known, the voltages Vi1, Vi2 at the respective output pins when a constant current is supplied to the output resistance. ,..., Vin−1, Vin are measured to easily calculate the values of the output resistances Ra1, Ra2,.

Ｈレベルテストモードでの出力抵抗検査は、高電圧測定手段４により実行される。このモードでは、１台の電流印加／高電圧測定器４１を、テスタ制御手段２からの切り換え指令で順次オンとなるマルチプレクサ５の接点Ｓ１，Ｓ２，…Ｓｎ−１，Ｓｎを介して、ＤＵＴ１の各出力ピンＰ１，Ｐ２，…Ｐｎ−１，Ｐｎに順次接続し、各出力ピンに発生する電圧Ｖｉ１，Ｖｉ２，…Ｖｉｎ−１，Ｖｉｎを順次切り換えながら測定する。テスタ制御手段２は、各出力ピンの電圧測定値を順次取得する。   The output resistance test in the H level test mode is executed by the high voltage measuring means 4. In this mode, one current application / high voltage measuring device 41 is connected to the DUT 1 via the contacts S1, S2,... Sn-1, Sn of the multiplexer 5 which are sequentially turned on by a switching command from the tester control means 2. Each of the output pins P1, P2,... Pn-1, Pn is sequentially connected, and the voltages Vi1, Vi2,. The tester control means 2 acquires the voltage measurement value of each output pin sequentially.

ＨレベルにおけるドライバＱ１，Ｑ２，…Ｑｎ−１，Ｑｎの電圧Ｖａ１，Ｖａ２，…Ｖａｎ−１，Ｖａｎは既知であるから、出力抵抗に定電流を供給したときの各出力ピンの電圧Ｖｉ１，Ｖｉ２，…Ｖｉｎ−１，Ｖｉｎ測定することで、出力抵抗Ｒａ１，Ｒａ２，…Ｒａｎ−１，Ｒａｎの値を算出することは容易である。   Since the voltages Va1, Va2,..., Van-1, Van of the drivers Q1, Q2,... Qn-1, Qn at the H level are known, the voltages Vi1, Vi2 at the respective output pins when a constant current is supplied to the output resistance. ,..., Vin−1, Vin are measured to easily calculate the values of the output resistances Ra1, Ra2,.

高電圧測定手段４を、１台の電流印加／高電圧測定器４１とする理由は、５０〜１００Ｖの高電圧を扱うために高価であり、プラズマディスプレイドライバのように出力ピン数が極めて多いＤＵＴでは、ＨレベルテストモードでＬレベルテストモードのように同時測定を実行しようとした場合に、装置コストがきわめて大となり、実用上採用できないためである。   The reason why the high voltage measuring means 4 is a single current application / high voltage measuring instrument 41 is that it is expensive to handle a high voltage of 50 to 100 V, and has a very large number of output pins like a plasma display driver. This is because when the simultaneous measurement is executed in the H level test mode as in the L level test mode, the apparatus cost becomes extremely high and cannot be employed practically.

特開２００４−０８５２９０号公報JP 2004-085290 A

１個のＤＵＴの検査時間を問題とするとき、従来構成では、Ｌレベルテストモードでは全出力ピンの電圧測定は１回で済むが、Ｈレベルテストモードでは出力ピン数のｎ回を必要とし、検査時間のボトルネックとなっている。   When the inspection time of one DUT is a problem, in the conventional configuration, voltage measurement of all output pins is only required in the L level test mode, but in the H level test mode, n times of output pins are required. It is a bottleneck for inspection time.

図４は、装置コストのアップと検査時間のトレードオフで、高電圧測定手段４の電流印加／高電圧測定器を、４１…４ｍのｍ台構成とし、ｍ台によりｍ個の出力ピン電圧を同時測定する構成を示す。この場合では、Ｈレベルテストモードでの測定回数は、ｎ／ｍ回に減少するが、コストとの兼ね合いでｍの台数に制約がある。   FIG. 4 shows that the current application / high voltage measuring device of the high voltage measuring means 4 is composed of 41 units of 4 m, and m output pin voltages are generated by the m units with a trade-off between an increase in apparatus cost and an inspection time. A configuration for simultaneous measurement is shown. In this case, the number of measurements in the H level test mode is reduced to n / m times, but the number of m is limited in consideration of cost.

本発明は上述した問題点を解決するためになされたものであり、高価な電流印加／高電圧測定器を使用することなく、Ｌレベル及びＨレベルテストモードでの測定回数を１回として検査時間を短縮できるＩＣテスタの実現を目的としている。   The present invention has been made in order to solve the above-described problems. The inspection time is set to one measurement in the L level and H level test modes without using an expensive current application / high voltage measuring instrument. The purpose is to realize an IC tester that can shorten the time.

このような課題を達成するために、本発明は次の通りの構成になっている。
（１）複数の出力ピンを有する被試験デバイスの前記各出力ピンの出力抵抗値を検査するＩＣテスタにおいて、
前記各出力ピンに接続された基準抵抗と、
これらの基準抵抗を介して前記各出力ピンに所定の基準電圧を印加する基準電圧印加手段と、
前記各出力ピンに発生する電圧を測定する電圧測定手段と、
を備えたことを特徴とするＩＣテスタ。 In order to achieve such a subject, the present invention has the following configuration.
(1) In an IC tester for inspecting an output resistance value of each output pin of a device under test having a plurality of output pins,
A reference resistor connected to each output pin;
A reference voltage applying means for applying a predetermined reference voltage to each of the output pins via these reference resistors;
Voltage measuring means for measuring a voltage generated at each output pin;
IC tester characterized by comprising:

（２）前記各出力ピンと前記電圧測定手段との間に挿入された減衰手段を備えることを特徴とする（１）に記載のＩＣテスタ。 (2) The IC tester according to (1), further comprising attenuation means inserted between the output pins and the voltage measuring means.

（３）前記被試験デバイスは、２種類の出力レベルに対して各出力ピンの出力抵抗値が検査され、前記出力レベルの種類に対応して、前記基準電圧の値または前記減衰手段の減衰量の少なくともいずれかが変更されることを特徴とする（１）または（２）に記載のＩＣテスタ。 (3) In the device under test, the output resistance value of each output pin is inspected with respect to two types of output levels, and the value of the reference voltage or the amount of attenuation of the attenuation means corresponds to the type of the output level. The IC tester according to (1) or (2), wherein at least one of the above is changed.

（４）前記被試験デバイスは、プラズマディスプレイドライバであることを特徴とする
（１）乃至（３）のいずれかに記載のＩＣテスタ。 (4) The IC tester according to any one of (1) to (3), wherein the device under test is a plasma display driver.

本発明によれば、次のような効果を期待することできる。
（１）Ｌレベル及びＨレベルテストモードでの測定回数を各１回とすることができ、出力ピン数が多いＤＵＴの検査時間を大幅に短縮できる。 According to the present invention, the following effects can be expected.
(1) The number of measurements in the L-level and H-level test modes can be reduced to one each, and the DUT inspection time with a large number of output pins can be greatly shortened.

（２）高価な電流印加／高電圧測定器を使用する必要がないので、装置のコストダウンに貢献することができる。 (2) Since it is not necessary to use an expensive current application / high voltage measuring instrument, it is possible to contribute to cost reduction of the apparatus.

（３）Ｌレベルモード及びＨレベルモードでの各出力ピンの電圧測定では、電流供給機能を持たない単純な電圧測定器が使用できるため、装置のコストダウンに貢献することができる。 (3) In the voltage measurement of each output pin in the L level mode and the H level mode, a simple voltage measuring device having no current supply function can be used, which can contribute to the cost reduction of the device.

以下、本発明を図面により詳細に説明する。図１は、本発明を適用したＩＣテスタの一実施形態を示す機能ブロック図である。図３で説明した従来テスタと同一要素には同一符号を付して説明を省略する。以下、本発明の特徴部につき説明する。   The present invention will be described in detail below with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of an IC tester to which the present invention is applied. The same elements as those of the conventional tester described with reference to FIG. Hereinafter, the characteristic part of the present invention will be described.

この実施形態では、ＤＵＴ１は簡単のために出力ピン数は４個で説明する。基準抵抗Ｒｂ１，Ｒｂ２，Ｒｂ３，Ｒｂ４の各一端は、ＤＣテストモードでテスタ制御手段２からの指令で全ての接点Ｓ１，Ｓ２，Ｓ３，Ｓ４がオンに操作されるリレー手段６の各接点を介して各出力ピンＰ１，Ｐ２，Ｐ３，Ｐ４に接続されている。   In this embodiment, for the sake of simplicity, the DUT 1 will be described with four output pins. One end of each of the reference resistors Rb1, Rb2, Rb3, Rb4 is connected to each contact of the relay means 6 in which all the contacts S1, S2, S3, S4 are turned on by a command from the tester control means 2 in the DC test mode. Are connected to the output pins P1, P2, P3 and P4.

この接続形態では、ＤＵＴ１の各出力ピンの出力抵抗Ｒａ１，Ｒａ２，Ｒａ３，Ｒａ４と、各基準抵抗Ｒｂ１，Ｒｂ２，Ｒｂ３，Ｒｂ４とが夫々直列接続された状態である。基準抵抗Ｒｂ１，Ｒｂ２，Ｒｂ３，Ｒｂ４の各他端は、共通接続されて基準電圧印加手段７に接続されている。   In this connection form, the output resistors Ra1, Ra2, Ra3, Ra4 of the output pins of the DUT 1 and the reference resistors Rb1, Rb2, Rb3, Rb4 are respectively connected in series. The other ends of the reference resistors Rb1, Rb2, Rb3, Rb4 are connected in common and connected to the reference voltage applying means 7.

この接続により、共通の基準電圧印加手段７より各基準抵抗Ｒｂ１，Ｒｂ２，Ｒｂ３，Ｒｂ４を介して各出力ピンＰ１，Ｐ２，Ｐ３，Ｐ４に基準電圧Ｖｂが印加される。   With this connection, the reference voltage Vb is applied from the common reference voltage applying means 7 to the output pins P1, P2, P3, and P4 via the reference resistors Rb1, Rb2, Rb3, and Rb4.

このような接続において、各出力ピンＰ１，Ｐ２，Ｐ３，Ｐ４に発生する電圧Ｖｉ１，Ｖｉ２，Ｖｉ３，Ｖｉ４は、電圧測定手段８を構成する電圧測定器８１，８２，８３，８４により同時に測定される。   In such connection, the voltages Vi1, Vi2, Vi3, Vi4 generated at the output pins P1, P2, P3, P4 are simultaneously measured by the voltage measuring devices 81, 82, 83, 84 constituting the voltage measuring means 8. The

ＤＵＴ１は、Ｌレベルテストモード及びＨレベルテストモードの２種類の出力レベルに対して各出力ピンの出力抵抗値が検査されるが、本発明の特徴として、電圧測定手段８は両モードで共通に使用される。   In the DUT 1, the output resistance value of each output pin is inspected for two kinds of output levels of the L level test mode and the H level test mode. As a feature of the present invention, the voltage measuring means 8 is commonly used in both modes. used.

電圧測定器８１，８２，８３，８４の電圧測定スパンを、Ｌレベルテストモードの０〜１０Ｖに合わせた場合、Ｈレベルテストモードの５０〜１００Ｖに対して電圧測定スパンを合わせるために、各出力ピンＰ１，Ｐ２，Ｐ３，Ｐ４と電圧測定手段８との間に減衰手段９が挿入され、例えば１／１０の減衰量が設定される。   When the voltage measurement spans of the voltage measuring devices 81, 82, 83, and 84 are set to 0 to 10V in the L level test mode, each output is set to adjust the voltage measurement span to 50 to 100V in the H level test mode. Attenuating means 9 is inserted between the pins P1, P2, P3, P4 and the voltage measuring means 8, and for example, an attenuation of 1/10 is set.

減衰手段９は、電圧測定器８１，８２，８３，８４の夫々の入力に対して接続される減衰器９１，９２，９３，９４で構成される。これら減衰器の減衰量は、テストモードに応じてテスタ制御手段２から指令される。減衰量は、スルー（減衰量＝０）を含む。   The attenuating means 9 is composed of attenuators 91, 92, 93, 94 connected to the respective inputs of the voltage measuring devices 81, 82, 83, 84. The attenuation amount of these attenuators is commanded from the tester control means 2 according to the test mode. The attenuation amount includes through (attenuation amount = 0).

テスタ制御手段２は、テストモードに応じて基準電圧Ｖｂを変更する印加電圧指令を基準電圧印加手段７に出力する。テスタ制御手段２は、減衰手段９の減衰量の変更または基準電圧Ｖｂの変更の一方または両方を実行して、Ｈレベルテストモードでの電圧測定器８１，８２，８３，８４の入力電圧のスパンを適切に調整する。   The tester control means 2 outputs an applied voltage command for changing the reference voltage Vb according to the test mode to the reference voltage applying means 7. The tester control means 2 executes one or both of the change of the attenuation amount of the attenuation means 9 and the change of the reference voltage Vb, and the span of the input voltage of the voltage measuring devices 81, 82, 83, 84 in the H level test mode. Adjust appropriately.

図２は、出力ピンの電圧測定による出力抵抗計算の手法を説明する回路構成図である。以下、出力ピンＰ１に関する回路を代表として説明する。   FIG. 2 is a circuit configuration diagram illustrating a method of calculating an output resistance by measuring a voltage at an output pin. Hereinafter, a circuit related to the output pin P1 will be described as a representative.

ドライバＱ１の出力電圧Ｖａ１と基準電圧Ｖｂの電位差により出力抵抗Ｒａ１と基準抵抗Ｒｂ１の直列回路を流れる電流Ｉａ１は、
Ｉａ１＝（Ｖａ１−Ｖｂ）／（Ｒａ１＋Ｒｂ１） （１）
である。従って出力ピンＰ１に発生する基準電位からの電圧Ｖｉ１は、
Ｖｉ１＝（Ｖａ１−Ｖｂ）／（Ｒａ１＋Ｒｂ１）・Ｒｂ１＋Ｖｂ （２）
である。 The current Ia1 flowing through the series circuit of the output resistor Ra1 and the reference resistor Rb1 due to the potential difference between the output voltage Va1 of the driver Q1 and the reference voltage Vb is:
Ia1 = (Va1-Vb) / (Ra1 + Rb1) (1)
It is. Therefore, the voltage Vi1 from the reference potential generated at the output pin P1 is
Vi1 = (Va1-Vb) / (Ra1 + Rb1) .Rb1 + Vb (2)
It is.

ここで、Ｖａ１、Ｒｂ１、Ｖｂは既知であるから、測定値Ｖｉ１から（２）式に基づいて出力抵抗Ｒａ１を容易に算出することができる。   Here, since Va1, Rb1, and Vb are known, the output resistance Ra1 can be easily calculated based on the equation (2) from the measured value Vi1.

Ｈレベルテストモードでの計算例を示すと、ドライバＱ１の出力電圧Ｖａ１が８０Ｖ、基準電圧Ｖｂが７４Ｖとし、出力抵抗Ｒａ１の正常値が５００Ω、基準抵抗Ｒｂ１の抵抗値を１００Ωとすると、（２）式より出力ピンＰ１の電圧Ｖｉ１として７５Ｖが発生する。これを減衰器９１で１／１０の減衰させた電圧７．５Ｖが電圧測定器８１で測定される。   In the calculation example in the H level test mode, when the output voltage Va1 of the driver Q1 is 80V, the reference voltage Vb is 74V, the normal value of the output resistor Ra1 is 500Ω, and the resistance value of the reference resistor Rb1 is 100Ω, (2 ) Generates 75V as the voltage Vi1 of the output pin P1. A voltage 7.5V, which is attenuated by 1/10 of the attenuator 91, is measured by the voltage measuring device 81.

つまり、電圧測定器８１で７．５Ｖが測定されたときには、出力ピンＰ１の出力抵抗は５００Ωで正常と判定される。正常判定には所定の閾値が設定され、７．５Ｖを中心に適当な近似値までを正常と判定する。   That is, when 7.5 V is measured by the voltage measuring device 81, the output resistance of the output pin P1 is determined to be normal at 500Ω. A predetermined threshold value is set for normality determination, and it is determined that a proper approximate value centering around 7.5V is normal.

他の出力ピンＰ２，Ｐ３，Ｐ４での出力抵抗算出と判定についても同様である。また、Ｌレベルテストモードでの各出力ピンの出力抵抗算出と判定についても同様の手法が適用される。   The same applies to the calculation and determination of output resistance at the other output pins P2, P3, and P4. A similar method is applied to the calculation and determination of the output resistance of each output pin in the L level test mode.

実施形態では、ＨレベルテストモードとＬレベルテストモードに対応して電圧測定手段８の電圧測定スパンを同じにするために減衰手段９を設けた例を示したが、電圧測定手段８の電圧測定スパンが十分大きく、Ｈレベルテストモードでの出力ピン電圧も測定可能範囲であれば、減衰手段９を省く構成も可能である。   In the embodiment, the example in which the attenuation unit 9 is provided in order to make the voltage measurement span of the voltage measurement unit 8 the same corresponding to the H level test mode and the L level test mode is shown. If the span is sufficiently large and the output pin voltage in the H level test mode is also measurable, a configuration in which the attenuation means 9 is omitted is possible.

実施形態では、リレー手段６により複数の出力ピンを同時測定する手法を例示したが、マルチプレクサにより基準電圧印加手段７を順次切り換えて出力ピンに接続する測定手法をとることも可能である。この手法は、電圧測定手段８の資源が少ないときには有効である。   In the embodiment, the method of simultaneously measuring a plurality of output pins by the relay unit 6 is exemplified. However, it is also possible to take a measurement method in which the reference voltage applying unit 7 is sequentially switched by a multiplexer and connected to the output pin. This technique is effective when the voltage measuring means 8 has few resources.

本発明を適用したＩＣテスタの一実施形態を示す機能ブロック図である。It is a functional block diagram showing one embodiment of an IC tester to which the present invention is applied. 出力ピンの電圧測定による出力抵抗計算の手法を説明する回路構成図である。It is a circuit block diagram explaining the method of the output resistance calculation by the voltage measurement of an output pin. 特許文献１に従来例として開示されているＩＣテスタの構成例を示す機能ブロック図である。FIG. 11 is a functional block diagram showing a configuration example of an IC tester disclosed in Patent Document 1 as a conventional example. 電流印加／高電圧測定器を、複数台としたＩＣテスタの構成例を示す機能ブロック図である。It is a functional block diagram which shows the structural example of IC tester which used multiple electric current application / high voltage measuring devices.

符号の説明Explanation of symbols

１ 被試験デバイス
２ テスタ制御手段
６ リレー手段
７ 基準電圧印加手段
８ 電圧測定手段
８１〜８４ 電圧測定器
９ 減衰手段
９１〜９４ 減衰器
Ｐ１〜Ｐ４ 出力ピン
Ｒａ１〜Ｒａ４ 出力抵抗
Ｒｂ１〜Ｒｂ４ 基準抵抗
Ｖａ１〜Ｖａ４ ドライバ出力電圧
Ｖｉ１〜Ｖｉ４ 出力ピン電圧
Ｖｂ 基準電圧 DESCRIPTION OF SYMBOLS 1 Device under test 2 Tester control means 6 Relay means 7 Reference voltage application means 8 Voltage measurement means 81-84 Voltage measurement device 9 Attenuation means 91-94 Attenuator P1-P4 Output pin Ra1-Ra4 Output resistance Rb1-Rb4 Reference resistance Va1 ~ Va4 Driver output voltage Vi1 ~ Vi4 Output pin voltage Vb Reference voltage

Claims (4)

複数の出力ピンを有する被試験デバイスの前記各出力ピンの出力抵抗値を検査するＩＣテスタにおいて、
前記各出力ピンに接続された基準抵抗と、
これらの基準抵抗を介して前記各出力ピンに所定の基準電圧を印加する基準電圧印加手段と、
前記各出力ピンに発生する電圧を測定する電圧測定手段と、
を備えたことを特徴とするＩＣテスタ。 In an IC tester for inspecting an output resistance value of each output pin of a device under test having a plurality of output pins,
A reference resistor connected to each output pin;
A reference voltage applying means for applying a predetermined reference voltage to each of the output pins via these reference resistors;
Voltage measuring means for measuring a voltage generated at each output pin;
IC tester characterized by comprising: 前記各出力ピンと前記電圧測定手段との間に挿入された減衰手段を備えることを特徴とする請求項１に記載のＩＣテスタ。   2. The IC tester according to claim 1, further comprising attenuation means inserted between each output pin and the voltage measuring means. 前記被試験デバイスは、２種類の出力レベルに対して各出力ピンの出力抵抗値が検査され、前記出力レベルの種類に対応して、前記基準電圧の値または前記減衰手段の減衰量の少なくともいずれかが変更されることを特徴とする請求項１または２に記載のＩＣテスタ。   In the device under test, the output resistance value of each output pin is inspected with respect to two types of output levels, and at least one of the value of the reference voltage or the amount of attenuation of the attenuation means corresponds to the type of the output level. The IC tester according to claim 1, wherein the IC tester is changed. 前記被試験デバイスは、プラズマディスプレイドライバであることを特徴とする請求項１乃至３のいずれかに記載のＩＣテスタ。   4. The IC tester according to claim 1, wherein the device under test is a plasma display driver.
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JPH06213970A (en) * 1992-11-30 1994-08-05 Yokogawa Electric Corp Ic tester
JPH0829463A (en) * 1994-07-19 1996-02-02 Nippondenso Co Ltd Resistance value detecting device
JPH08226944A (en) * 1995-02-22 1996-09-03 Tohoku Electric Power Co Inc Multi-functional device for measuring ground resistance
JPH09196998A (en) * 1996-01-22 1997-07-31 Advantest Corp Measuring apparatus for output resistance of driver ic
JP2003283267A (en) * 2002-03-27 2003-10-03 Matsushita Electric Ind Co Ltd Output circuit for controlling gray-scale, its testing device, and method for testing the circuit
JP2004085290A (en) * 2002-08-26 2004-03-18 Yokogawa Electric Corp Ic tester
JP2005265756A (en) * 2004-03-22 2005-09-29 Yokogawa Electric Corp Ic tester

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108510923A (en) * 2018-03-30 2018-09-07 武汉精立电子技术有限公司 A kind of detection liquid crystal module ID pins open the device of short circuit

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