JPH09181715A - Frame synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent erroneous synchronization protection when a signal having a length of 1/n times (n = integer) of a selected frame length is received. SOLUTION: An FS comparator circuit 1 compares a reception signal Din with a frame SYNC pattern FS. A gate signal generating circuit 3 provides an output of a gate signal GA representing a position at which a frame SYNC is in existence upon the receipt of the signal Din with a frame length selected by a receiver. A frame synchronization protection circuit 4 conducts frame synchronization protection at a position represented by the signal GA. An FS pattern protection circuit 6 protects the frame SYNC pattern at other position than that at which the protection circuit 4 is going to protect the frame synchronization and provides an output of a reset pulse RS when number of protection times reaches a prescribed number of times. Since the protection circuit 4 is initialized thereby, erroneous section protection is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronizing circuit of a receiving apparatus used for digital broadcasting or communication for multiplexing and transmitting a plurality of types of data by forming transmission contents into frames.

[0002]

2. Description of the Related Art Conventionally, in digital broadcasting or communication in which transmission contents are formed into a frame and a plurality of types of data are multiplexed and transmitted, a frame sync pattern is included in the frame in order to synchronize the frame on a receiving apparatus side. Has been inserted. In addition, the bit length of one frame, that is, the frame length varies depending on programs and stations depending on the number of signals multiplexed in the frame, the transmission amount, the transmission rate, and the like. The frame synchronization circuit on the receiving device side detects data at a location where a frame sync is expected to be present in the received data based on the transmission rate (frame length) selected by the receiving device, and determines the data with the true frame sync pattern. Pattern comparison is performed, and synchronization protection is performed based on the comparison result.

[0003]

In such a conventional frame synchronization circuit, even if a signal having a length equal to an integral number of the frame length based on the transmission rate selected by the receiving apparatus is received, the synchronization is erroneously performed. There was a problem that protection was performed. This is because a frame sync exists in the same location in a received signal whose frame length is a fraction of an integer. Therefore, as described above, when data at a location where a frame sync is expected to exist is detected, the selected frame is selected. This is because synchronization protection is performed by erroneously recognizing the frame sync of a long signal. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a frame synchronization circuit that does not erroneously perform synchronization protection even when a signal having a frame length that is a fraction of the selected frame length is received. The purpose is to provide.

[0004]

SUMMARY OF THE INVENTION The present invention compares a received signal with a frame sync pattern and outputs the result as a comparison result signal, and a frame showing a frame length at a selected transmission rate. A frame length output circuit that outputs a long parameter, a gate signal generation circuit that outputs a gate signal indicating a position where a frame sync pattern exists when a signal of a length represented by this frame length parameter is received, and a comparison result signal and Frame synchronization protection circuit that performs frame synchronization protection at the position indicated by the gate signal based on the gate signal, and frame sync pattern protection at positions other than the position indicated by the gate signal based on the comparison result signal and gate signal. When the number of times has reached a predetermined number, the protection operation by the frame synchronization protection circuit is initialized. Those having a synchronization protection malfunction prevention circuit for outputting a reset pulse. in this way,
The synchronization protection malfunction prevention circuit detects whether or not a frame sync pattern exists in the same cycle at a position other than the position indicated by the gate signal, that is, other than the position where the frame synchronization protection circuit is trying to protect, and protects the frame sync pattern. By outputting a reset pulse when the number of times of protection reaches a predetermined number, the frame synchronization protection circuit is initialized.

The synchronization protection malfunction preventing circuit outputs a comparison result signal at a position other than the position indicated by the gate signal as a confirmation result signal, and protects the frame sync pattern based on the confirmation result signal. And a frame sync pattern protection circuit that outputs a reset pulse when the number of protections reaches a predetermined number.

[0006]

1 is a block diagram of a frame synchronization circuit showing a first embodiment of the present invention. In FIG. 1, an FS comparison circuit 1 compares a received signal (bit stream signal) Din received from a transmission path or the like (not shown) with a frame sync pattern FS, and compares the result with a comparison result signal CE (in the present embodiment, The signal is output as “H” when the signal Din and the pattern FS match, and “L” when they do not match. The frame length output circuit 2 outputs a frame length parameter FL indicating a frame length at the transmission rate based on the transmission rate TR selected in the receiving device including the frame synchronization circuit according to the present embodiment.

The gate signal generating circuit 3 receives the received signal Din
Receives the clock signal CLK synchronized with the clock signal CLK, counts the number of clocks, outputs a count value C, and indicates the position where the frame sync pattern exists when the signal Din having the length indicated by the frame length parameter FL is received. The gate signal GA is output. Frame synchronization protection circuit 4
Performs frame synchronization protection (backward protection) at the position indicated by the gate signal GA based on the comparison result signal CE and the gate signal GA, and determines that synchronization has been achieved when a certain number of protections is reached. Notification is made to another device (not shown) in the receiving device.

The FS pattern confirmation circuit 5 confirms the existence of a frame sync pattern at a position other than the position indicated by the gate signal GA based on the comparison result signal CE and the gate signal GA.
This is output as the confirmation result signal AE. The FS pattern protection circuit 6 performs the frame synchronization protection circuit 4 based on the confirmation result signal AE, the frame length parameter FL, and the count value C.
Performs the protection of the frame sync pattern at a position other than the position to be protected, and outputs a reset pulse RS for initializing the protection operation by the protection circuit 4 when the number of protections reaches a predetermined number.

Next, the operation of such a frame synchronization circuit will be described with reference to FIGS. FIG. 2 shows the reception signal Di.
FIG. 3 is a timing chart for explaining the operation of the frame synchronization circuit. Here, the received signal Din has a frame configuration as shown in FIG. 2A having a frame length of 1500 bytes, and a signal based on the transmission rate TR has a frame configuration as shown in FIG. It is assumed that Therefore, it means that the signal Din having a length of 1/2 of the selected frame length is received.

The number of backward protections of the frame synchronization protection circuit 4 and the FS pattern protection circuit 6 is assumed to be five and three, respectively. The FS comparison circuit 1 compares the received signal Din with the frame sync pattern FS and outputs a comparison result signal CE. Here, a signal D having a frame length of 1500 bytes
2 has been received, as shown in FIG.
The comparison result signal CE becomes “H” every 00 bytes.

Subsequently, the frame synchronization protection circuit 4 outputs the FS
The comparison result signal CE output from the comparison circuit 1 is the frame sync and the frame sync pattern F in the received signal Din.
The first match with S ("H" level) is shown in FIG.
The first coincidence pulse AP is output as shown in FIG. That is, at time t1, a frame sync exists at a predetermined position in the signal Din, and the comparison result signal CE indicates that the frame sync matches the frame sync pattern FS.
The first match pulse AP is output.

When the first match pulse AP is input, the gate signal generation circuit 3 is initialized and sets the gate signal GA to "L" level (non-active) as shown in FIG. The FS pattern confirmation circuit 5 validates the comparison result signal CE when the gate signal GA is "L" and outputs this as a confirmation result signal AE as shown in FIG. Thus, at time t2, the confirmation result signal AE becomes “H”.

The FS pattern protection circuit 6
"H" level confirmation result signal A from pattern confirmation circuit 5
When E is input, an internal protection counter (not shown) is counted up, and the number of times the frame sync pattern is protected is shown in FIG.
One time as shown in (g). When the gate signal generation circuit 3 initialized by the first match pulse AP receives the signal Din having the length represented by the frame length parameter FL,
An “H” level (active) gate signal GA is generated at a position where a frame sync pattern is expected to exist.

Here, since the selected frame length indicated by the frame length parameter FL is 3000 bytes, the gate signal GA becomes "H" at time t3 3000 bytes after time t1 when the frame sync is first confirmed. The frame synchronization protection circuit 4 validates the comparison result signal CE when the gate signal GA is “H”, and the comparison result signal CE matches the frame sync in the signal Din with the frame sync pattern FS (“H” level). , An internal protection counter (not shown) is counted up, and the number of times of frame synchronization protection is set to one as shown in FIG.

At time t4, similarly to time t2, the FS pattern confirmation circuit 5 outputs an "H" level confirmation result signal AE, and the number of frame sync pattern protections by the FS pattern protection circuit 6 is counted up. g)
Twice. At time t5, similarly to time t3, gate signal G of “H” level is output from gate signal generation circuit 3.
A is output, and the number of times of frame synchronization protection by the frame synchronization protection circuit 4 is counted up to two times as shown in FIG.

At time t6, as in times t2 and t4, F
The number of times of frame sync pattern protection by the S pattern protection circuit 6 is counted up to 3 times. Since the threshold of the number of times of protection in the FS pattern protection circuit 6 is set to 3 as described above, the FS pattern protection circuit 6
3G initializes the internal protection counter to zero the frame sync pattern protection count as shown in FIG. 3G, and outputs a reset pulse RS as shown in FIG.

When the reset pulse RS is input, the frame synchronization protection circuit 4 initializes an internal protection counter and sets the number of times of frame synchronization protection to 0 as shown in FIG. Then, when the reset pulse RS is input, the gate signal generation circuit 3 keeps the gate signal GA at “H” level.

Next, the frame synchronization protection circuit 4 operates at time t.
6, when the comparison result signal CE of “H” level is input at the next time t7, the reception signal Din
Recognizing that it is the first match between the middle frame sync and the frame sync pattern FS, it outputs the first match pulse AP as at time t1. With the first match pulse AP, the gate signal generation circuit 3 sets the gate signal GA to “L” level. Thus, the operation after time t1 is similarly repeated.

In the above frame synchronization circuit,
Assuming that the FS pattern protection circuit 6 does not output the reset pulse RS, the internal protection counter (not shown) of the frame synchronization protection circuit 4 continues to count up, and the number of protections eventually reaches 5, and the frame synchronization protection circuit 4 is synchronized. recognize. However, since the signal Din of 1500 bytes is received for the selected frame length of 3000 bytes, incorrect synchronization protection is performed.

Therefore, the threshold of the number of times of protection in the FS pattern protection circuit 6 (three times in this embodiment) is changed to the threshold of the number of times of protection in the frame synchronization protection circuit 4 (five times).
If it is set to be smaller than the frame synchronization protection circuit 4 before the protection count of the frame synchronization protection circuit 4 reaches the threshold value.
Can be initialized, so that erroneous synchronization protection can be prevented.

[0021]

According to the present invention, the synchronization protection malfunction prevention circuit protects the frame sync pattern at a position other than the position indicated by the gate signal, and when the number of protection reaches a predetermined number, the frame synchronization protection circuit is activated. Since the initialization is performed, it is possible to prevent the frame synchronization protection circuit from erroneously performing the synchronization protection when a signal having a frame length that is an integral fraction of the selected frame length is received.

Further, the synchronization protection malfunction prevention circuit is composed of a frame sync pattern confirmation circuit and a frame sync pattern protection circuit, so that a synchronization protection malfunction prevention circuit for preventing erroneous synchronization protection is realized with a simple configuration. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a frame configuration of a received signal.

FIG. 3 is a timing chart for explaining the operation of the frame synchronization circuit in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... FS comparison circuit, 2 ... Frame length output circuit, 3 ... Gate signal generation circuit, 4 ... Frame synchronization protection circuit, 5 ... FS
Pattern confirmation circuit, 6 ... FS pattern protection circuit.

Claims (2)

[Claims] 1. A frame synchronization circuit of a receiving apparatus for receiving a digital signal having a frame structure, which compares a received signal with a frame sync pattern, and outputs a result of the comparison as a comparison result signal. A frame length output circuit for outputting a frame length parameter indicating a frame length at a transmission rate, and a gate signal for outputting a gate signal indicating a position where a frame sync pattern exists when a signal having the length indicated by the frame length parameter is received A generation circuit, a frame synchronization protection circuit that performs frame synchronization protection at a position indicated by the gate signal based on the comparison result signal and the gate signal, and a frame synchronization protection circuit based on the comparison result signal and the gate signal, at a position other than the position indicated by the gate signal. The frame sync pattern is protected, and the number of protections reaches a predetermined number. When the frame synchronization circuit; and a synchronization protection malfunction prevention circuit for outputting a reset pulse for initializing the protection operation by the frame synchronization protection circuit. 2. The frame synchronization circuit according to claim 1, wherein the synchronization protection malfunction prevention circuit outputs a comparison result signal at a position other than the position indicated by the gate signal as a confirmation result signal. A frame sync pattern protection circuit that protects the frame sync pattern based on the confirmation result signal and outputs the reset pulse when the protection count reaches a predetermined count. circuit.