JP2619019B2 - Satellite broadcast receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a satellite broadcast receiving apparatus,
The signal is frequency-spread and scrambled by taking an exclusive OR with the pseudo-random data sequence, a signal transmitted periodically with a synchronization signal and a control signal is received, and after detecting the synchronization signal, the signal is subjected to frequency-spread descrambling. The present invention relates to a satellite broadcast receiving apparatus for reproducing.

(Prior Art) A satellite broadcasting system in which this kind of satellite broadcasting receiving apparatus is used. Specifically, in the high-fidelity audio satellite broadcasting system, in consideration of expandability, the transmission signal format is divided into a low-order multiplex part and a high-order multiplex part obtained by further multiplexing the low-order multiplex part. Therefore, a transmitting device as shown in FIG. 7 is used in this satellite broadcasting system. This transmitting device is composed of a low-order unit 1 that handles low-order multiplexed signals and a high-order unit 3 that handles high-order multiplexed signals. It is configured. The lower order part 1 is, for example, 12 or
A / D converter 5 for converting an analog signal such as audio to be transmitted into a digital signal, a range bit generator 7 for generating range bits,
It comprises an error correction addition section 9 for adding an error correction code and an interleave section 11. Higher order part 3 is lower order part 1
A multiplexing unit 13 for multiplexing low-order multiplexed signals from the respective channels, a frequency spreading scrambling unit 15 for frequency spreading and scrambling the multiplexed transmission signal, and a synchronization adding unit 17 for adding a synchronization signal. It is transmitted from the synchronization adding unit 17 as a bit stream.

As shown in FIG. 8, the format of each low-order multiplexed signal processed in each channel of the low-order unit 1 of the transmitting device is a 16-bit synchronization signal, a 16-bit control signal, and a 32-bit range bit. , 49x32 bit PCM audio signal, 13x
Each frame is composed of 2048 bits each composed of a 32-bit error correction code. Also, the audio signal is A mode and B
It has a mode and has expandability to incorporate digital data other than voice. The control signal is used for switching the contents of low-order multiplex frames such as A and B modes, stereo and monaural, and switching of multiple items is performed so as to sufficiently cope with broadcasting services other than audio. It has 16 bits to be able to.

The low-order multiplexed signal of 2048 bits per frame has a 32 × 64 bit matrix configuration as shown in FIG. 9. As described above, the A mode multiplexes four audio signals as shown in FIG. 9 (a). In the B mode, two audio signals are multiplexed as shown in FIG. 9 (b).

The format of the high-order multiplexed signal multiplexed in the high-order section 3 of the transmitting apparatus is 12 or 16 low-order multiplexed signals from each channel of the low-order section 1 as shown in FIG.
The data is multiplexed, interleaved, and transmitted as a bit stream as shown in FIG. Since the high-order multiplexed signal is repeatedly transmitted at a cycle of, for example, 1 kHz, the final bit trace is 24.567 when multiplexing 12 low-order multi-signals.
Mb / S, and 32.766 Mb / S when 16 signals are multiplexed.

The transmission data multiplexed in the multiplexing unit 13 of the above-described satellite broadcasting transmission device is subjected to an exclusive OR operation with a pseudo random data sequence as shown in FIG.
Frequency spread scrambling is performed.
FIG. 12 (b) shows an exclusive OR circuit for performing the frequency spread scrambling process. The pseudo-random data sequence for frequency spreading scrambling repeats the same pattern at one frame period with one period between the initialization timings at the end of the synchronization signal of the transmission data.

(Problems to be Solved by the Invention) In the above-described transmitting apparatus of the satellite broadcasting system, the transmission data that is frequency-spread and scrambled by taking an exclusive OR with a pseudo-random data sequence is as shown in FIG. A control code is provided after the synchronization signal. Since the control code is used to switch between the A mode and the B mode as described above, it is a signal that appears repeatedly without change when set once. In addition, when transmitting as a bit stream as described above, since each low-order multiplexed signal is interleaved one bit at a time, a signal of an arbitrary bit combination appears in the control signal, and this signal is an exclusive logical combination with the pseudo random data sequence. When the sum is obtained, data 0 represents the data of the pseudo random data sequence itself, and data 1 represents the inverted pseudo random data. Since only columns appear, from the frequency spread scrambled control code is a problem that the synchronization signals false having the same data pattern as the synchronization signal appears in the same frame period. On the other hand, the conventional satellite broadcast receiving apparatus does not have a function of determining the authenticity of the false synchronization signal, so that there is a problem that the false synchronization is performed using the false synchronization signal. is there.

The present invention has been made in view of the above, and an object of the present invention is to prevent a synchronization pull-in by a false synchronization signal generated from a control code or the like after a true synchronization signal, and to operate the satellite properly. An object of the present invention is to provide a broadcast receiving device.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, a satellite broadcast receiving apparatus of the present invention takes an exclusive OR with a pseudo random data sequence, performs frequency spread scrambling, and generates a synchronization signal. And receiving a signal transmitted periodically with a control signal, and after detecting the synchronization signal, a satellite broadcast receiving apparatus that reproduces the spread spectrum descrambled, after detecting the synchronization signal, at least A gist of the invention is to include a synchronization signal detection prohibiting unit that does not detect a synchronization signal for a predetermined period including the control signal.

(Operation) In the satellite broadcast receiving apparatus of the present invention, after detecting the synchronization signal, the synchronization signal is not detected for a predetermined period including the control signal.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a satellite broadcast receiving apparatus according to one embodiment of the present invention. The satellite broadcast receiving apparatus shown in FIG. 7 receives the multiplexed and frequency-spread scrambled digital transmission signal transmitted from the transmitting apparatus shown in FIG. 7 described above. Higher order part 21 for processing signals and higher order part 21
And a low-order unit 23 for processing the low-order multiplexed signal demultiplexed by the above. The high-order unit 21 performs a synchronization detection unit 25 for detecting a synchronization signal from the received transmission signal, and reproduces and protects a frame synchronization signal from the synchronization signal detected by the synchronization detection unit 25, and generates various timing pulses. Synchronization protection unit 27
And the same pseudo-random pulse train as that in the transmitting device is generated at the same timing based on the timing pulse from the synchronization protection unit 27, and an exclusive OR of the pseudo-random pulse train and the received signal is taken to obtain a frequency spread data. A frequency spread descrambling unit 29 for performing scrambling, and a demultiplexing unit for selectively extracting a low-order multiplexed signal from an output signal subjected to frequency spread descrambling in the frequency descramble unit 29 based on a timing pulse from the synchronization protection unit 27. 31
It is composed of Further, the low-order unit 23 includes a deinterleave unit 33 for deinterleaving the low-order multiplexed signal extracted by the demultiplexing unit 31 of the high-order unit 21, and an error correction unit for error-correcting the output signal of the deinterleave unit 33. 35, and an error control unit 37 for performing error control on an output signal of the error correction unit 35.
An interpolation unit 39 for interpolating the output signal of the error control unit 37;
A D / A converter 41 converts the digital output signal interpolated by the interpolator 39 into an analog audio signal and outputs the analog audio signal.

The synchronization detecting section 25 detects the synchronization signal from the frequency-spread scrambled reception signal from the transmitting apparatus as described above. In this case, as described above, the false detection by the control code generated after the synchronization signal is performed. A predetermined period including a portion where the control code is generated is masked so as not to detect the synchronization signal, and the synchronization signal is not detected during the predetermined period.

FIG. 2 is a timing chart for explaining this function. FIG. 5A shows a frequency-spread scrambled received signal from the transmitting apparatus. As shown in the figure, the received signal is repeated with a period between synchronization signals as one frame period, and a control code is generated after the synchronization signal. Therefore, this received signal is supplied to the synchronization signal detection unit 25,
When the synchronization signal is detected by the synchronization detection unit 25, the synchronization detection unit 25
As shown in FIG. 3B, in addition to generating a synchronization detection signal in response to a synchronization signal, the control signal is erroneously detected and a false synchronization detection signal is generated in a portion corresponding to the control code.

In order to prevent the generation of the false synchronization detection signal, when the synchronization detection section 25 generates the synchronization detection signal in response to the true synchronization signal, the synchronization detection section 25 responds to the synchronization detection signal as shown in FIG. As described above, a synchronization signal detection prohibition pulse is generated, thereby masking the control signal, thereby preventing the generation of a false synchronization signal by the control code. Note that the synchronization signal detection inhibition pulse is longer than a period including at least the control code.

FIG. 3 is a detailed circuit diagram of the synchronization detecting section 25, and FIG. 4 is a timing chart thereof.

The circuit of the synchronization detecting unit 25 shown in FIG. 3 has a 16-stage shift register 51 to which a frequency-spread scrambled received signal from the transmitting device is input, and a plurality of parallel output terminals of the shift register 51 are provided. Inverters 53 are connected as appropriate, and the outputs of these inverters 53 are supplied to a 16-input NAND circuit 55, which detects a synchronization signal. That is, in this embodiment, as an example, the pattern of the synchronization signal is “0001 0011 0101
The inverter 53 is connected to the parallel output terminal of the shift register 51 so as to detect “1110” and detect the synchronization signal of this pattern. Therefore, when the synchronization signal of this pattern is recognized as a reception signal by the shift register 51,
The inputs of the input NAND circuit 55 all become "1", whereby the output of the 16-input NAND circuit 55 changes to a low level to detect a synchronization signal. This low-level synchronization detection signal is output from the NAND circuit 55 via the three-state buffer 57, and at the same time, the clear terminal (▲
▼) to reset the counter. When the counter 59 is reset, it starts counting the clock signal CLK and generates a carry signal corresponding to the synchronization signal detection inhibition pulse from the carry output terminal CY. counter
59 counts the clock signal, and stops the generation of the carry signal when counting up for a predetermined period from 0 to 496. That is, the carry signal is output for a predetermined period after the counter 59 starts counting based on the synchronization detection signal. The carry signal is supplied to the three-state buffer 57.
Of the counter 59 via the inverter 61, thereby controlling the buffer 57 not to operate during the predetermined period. The output of buffer 57 is connected to pull-up resistor 63
Is connected.

FIG. 4 (a) shows the received signal subjected to the frequency spread scrambling. The received signal shows the synchronization signal and the control signal included therein. In some cases, the same pattern as the synchronization signal exists in the synchronization detection unit 25.
, A false synchronizing signal is also detected in the portion corresponding to the control code as shown in FIG. 4 (b), and a plurality of false synchronizing detection signals are generated from the 16-input NAND circuit 55. Accordingly, when the counter 59 is cleared by the synchronization detection signal detected for the correct synchronization signal, FIG.
, A carry signal for a predetermined period covering the control code is generated, and the carry signal is supplied to a prohibition gate of the buffer 57. Even if a false synchronization detection signal is output from the NAND circuit 55, Blocking the passage of
Only the true sync detection signal corresponding to the correct sync signal is
The output is as shown in FIG.

In the description of FIG. 3 and FIG.
Since the data format shown in the figure is premised, the period from the end of the correct synchronization signal to the beginning of the control code is up to 240 clocks in the counter 59, and the range in which the control code in which a false synchronization detection signal is easily generated exists in the correct synchronization signal. Of 24
The range is 256 clocks from 1 clock to 496 clocks later. Accordingly, the counter 59 starts counting from 0 and counts up from 496 to 496 as shown in FIG. 4D, during which time the carry signal is output and the operation of the buffer is inhibited.

FIG. 5 is a detailed circuit diagram of the synchronization protection section 27. The circuit of the synchronization protection unit 27 receives the low-level synchronization detection signal detected by the synchronization detection unit 25, and the synchronization detection signal is supplied to an input inversion type NAND circuit 75 on the one hand and the inverter 71 on the other hand. The AND circuit 73 supplies the logical product with the frame pulse supplied through the input inverting NAND circuit 77, and supplies the logical product to the synchronous / asynchronous determination circuit 81. Is determined. The synchronization determination signal from the synchronization / asynchronization determination circuit 81 is supplied to one input of the NAND circuit 77, and the logical AND with the frame pulse from the frame counter 79 is obtained. In such a configuration, when the synchronization detection signal from the synchronization detection unit 25 and the frame pulse from the frame counter 79 occur simultaneously, a synchronization pulse is generated from the NAND circuit 75,
Even if a frame pulse is generated, if a synchronous detection signal is not generated at this time, an asynchronous pulse is generated from the NAND circuit 73, and the synchronous pulse and the asynchronous pulse are supplied to the synchronous / asynchronous determination circuit 81. The synchronization pulse is cleared, the synchronization pulse clears the frame counter 79, and always outputs the correct frame pulse. This frame pulse is supplied to the timing generation circuit 83, and various timings are output from the timing generation circuit 83. It is supposed to be.

FIG. 6 is an explanatory diagram of the decision logic of the synchronous / asynchronous decision circuit. The number in the circle is a value obtained by subtracting the number of occurrences of the asynchronous pulse from the number of occurrences of the synchronization pulse, and 0
And saturates at 8. If the number in the circle is 2 or less, it is determined to be asynchronous, and if it is 3 or more, it is determined to be synchronous.

[Effects of the Invention] As described above, according to the present invention, after detecting a synchronization signal, the synchronization signal is not detected for a predetermined period including the control signal. Even if a false synchronizing signal having the same data pattern as that of the synchronizing signal is generated, the synchronizing signal for this purpose is not detected, so that erroneous synchronization pull-in can be properly prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a satellite broadcast receiving apparatus according to one embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the satellite broadcast receiving apparatus of FIG. 1, and FIG. FIG. 4 is a detailed circuit diagram of a synchronization detector used in the satellite broadcast receiver, FIG. 4 is a timing chart showing the operation of the synchronization detector of FIG. 3, and FIG. 5 is used in the satellite broadcast receiver of FIG. FIG. 6 is an explanatory diagram showing the operation of the synchronization / asynchronization determination circuit used in the synchronization protection section of FIG. 5, and FIG. 7 is used in the satellite broadcasting system. FIG. 8 is a block diagram showing the configuration of a transmitting apparatus, FIG. 8 is a diagram showing a low-order multiplex signal format used in the satellite broadcasting system, and FIG. 9 is a low-order multiplex matrix of the low-order multiplex signal format of FIG. Fig. 10 and Fig. 10 further multiplex the low-order multiplexed signal of Fig. 8. Shows a higher order multiplex signal format was, FIG. 11 shows the configuration procedure of the digital signal diagram, 12
FIGS. 1A and 1B are a timing chart and a simple circuit diagram for explaining frequency spread scrambling in a transmitting apparatus of a satellite broadcast system, respectively. 25 Synchronization detection unit 27 Synchronization protection unit 29 Frequency spread scrambling unit 31 Demultiplexing unit 51 Shift register 53 Inverter 57 Three-state buffer 59 Counter

Claims (1)

(57) [Claims] An exclusive OR with a pseudo-random data sequence is taken, frequency-spread and scrambled, a signal transmitted periodically with a synchronization signal and a control signal is received, and after detecting a synchronization signal, What is claimed is: 1. A satellite broadcast receiving apparatus for performing spread spectrum descrambling and reproducing, comprising: a synchronization signal detection prohibiting unit that does not detect a synchronization signal for at least a predetermined period including the control signal after detecting the synchronization signal. Satellite broadcast receiver.