JPH09181216A - Hybrid integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current level by forming via holes in contact with the lower layer contact part and a plurality of via holes in contact with the same on the Nth upper layer substrate and Nth and the first upper layer substrate. SOLUTION: A lower layer metallic substrate 30 is coated with an insulating resin 33 having bond properties such as epoxy resin or polyimide resin, etc., so as to stick conductive means such as a lower layer conductive paths 31, lower layer conductive land, etc., on the insulating resin 33 by hot pressing step. Furthermore, on said conductive means, an upper layer substrate 34 to be insulating substrate or a sheet is laminated and the in the Nth and the Nth and the first upper layer substrate 34, the contact parts to be the lower layer conductive paths 31 are brought into contact with one via hole 37 further with a plurality of via holes 38. Through these procedures, the lowering of the current level fed by respective via holes can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a multi-layered hybrid integrated circuit device having via holes.

[0002]

2. Description of the Related Art Generally, a multilayer substrate structure in which a plurality of substrates or sheets are laminated is disclosed in, for example, Japanese Patent Laid-Open No. 1-128493 and IMC 1988 Proceeding, Tokyo, May 25-27, "THE DEV
ELOPMENT OF THE MULTILAYERED IMST SUBSTRATE ". Particularly, in the latter document, it is disclosed that in connecting via holes, electroless Cu plating is first performed and then electrolytic plating is performed to realize via hole connection.

In FIG. 3, a flexible sheet 3 having a Cu foil 2 bonded to the entire surface thereof is fixed to a first layer substrate 1, and holes 4 and 5 are provided at portions corresponding to via holes. This is a diagram of a place where the Cu foil 2 including the holes is also plated, and then the Cu foil 2 including the Cu plating 6 is patterned with the resist 7. Although the description of this step will be given later, the outline of the hybrid integrated circuit device will be described first with reference to FIG.

That is, as can be seen from FIG. 3, the copper foil 2 is attached by hot pressing to the Al substrate 1 whose surface is anodized through the adhesive resin 8. This copper foil 2 is
The printed resistor, the chip capacitor, the chip resistor, and the bare chip semiconductor element are electrically connected to each other by etching into a predetermined pattern. Subsequently, the sheet 3 attached to the Al substrate 1 is, for example, a Cu attachment film with the adhesive 8, and the holes 4 and 5, for example, are punched with a drill, a punch, a laser, or the like before or after the attachment. ing.

Due to this drilling, the first layer wirings 9 and 10 provided on the substrate 1 are exposed in the holes, and the exposed first layer wirings, the side surfaces of the holes and the entire surface of the flexible sheet are attached. The Cu plating 6 is formed on the Cu foil. The Cu foil 2 integrated with the Cu plating 6 is patterned into a predetermined shape by a resist 7, and the flexible sheet 3
Second-layer wiring, lands, etc. are formed in this layer, and semiconductor elements such as printed resistors, chip capacitors, chip resistors, and bare chips are also electrically connected thereto. If necessary, the semiconductor chip and the wiring are electrically connected with a thin metal wire.

After that, the external leads are soldered and sealed if necessary. There are various sealing methods, and a transfer molding method, a dipping method in a resin solution, a sealing method using a metal can, a method of enclosing a substrate with a case material and injecting a resin into the method can be considered.

[0007]

The sizes of the holes 4 and 5 are determined by the current capacity, and the hole 4 naturally has a larger current capacity. However, referring back to FIG. 3, the resist 7 adopts the spin coating used in the semiconductor manufacturing method, and is adjusted to have a film thickness that allows photo-etching. When a resist is coated on the flexible sheet with this film thickness, the resist coated on the large hole 4 is recessed downward due to the flexibility of the resist itself. Further, the resist strength that is placed on a small hole such as the hole 5 and the resist strength that is placed on a large hole such as the hole 4 are weaker in the larger hole. That is, when the film is out of focus like the hole 5, the film has large elasticity and is strong, but when it hangs down like the hole 4 and forms a dull, the elasticity is weak and its strength is weak. When a forced circulation wet etching method such as a shower is adopted as the etching method, the shower pressure is as strong as 2 Kg / cm2, and the etchant of ferric chloride is 1.4 g / c.
Very heavy with a specific gravity of m3. That is, the impact of the etchant hitting the resist by the shower is very strong, and the film is broken, so that there is a problem that the hole 4 is penetrated and the conductive portion in the hole is etched. Further, there is a problem that the etchant accumulates in the recess of the resist, which further promotes this phenomenon.
Moreover, the phenomenon is recognized in other etchants to some extent.

Considering high-density mounting, it is preferable that the holes 4 and 5 are as small as possible. However, considering the current capacity, the size is inevitably large and the size of the substrate is large.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. First, a via hole is made to contact with a contact portion of an underlying wiring by one hole, and The problem is solved by preparing two kinds of contacts which are to be contacted by a plurality of holes for the contact part of the wiring of FIG. 3, and since the contact part originally corresponding to a large hole is composed of a plurality of holes, the process of FIG. In this case, even if the resist is applied, the resist does not dent downward and the etching solution does not accumulate. Also, the smaller the holes, the higher the resist strength and the ability to resist the etchant that collides with the resist.

Second, in the via hole shown in FIG. 3, the amount of current is determined by the area of the hole side surface and the plating thickness formed on the hole side surface. That is, the present application provides a hole in the contact portion of the second layer wiring so that a plurality of contact portions of the first layer wiring are exposed in an island shape, and the first layer wiring corresponding to the hole,
If a conductive material is provided on the side surface of the hole and on the second layer wiring corresponding to the periphery of the hole, the area of the side surface of the hole is increased as shown in FIG. The size of can be reduced. Even if the solder is embedded in the hole, Cu is as small as 1/10 of the solder,
After all, the current capacity depends on the area of the hole side surface.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Here, an explanation will be given with one insulating substrate (sheet-shaped or one having a slight thickness) attached on the Al substrate, but it may be further laminated. First, as shown in FIG. 1, the lower metal substrate 30
Conductive means such as the lower layer conductive path 31 and the lower layer conductive land are attached thereon. This lower layer substrate 30 is
An oxide film 32 shown by a dotted line is formed on the surface of the substrate 1. Although this oxide film is formed by anodizing both surfaces by anodic oxidation, it may be formed by thermal oxidation or may be formed by deposition. An insulating resin 33 having adhesiveness such as epoxy resin or polyimide resin is coated, and the conductive means 31 is attached by hot pressing. The conductive means is made of Cu, and is adhered on the entire surface and then etched and patterned with a solution of ferric chloride or the like. The conductive land is an area for fixing a lower chip semiconductor element or the like in the form of a bare chip. Here, since a heating element for a large signal is mounted, a heat sink such as Cu is fixed to the lower layer of the chip through solder or the like. It is integrated with the conductive path or has an island shape. Here, since the semiconductor element has a slight thickness, a second-layer insulating substrate or sheet 34 (which will be hereinafter collectively referred to as an insulating substrate including the sheet) to be described later has a region where the semiconductor element is fixed. It has been pulled out. (Here, if the semiconductor element is not fixed to the lower layer substrate but fixed to the insulating substrate of the second layer, it is not necessary to cut out.)
Although it may be an IC chip, an LSI chip, a power MOSFET chip, an IGBT chip, or the like, in the case of a bipolar power transistor, the base electrode and the emitter electrode on the surface are made of metal thin wires like the above-mentioned elements, and the wiring of the upper insulating substrate 34 is provided. Although a wire is bonded to a pad integrated with a part of 35, since the back surface of the chip is a collector, it is fixed to a conductive land (on the side of the metal substrate) integrated with a conductive path via solder or the like. Furthermore, lower layer components such as chip resistors and chip capacitors are connected to the conductive paths via solder.

Further, as will be described later, conductive lands and wirings of a semiconductor element which should originally be bonded to the upper substrate are provided in the region where the upper substrate 34 is bonded, and chip resistors, printing resistors, chip capacitors, etc. are conductive. It is mounted by being electrically fixed to the path 35. An upper layer semiconductor element such as a transistor is fixed to the upper layer conductive land via solder or the like.

Here, the electrical contact between the circuit of the metal substrate 30 and the upper substrate 34 is provided by the upper bonding pad provided on the periphery of the upper substrate 34, the position corresponding to this, and slightly more than the periphery of the upper substrate. It may be achieved by a lower layer bonding pad provided outside and a thin metal wire connecting them, or by wire bonding the conductive means exposed in the opening and the conductive means provided in the uppermost layer.

However, the wire bonding has a problem that a certain height is required to draw an arc. Also, it is common to achieve a single-layer circuit only with a metal substrate, but as the circuit becomes more complicated, crossover occurs, and this is avoided by jumping. However, as this jumping increases, Multilayer substrates and via holes are required.

The present invention is characterized by the structure of this via hole. In FIG. 1, the left via hole and the right via hole have different sizes. Left via hole 3
7 has one hole for the lower layer conductive path 31. Further, a plurality of right via holes 38 (here, nine) are provided for the lower layer conductive path 31. In FIG. 2, the alternate long and short dash line represents the lower layer conductive path 31, and the solid line represents the upper layer conductive path 3.
5 The wavy lines are the hole portions 37 and 38, and the solid line immediately adjacent to these wavy lines is the Cu plating layer 39. This hole may be opened by etching, mechanically, or even laser. Of the holes 37 and 38 that have been opened, 37 is used for a small current capacity and 38 is used for a large current capacity. Although it is shown as a rectangle here, it may be a circle.

Unlike the case where one hole 4 is used as shown in FIG. 3, since the side surface area of the hole can be increased as shown in FIGS. 1 and 2, the current capacity can be increased accordingly. Further, since the current can be increased and the size can be reduced, the packaging density can be improved. Also, as will be described later,
When the resist 7 as shown in FIG. 3 is attached to pattern the upper substrate, the resist formed by spin-on is divided into a plurality of holes 4 and the size of the holes 38 becomes smaller. As shown in FIG. 4, the resist is suppressed from being depressed like the resist located at No. 5, and the strength of the resist increases as the holes become smaller. Therefore, even if an etchant having a large specific gravity such as ferric chloride is etched by a shower, the resist is not destroyed and the etchant does not penetrate into the hole, so that the conductive material in the hole is etched. There is no.

Further, even if solder is formed in the hole to increase the current capacity and to protect the Cu plating layer, the resistance of Cu is about 1/10 of the solder, so that the resistance value is C.
Almost decided by u plating. Therefore, also in this case, the current capacity value can be increased by dividing the hole into a plurality of parts. Finally, the leads are fixed, and although not shown in the drawing, they are sealed with a metal or resin case or directly with resin. Further, a frame is provided around the substrate and resin is injected into the frame to seal the frame.

Next, a method of manufacturing the hybrid integrated circuit device will be briefly described. First, an Al metal substrate 30 whose surface is anodized is prepared, and a copper foil is attached to the entire surface. Since this Cu foil serves as the lower layer conductive path 31, its thickness is 10 to 10.
It is about 100 μm and hot pressed with an adhesive resin 33 such as polyimide or epoxy resin. Further, as the adhesive resin, in order to reduce the heat resistance, an adhesive having a low heat resistance mixed with Si filler or the like may be used.

Then, the copper foil is patterned. The metal substrate is dipped in an etching solution of ferric chloride, for example, and only the copper foil is patterned into a predetermined shape to form the lower layer conductive path 31. Further, here, as described in the description of the structure, the passive element and the active element are fixed via solder, silver paste or the like.

Subsequently, the insulating substrate 34 is bonded to the insulating resin 3.
Bonded via 6. (Here, the upper conductive path 35 of the insulating substrate 34 corresponding to the via hole may be removed in advance.) Further, there is a removal step by laser. Hole 37 in advance,
If the upper layer conductive path corresponding to 38 is removed, this conductive path serves as a mask and laser light can be irradiated. Due to the difference between the evaporation threshold energies of the metal and the polymer, the insulating film of the polymer material and the adhesive material of the polymer material corresponding to the inside of the holes 37 and 38 are evaporated by the ablation effect.

Subsequently, the hole portion is plated to electrically connect the lower layer conductive path 31 and the upper layer conductive path 35. Here, the entire surface may be plated, or the partial plating may be performed via a resist. Here, like the holes 37 and 38 in FIG. 4, since the inside of the holes is an insulating film, Cu is first deposited by electroless plating, and then Cu electrolytic plating is performed.

Then, as shown in FIG. 4, a resist 40 is formed on the entire surface.
Is formed by spin-on, developed into a predetermined pattern,
The Cu foil 35 exposed from the resist, or the Cu foil and the Cu plating film are etched with an etchant of ferric chloride. This step is a feature of the present invention,
As can be seen from FIG. 2, since the right contact 38 is divided into a plurality of pieces, even if the resist is coated by spin-on, the size of each hole becomes small, so that the contact 38 is formed substantially flat without any recess. be able to. Further, since the size of the hole is reduced, the strength of the resist stuck on the hole can be improved.

First, since the resist is flat, the amount of deformation of the resist due to the etchant is small. Therefore, even if etching is performed with an etchant having a large specific gravity such as ferric chloride as a main component, the resist is not deformed so much and its strength is large, so that the etchant may break and the etchant may enter the hole. There is no.

Finally, one of the wirings in the upper layer, a step of fixing a heat sink to a conductive land and a semiconductor element thereon, a step of mounting a passive element if necessary, and wire bonding for connecting a conductive element and a conductive path. There is a step and a step of soldering the leads. However, when fixing the semiconductor IC, the heat sink can be omitted. In consideration of moisture resistance and the like, a gel-like resin such as silicone or epoxy resin is injected into the case material, and the substrate is sealed to complete the product.

[0025]

As is clear from the above description, the first
In addition, by preparing a via hole that is to be contacted with one hole for the contact portion of the lower wiring and one that is contacted with a plurality of holes for the contact portion of the lower wiring, Since the contact portion corresponding to an essentially large hole is composed of a plurality of holes, even if the resist is applied in the step of FIG. 3, the resist does not dent downward and the etching solution does not accumulate. Also, the smaller the holes, the higher the resist strength and the ability to resist the etchant that collides with the resist. Therefore, since the resist is not broken and the etchant is immersed in the hole and the conductive material inside is not etched, it is possible to suppress the opening of the via hole and the decrease in the amount of current that the via hole can flow.

Second, in the via hole shown in FIG. 3, the amount of current is determined by the area of the side surface of the hole and the plating thickness formed on the side surface of the hole. That is, the present application provides a hole in the contact portion of the second layer wiring so that a plurality of contact portions of the first layer wiring are exposed in an island shape, and the first layer wiring corresponding to the hole,
If a conductive material is provided on the side surface of the hole and on the second layer wiring corresponding to the periphery of the hole, the area of the side surface of the hole is increased as shown in FIG. The size of can be reduced. Even if the solder is embedded in the hole, Cu is as small as 1/10 of the solder,
After all, the current capacity depends on the area of the side surface of the hole.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a hybrid integrated circuit device illustrating an embodiment of the present invention.

FIG. 2 is a plan view of the hybrid integrated circuit device in FIG.

FIG. 3 is a cross-sectional view illustrating a conventional manufacturing method.

FIG. 4 is a cross-sectional view illustrating a manufacturing method of the present invention.

Claims (2)

[Claims] 1. A hybrid integrated circuit device in which at least one upper-layer substrate having at least a surface insulating property is laminated on a substrate having at least a surface insulating property to form a multilayer substrate as a whole. And a N-th upper layer substrate and an N + 1-th upper layer substrate,
A via hole is formed to achieve electrical connection with the wiring provided in each, and the via hole is contacted with the contact portion of the lower wiring by one hole, and the contact of the lower wiring. A hybrid integrated circuit device characterized in that it has a plurality of holes that are in contact with the part. 2. A substrate having at least an insulating surface, a circuit element electrically connected to a first layer wiring provided on the substrate, and at least a surface attached to the substrate having an insulating property. An upper-layer substrate, a circuit element electrically connected to a second-layer wiring provided on the upper-layer substrate, a contact portion between the first-layer wiring and the second-layer wiring, A hole in which a plurality of island-shaped contact portions of the first layer wiring are exposed in the contact portion, the first layer wiring corresponding to the hole, the side surface of the hole, and the second layer wiring corresponding to the periphery of the hole And a conductive material provided in the hybrid integrated circuit device.