JP2957747B2 - Method of manufacturing circuit board with circuit component mounting terminals - Google Patents

Method of manufacturing circuit board with circuit component mounting terminals

Info

Publication number
JP2957747B2
JP2957747B2 JP3119312A JP11931291A JP2957747B2 JP 2957747 B2 JP2957747 B2 JP 2957747B2 JP 3119312 A JP3119312 A JP 3119312A JP 11931291 A JP11931291 A JP 11931291A JP 2957747 B2 JP2957747 B2 JP 2957747B2
Authority
JP
Japan
Prior art keywords
wiring pattern
hole
circuit
circuit wiring
insulating base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3119312A
Other languages
Japanese (ja)
Other versions
JPH04323894A (en
Inventor
雅一 稲葉
篤 宮川
健 岩山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON MEKUTORON KK
Original Assignee
NIPPON MEKUTORON KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON MEKUTORON KK filed Critical NIPPON MEKUTORON KK
Priority to JP3119312A priority Critical patent/JP2957747B2/en
Publication of JPH04323894A publication Critical patent/JPH04323894A/en
Application granted granted Critical
Publication of JP2957747B2 publication Critical patent/JP2957747B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、IC等の回路部品を搭
載する為の端子を備えた回路基板の製造法に関する。更
に具体的に云えば、本発明は、絶縁べ−ス材上に所要の
回路配線パタ−ンを形成し、この回路配線パタ−ンに対
して一端が電気的に接合すると共に他端が上記絶縁べ−
ス材を貫通して外部に突出する回路部品の為の確実な接
続用パッド又はバンプを備えるように形成可能な回路部
品搭載用端子を備えた回路基板の製造法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a circuit board having terminals for mounting circuit components such as ICs. More specifically, in the present invention, a required circuit wiring pattern is formed on an insulating base material, one end of which is electrically connected to the circuit wiring pattern, and the other end of which is formed as described above. Insulation base
The present invention relates to a method for manufacturing a circuit board having a circuit component mounting terminal that can be formed so as to have a reliable connection pad or bump for a circuit component that penetrates and protrudes to the outside.

【0002】[0002]

【従来の技術】この種のIC等の回路部品を搭載する為
の端子を備えた回路基板を製作する手法としては図3に
示す方法がある。この手法は図3の(1)の如く、先ず
可撓性又は硬質の絶縁べ−ス材21の一方面に所要の回
路配線パタ−ン22を形成すると共に、この絶縁べ−ス
材21の他方面にエキシマレ−ザ−光の遮光の為のメタ
ルマスク23を形成する。このメタルマスク23には、
回路配線パタ−ン22の位置する該当箇所に孔24を形
成するように処理し、また回路配線パタ−ン22の表面
には接着剤25を用いてポリイミドフィルム等からなる
保護フィルム26を貼着して表面保護層27を形成す
る。
2. Description of the Related Art As a method for manufacturing a circuit board having terminals for mounting circuit components such as an IC of this type, there is a method shown in FIG. In this method, as shown in FIG. 3A, first, a required circuit wiring pattern 22 is formed on one surface of a flexible or hard insulating base material 21, and the insulating base material 21 is formed. On the other surface, a metal mask 23 for shielding excimer laser light is formed. In this metal mask 23,
The circuit wiring pattern 22 is processed so as to form a hole 24 at a corresponding position, and a protective film 26 made of a polyimide film or the like is adhered to the surface of the circuit wiring pattern 22 using an adhesive 25. Thus, a surface protection layer 27 is formed.

【0003】次に、同図(2)の如く、メタルマスク2
3の側からエキシマレ−ザ−光Aを照射して回路配線パ
タ−ン22に達する導通用孔28を形成する。そこで、
同図(3)のように不要なメタルマスク23をエッチン
グ等の手段で除去したのち、同図(4)のとおり、上記
導通用孔28に対して一端が回路配線パタ−ン22に電
気的に接合すると共に他端が絶縁べ−ス材21から外部
に突出するような形状のIC等の回路部品の為の接続用
パッド又はバンプ29を半田等の充填処理で形成する。
[0003] Next, as shown in FIG.
The conductive hole 28 reaching the circuit wiring pattern 22 is formed by irradiating the excimer laser light A from the side 3. Therefore,
After the unnecessary metal mask 23 is removed by means such as etching as shown in FIG. 3 (3), one end of the conductive hole 28 is electrically connected to the circuit wiring pattern 22 as shown in FIG. 4 (4). And connection pads or bumps 29 for a circuit component such as an IC having such a shape that the other end protrudes outside from the insulating base material 21 are formed by filling processing such as solder.

【0004】[0004]

【発明が解決しようとする課題】上記手法に於いて、メ
タルマスク23を除去する工程では、回路配線パタ−ン
22の一部もエッチング液にさらされ損傷を受けて陥部
22Aを形成し、極端な場合には回路配線パタ−ン22
に貫通孔を形成する虞もある。その損傷を受ける度合い
は、回路配線パタ−ン22を形成する銅箔と絶縁べ−ス
材21に使用するポリイミドフィルムを接着する際の接
着性を向上させる為に通常施す銅箔裏面に対する処理層
の耐エッチング性のばらつきの他、メタルマスク23表
面の汚れ、メタルマスク23層の厚さのばらつきや導通
用孔28の内部に於けるエッチング液の更新度合のばら
つき等により影響を受ける。
In the above-described method, in the step of removing the metal mask 23, a part of the circuit wiring pattern 22 is also exposed to the etching solution and is damaged to form a recess 22A. In extreme cases, the circuit wiring pattern 22
There is also a risk that a through hole may be formed in the hole. The degree of the damage is determined by the processing layer applied to the back surface of the copper foil which is usually applied to improve the adhesion when the copper foil forming the circuit wiring pattern 22 and the polyimide film used for the insulating base material 21 are bonded. Of the metal mask 23, variations in the thickness of the metal mask 23 layer, variations in the degree of renewal of the etching solution inside the conductive holes 28, and the like.

【0005】導通用孔28に位置する回路配線パタ−ン
22に対する上記の如き損傷度合のばらつきは、接続用
パッド又はバンプ29の大きさや高さのばらつきの要因
となるので、これではIC等の回路部品を搭載する際の
接続不良の原因となって好ましくない。
The above-mentioned variation in the degree of damage to the circuit wiring pattern 22 located in the conduction hole 28 causes a variation in the size and height of the connection pads or bumps 29. It is not preferable because it causes connection failure when mounting circuit components.

【0006】[0006]

【課題を解決するための手段】本発明は、メタルマスク
を除去する為のエッチング処理工程の際に回路配線パタ
−ンに損傷を与えるような事態を確実に阻止し、これに
よりIC等の回路部品を搭載する際に接続不良を好適に
防止できるようにした精度の高い回路部品搭載用端子を
備えた回路基板の製造法を提供するものである。
SUMMARY OF THE INVENTION The present invention reliably prevents a situation in which a circuit wiring pattern is damaged during an etching process for removing a metal mask. An object of the present invention is to provide a method of manufacturing a circuit board having a high-precision circuit component mounting terminal capable of suitably preventing a connection failure when mounting a component.

【0007】その為に、本発明の回路部品搭載用端子を
備えた回路基板の製造法によれば、絶縁べ−ス材の一方
面に所要の回路配線パタ−ンを形成すると共にこの絶縁
べ−ス材の他方面にメタルマスクを形成し、このメタル
マスクには上記回路配線パタ−ンが位置する該当箇所に
孔を形成すると共にこの回路基板の外形に適合した形状
の分離用溝孔を形成し、次に上記メタルマスク側からエ
キシマレ−ザ−光を照射して上記孔の部位から上記回路
配線パタ−ンに達する導通用孔を形成すると共に上記分
離用溝孔の部分に位置する上記絶縁べ−ス材部分を貫通
させる分離用溝を形成し、次いで上記導通用孔の底部に
露出している上記回路配線パタ−ン部分に耐腐食性に富
む導電性金属層を被着形成し、更に該導電性金属層上に
電着法でレジスト層を形成し、次に上記メタルマスクを
エッチング除去し、また上記レジスト層を剥離処理した
後、上記導通用孔に対して一端が上記回路配線パタ−ン
に上記耐腐食性導電性金属層を介して電気的に接合する
と共に他端が上記絶縁べ−ス材の外部に突出する回路部
品の為の接続用パッド又はバンプを形成する各工程が採
用される。
Therefore, according to the method of manufacturing a circuit board provided with circuit component mounting terminals of the present invention, a required circuit wiring pattern is formed on one surface of an insulating base material and the insulating base is formed. A metal mask is formed on the other surface of the base material, a hole is formed in the metal mask at a corresponding location where the circuit wiring pattern is located, and a separation groove hole having a shape adapted to the outer shape of the circuit board is formed. And then irradiating excimer laser light from the metal mask side to form a conduction hole reaching the circuit wiring pattern from the hole portion, and forming the conduction hole located at the separation groove hole. A separating groove is formed to penetrate the insulating base material, and then a conductive metal layer having high corrosion resistance is formed on the circuit wiring pattern exposed at the bottom of the conductive hole. And a resist on the conductive metal layer by an electrodeposition method. After the metal mask is removed by etching and the resist layer is peeled off, one end of the conductive hole is connected to the circuit wiring pattern via the corrosion-resistant conductive metal layer. Each step of forming connection pads or bumps for circuit components that are electrically joined together and whose other end protrudes outside the insulating base material is employed.

【0008】ここで、回路配線パタ−ンの裏面を導電性
金属層で底上げすると、上記の電着レジスト層をその導
電性金属層の表面に選択的に被着形成する際、上記導通
用孔の内部に於ける電着レジスト液の更新を良好に行え
るようになるので、電着レジスト使用時の問題である被
着面に発生する気泡を好適に排除することができ、従っ
て気泡まきこみによるレジストピンホ−ルの発生を確実
に抑制できる。
Here, when the back surface of the circuit wiring pattern is raised with a conductive metal layer, when the electrodeposition resist layer is selectively formed on the surface of the conductive metal layer, the conductive hole is formed. Because the electrodeposition resist liquid inside the inside of the electrodeposition renewal can be satisfactorily performed, air bubbles generated on the surface to be adhered, which is a problem at the time of using the electrodeposition resist, can be suitably removed, and therefore, the resist caused by air bubble entrapment can be removed. The occurrence of pinholes can be reliably suppressed.

【0009】[0009]

【実施例】以下、図示の実施例を参照しながら本発明を
更に詳述する。図1は本発明の一実施例に従って製作さ
れる回路部品搭載用端子を備えた回路基板の要部を概念
的に示す拡大断面構成図であり、可撓性又は硬質の絶縁
べ−ス材1の一方面の所要位置にはその裏面の該当箇所
が耐腐食性の導電性金属層6で被覆された回路配線パタ
−ン2が形成されている。そして、絶縁べ−ス材1には
回路配線パタ−ン2の位置する該当箇所に該絶縁べ−ス
材1の上面から導電性金属層6に達する導通用孔10が
形成されており、この導通用孔10には一端が回路配線
パタ−ン2に上記導電性金属層6を介して電気的に接合
すると共に他端が絶縁べ−ス材1の外部に突出するIC
等の回路部品の為の接続用パッド又はバンプ11を形成
するように構成している。また、回路配線パタ−ン2の
表面側には接着剤7によりポリイミドフィルム等の保護
フィルム8が貼着されて表面保護層9を構成している。
この表面保護層9は、上記の如きフィルム部材に限ら
ず、ワニス状ポリイミド樹脂や絶縁性カバ−コ−トイン
ク等を印刷塗布して形成することも可能である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in further detail with reference to the illustrated embodiments. FIG. 1 is an enlarged cross-sectional view conceptually showing a main part of a circuit board provided with circuit component mounting terminals manufactured according to an embodiment of the present invention. A circuit wiring pattern 2 is formed at a required position on one side of the substrate, the pertinent portion of the back side being covered with a conductive metal layer 6 having corrosion resistance. A conductive hole 10 is formed in the insulating base material 1 at a corresponding position where the circuit wiring pattern 2 is located and reaches the conductive metal layer 6 from the upper surface of the insulating base material 1. One end of the conduction hole 10 is electrically connected to the circuit wiring pattern 2 via the conductive metal layer 6 and the other end projects outside the insulating base material 1.
It is configured to form connection pads or bumps 11 for circuit components such as. A protective film 8 such as a polyimide film is adhered to the surface side of the circuit wiring pattern 2 with an adhesive 7 to form a surface protective layer 9.
The surface protective layer 9 is not limited to the film member as described above, and may be formed by printing and applying a varnish-like polyimide resin, an insulating cover coat ink, or the like.

【0010】図2の(1)から(4)はその為の製造工
程図を示すものであって、先ず同図(1)の如く、例え
ば接着剤のあるもの又は無接着剤型の可撓性又は硬質の
両面銅張積層板等の材料を用意し、これにフォトエッチ
ング処理を施して絶縁べ−ス材1の一方面に対して所要
の回路配線パタ−ン2を形成し、またその他方面にはメ
タルマスク3を形成する。このメタルマスク3は図のよ
うに回路配線パタ−ン2の位置する該当箇所に孔4を有
し且つ製品の外形に沿って形成した分離用溝孔5を備え
るようにエッチング形成されている。また、回路配線パ
タ−ン2の表面には接着剤7を用いてポリイミドフィル
ム等の保護フィルム8を貼着することによって表面保護
層9を形成してある。
FIGS. 2 (1) to 2 (4) show a manufacturing process diagram for this purpose. First, as shown in FIG. 2 (1), for example, an adhesive or non-adhesive type flexible member is used. A material such as a double-sided copper-clad laminate, which is hard or hard, is prepared and subjected to a photo-etching process to form a required circuit wiring pattern 2 on one surface of the insulating base material 1; A metal mask 3 is formed on the side. The metal mask 3 is formed by etching so as to have a hole 4 at a corresponding position where the circuit wiring pattern 2 is located as shown in the figure and to have a separation groove 5 formed along the outer shape of the product. A surface protective layer 9 is formed on the surface of the circuit wiring pattern 2 by attaching a protective film 8 such as a polyimide film using an adhesive 7.

【0011】そこで、同図(2)の如く、エキシマレ−
ザ−光Aをメタルマスク3の側から照射して後述のIC
等の回路部品の搭載用端子を形成するための導通用孔1
0と分離用溝5Aをアブレ−ション形成する。これによ
り、導通用孔10は回路配線パタ−ン2の一部を露出さ
せると共に、分離用溝5Aは絶縁べ−ス材1、接着剤8
及び保護フィルム8を貫通させることとなる。
Therefore, as shown in FIG.
The light A is irradiated from the side of the metal mask 3 to form an IC to be described later.
Holes 1 for forming mounting terminals for circuit components such as
Ablation is formed with the separation groove 5A. As a result, the conduction hole 10 exposes a part of the circuit wiring pattern 2, and the separation groove 5A includes the insulating base material 1, the adhesive 8
And the protective film 8 is penetrated.

【0012】次に、同図(3)のように、導通用孔10
の底部に露出する回路配線パタ−ン2の部分に耐腐食性
に富む金等の導電性金属層6をメッキ等の手段で形成
し、更にこの導電性金属層6の表面に電着法でレジスト
層12を形成する。
Next, as shown in FIG.
A conductive metal layer 6 such as gold, which is rich in corrosion resistance, is formed by plating or other means on the portion of the circuit wiring pattern 2 exposed at the bottom of the metal wiring pattern 2 and is further deposited on the surface of the conductive metal layer 6 by an electrodeposition method. A resist layer 12 is formed.

【0013】そこで、同図(4)の如く、不要となった
メタルマスク3をエッチング手段で除去し、また電着形
成されたレジスト層12を剥離する。次いで、導通用孔
10に対して半田等の充填処理を施すことにより、一端
が回路配線パタ−ン2に耐腐食性の導電性金属層6を介
して電気的に接合すると共に他端が絶縁べ−ス材1の外
部に突出するIC等の回路部品の為の接続用パッド又は
バンプ11を形成することが可能となる。
Then, as shown in FIG. 1D, the unnecessary metal mask 3 is removed by etching means, and the resist layer 12 formed by electrodeposition is peeled off. Next, by filling the conduction hole 10 with solder or the like, one end is electrically connected to the circuit wiring pattern 2 via the corrosion-resistant conductive metal layer 6 and the other end is insulated. It becomes possible to form connection pads or bumps 11 for circuit components such as ICs protruding outside the base material 1.

【0014】[0014]

【発明の効果】本発明に従った回路部品搭載用端子を備
えた回路基板の製造法によれば、回路配線パタ−ンの裏
面を耐腐食性の導電性金属層で底上げした状態で電着レ
ジストをその導電性金属層の表面に選択的に被着形成す
るので、導通用孔の内部に於ける電着レジスト液の更新
を良好に行えることから、電着レジスト使用時の特有な
問題である被着面に発生する気泡のまきこみによるレジ
ストピンホ−ルを好適に抑制でき、またメタルマスクを
エッチング除去する際に回路配線パタ−ンが損傷を受け
る虞がなく、これによって回路部品の為の接続用パッド
又はバンプを形成する為の導通用孔の深さのばらつきを
好適に抑制できる。
According to the method of manufacturing a circuit board provided with circuit component mounting terminals according to the present invention, electrodeposition is performed with the back surface of the circuit wiring pattern raised with a corrosion-resistant conductive metal layer. Since the resist is selectively formed on the surface of the conductive metal layer, the renewal of the electrodeposition resist solution inside the conductive holes can be performed satisfactorily. Resist pinholes caused by the incorporation of bubbles generated on a certain adherend surface can be suitably suppressed, and there is no possibility that the circuit wiring pattern will be damaged when the metal mask is removed by etching. Variations in the depth of conduction holes for forming connection pads or bumps can be suitably suppressed.

【0015】従って、IC等の回路部品との接続の際、
接続不良となる接続用パッド又はバンプに於ける大きさ
のばらつきや高さのばらつきを確実に解消できることと
なるので、接続信頼性の極めて高い回路部品搭載用端子
を備えた回路基板を提供することが可能である。
Therefore, when connecting to a circuit component such as an IC,
To provide a circuit board having circuit component mounting terminals with extremely high connection reliability, because it is possible to reliably eliminate the variation in size and height in connection pads or bumps that cause connection failure. Is possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例によって製作される回路部品
搭載用端子を備えた回路基板の概念的な要部拡大断面構
成図
FIG. 1 is a conceptual enlarged cross-sectional configuration view of a principal part of a circuit board having circuit component mounting terminals manufactured according to an embodiment of the present invention.

【図2】本発明の一実施例による回路部品搭載用端子を
備えた回路基板の製造工程図
FIG. 2 is a manufacturing process diagram of a circuit board provided with circuit component mounting terminals according to an embodiment of the present invention.

【図3】従来手法に従った回路部品搭載用端子を備えた
回路基板の製造工程図
FIG. 3 is a manufacturing process diagram of a circuit board provided with circuit component mounting terminals according to a conventional method.

【符号の説明】[Explanation of symbols]

1 絶縁べ−ス材 2 回路配線パタ−ン 3 メタルマスク 4 孔 5 分離用溝孔 5A 分離用溝 6 導電性金属層 7 接着剤 8 保護フィルム 9 表面保護層 10 導通用孔 11 接続用パッド又はバンプ 12 レジスト層 DESCRIPTION OF SYMBOLS 1 Insulation base material 2 Circuit wiring pattern 3 Metal mask 4 Hole 5 Separation groove 5A Separation groove 6 Conductive metal layer 7 Adhesive 8 Protective film 9 Surface protective layer 10 Conducting hole 11 Connection pad or Bump 12 resist layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−323893(JP,A) 特許2539287(JP,B2) (58)調査した分野(Int.Cl.6,DB名) H05K 3/40 H05K 3/24 H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-323893 (JP, A) Patent 2539287 (JP, B2) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 3/40 H05K 3/24 H01L 21/60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁べ−ス材の一方面に所要の回路配線
パタ−ンを形成すると共にこの絶縁べ−ス材の他方面に
メタルマスクを形成し、このメタルマスクには上記回路
配線パタ−ンが位置する該当箇所に孔を形成すると共に
この回路基板の外形に適合した形状の分離用溝孔を形成
し、次に上記メタルマスク側からエキシマレ−ザ−光を
照射して上記孔の部位から上記回路配線パタ−ンに達す
る導通用孔を形成すると共に上記分離用溝孔の部分に位
置する上記絶縁べ−ス材部分を貫通させる分離用溝を形
成し、次いで上記導通用孔の底部に露出している上記回
路配線パタ−ン部分に耐腐食性に富む導電性金属層を被
着形成し、更に該導電性金属層上に電着法でレジスト層
を形成し、次に上記メタルマスクをエッチング除去し、
また上記レジスト層を剥離処理した後、上記導通用孔に
対して一端が上記回路配線パタ−ンに上記耐腐食性導電
性金属層を介して電気的に接合すると共に他端が上記絶
縁べ−ス材の外部に突出する回路部品の為の接続用パッ
ド又はバンプを形成する各工程を含む回路部品搭載用端
子を備えた回路基板の製造法。
A required circuit wiring pattern is formed on one surface of an insulating base material, and a metal mask is formed on the other surface of the insulating base material. In addition, a hole is formed at a corresponding position where the pin is located, and a separating groove hole having a shape conforming to the outer shape of the circuit board is formed. Then, excimer laser light is irradiated from the metal mask side to form the hole. Forming a conduction hole reaching the circuit wiring pattern from the portion, forming a separation groove penetrating the insulating base material portion located in the separation groove hole portion, and then forming the conduction hole; A conductive metal layer having high corrosion resistance is formed on the circuit wiring pattern exposed at the bottom, and a resist layer is formed on the conductive metal layer by an electrodeposition method. Etch and remove metal mask
After the resist layer is peeled off, one end of the conductive hole is electrically connected to the circuit wiring pattern via the corrosion-resistant conductive metal layer and the other end is connected to the insulating base. A method of manufacturing a circuit board having circuit component mounting terminals including a step of forming connection pads or bumps for circuit components protruding out of a material.
JP3119312A 1991-04-23 1991-04-23 Method of manufacturing circuit board with circuit component mounting terminals Expired - Fee Related JP2957747B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3119312A JP2957747B2 (en) 1991-04-23 1991-04-23 Method of manufacturing circuit board with circuit component mounting terminals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3119312A JP2957747B2 (en) 1991-04-23 1991-04-23 Method of manufacturing circuit board with circuit component mounting terminals

Publications (2)

Publication Number Publication Date
JPH04323894A JPH04323894A (en) 1992-11-13
JP2957747B2 true JP2957747B2 (en) 1999-10-06

Family

ID=14758326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3119312A Expired - Fee Related JP2957747B2 (en) 1991-04-23 1991-04-23 Method of manufacturing circuit board with circuit component mounting terminals

Country Status (1)

Country Link
JP (1) JP2957747B2 (en)

Also Published As

Publication number Publication date
JPH04323894A (en) 1992-11-13

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