JPH0917798A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To enable a polycrystalline wiring layer to be protected against short- circuiting caused by itself and prevented from malfunctioning and deteriorating in quality by a method wherein a defective pattern generated between polycrystalline silicon wiring layers in a photolithography process are removed. CONSTITUTION: When a gate insulating film is formed under polycrystalline silicon wiring layers 12 and 13, an opening is previously provided on a resist film which serves as a mask corresponding to a region where the wiring layers 12 and 13 are close to each other. The gate insulating film is selectively etched using this resist film as a mask, whereby an opening 14b is provided on the gate insulating film corresponding to the opening of the resist film, so that a defective pattern 15 generated when the polycrystalline silicon wiring layers 12 and 13 are formed is removed together with the insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a thin film transistor (TFT) structure on a substrate and a method for manufacturing the same, and more particularly, to two or more polycrystalline silicon wiring layers forming a thin film transistor at positions close to each other. The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Recently, in a liquid crystal display device or the like, a thin film transistor in which a source and drain regions are formed in a polycrystalline silicon layer is used as a pixel transistor in order to achieve high integration.

[0003]

By the way, since this thin film transistor is required to have a high density especially in a liquid crystal display device, a large number of polycrystalline silicon wiring layers (including a gate electrode) are accompanied with the high density. In the meantime, pattern defects of polycrystalline silicon are likely to occur. FIG. 13 specifically shows this pattern defect. As is clear from this figure, a pattern defect portion 103 having a line spacing or more is generated between the two polycrystalline silicon wiring layers 101 and 102 formed on the quartz substrate 100.

The cause of the pattern defect portion 103 is considered to be dust generated in the photolithography process or the remaining resist after the photolithography process. In particular, regarding the resist residue, as shown in FIG. 14, during development, that is, by etching the polycrystalline silicon layer 105 using the resist film 104 as a mask (dry etching using CF ₄ and O ₂ gas) Silicon wiring layers 101, 1
When forming 02, for example, the polycrystalline silicon wiring layer 10
The resist peeling occurs on the resist film 104 on the second side, and the peeled portion 104a moves to the polycrystalline silicon wiring layer 101 side formed adjacently. As a result, a pattern defect portion 103 (see FIG. 3) having a line width greater than that of the polycrystalline silicon wiring layer remains between the polycrystalline silicon wiring layers 101 and 102. Therefore, in particular, in a portion where the line spacing between the polycrystalline silicon wiring layers 101 and 102 is smaller than the polycrystalline silicon wiring layer line width, a short circuit accident (short circuit) due to the polycrystalline silicon wiring layer itself frequently occurs. was there. When such a defect occurs, the current consumption of the drive circuit in the liquid crystal display device increases, which causes the voltage in the circuit to drop,
There are problems that malfunctions occur and the image quality is adversely affected.

The present invention has been made in view of the above problems, and its object is to easily remove a pattern defect generated between polycrystalline silicon wiring layers and to prevent a short circuit accident due to the polycrystalline silicon wiring layers themselves. Never happens,
It is an object of the present invention to provide a semiconductor device and its manufacturing method capable of preventing malfunction and deterioration of quality.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device having two or more polycrystalline silicon wiring layers forming a thin film transistor at positions close to each other on a substrate, wherein at least two adjacent polycrystals of a gate insulating film forming a thin film transistor are adjacent to each other. It is characterized in that the region between the silicon wiring layers is selectively removed and the pattern defect portion generated between the polycrystalline silicon wiring layers is removed.

Further, a method of manufacturing a semiconductor device according to the present invention
A method of manufacturing a semiconductor device having two or more polycrystalline silicon wiring layers forming a thin film transistor, which are located close to each other on a substrate, wherein a first multi-layer structure is provided on each of the source, drain and channel regions on the substrate. A step of forming a crystalline silicon layer, and after forming an insulating film to be a gate insulating film on the first polycrystalline silicon layer, a second polycrystalline silicon wiring layer to be two or more polycrystalline silicon wiring layers is formed on the insulating film. Forming a crystalline silicon layer, forming a first resist film having a wiring pattern including a gate electrode on the second polycrystalline silicon layer, and using the first resist film as a mask A step of selectively removing the crystalline silicon layer to form two or more polycrystalline silicon wiring layers; and a step of removing the first resist film, and then removing the polycrystalline silicon wiring layer and the insulating film. Forming a second resist film having a gate insulating film pattern and selectively removing the insulating film using the second resist film as a mask to form a gate insulating film; And selectively removing a region corresponding to two or more adjacent polycrystalline silicon wiring layers to remove the pattern defect portion generated between the polycrystalline silicon wiring layers.

Further, in the method for manufacturing a semiconductor device of the present invention, the second resist film is formed with the gate insulating film pattern at least in the opening pattern corresponding to the region between two or more adjacent polycrystalline silicon wiring layers adjacent to each other. To form
By selectively removing the insulating film by using the second resist film as a mask, the gate insulating film is formed, and at the same time, the pattern defect portion generated between the polycrystalline silicon wiring layers is removed. The opening pattern provided in the second resist film may be provided in a region where the line spacing between the polycrystalline silicon wiring layers is smaller than the line width of each polycrystalline silicon wiring layer.

[0009]

In the semiconductor device of the present invention, at least the region between two or more adjacent polycrystalline silicon wiring layers of the gate insulating film forming the thin film transistor is selectively removed, and the polycrystalline silicon wiring layer above the polycrystalline silicon wiring layer is selectively removed. Since the pattern defect portion generated at 1 is removed, there is no short circuit accident between the polycrystalline silicon wiring layers.

Further, in the method of manufacturing a semiconductor device of the present invention, after forming two or more polycrystalline silicon wiring layers, a region of the gate insulating film corresponding to an adjacent polycrystalline silicon wiring layer is selectively removed. Therefore, the pattern defect portion generated between the polycrystalline silicon wiring layers is removed. In particular, the second
When a gate insulating film pattern and an opening pattern corresponding to a region between two or more adjacent polycrystalline silicon wiring layers are formed in the resist film of, the insulating film is formed using the second resist film as a mask. When selectively removed, the gate insulating film is formed, and at the same time, the pattern defect portion generated between the polycrystalline silicon wiring layers is removed.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Prior to the description of the embodiments, the basic principle of the present invention will be described with reference to FIG. That is, in the present invention, a thin film transistor is formed on a substrate, for example, a quartz substrate (transparent insulating substrate) 11 at positions close to each other.
After forming the above polycrystalline silicon wiring layers 12 and 13,
The pattern of the gate insulating film is formed by selectively removing (etching) the insulating film previously formed under the polycrystalline silicon wiring layers 12 and 13. At this time, the gate film is formed on the resist film serving as a mask. Along with the insulating film pattern, an opening is formed corresponding to the adjacent region between the polycrystalline silicon wiring layers 12 and 13, and the insulating film is selectively etched by using this resist film as a mask to form the insulating film opening 14a. Form. As a result, in the present invention, the pattern defect portion 15 generated at the time of forming the polycrystalline silicon wiring layers 12 and 13 (photolithography step) can be removed at the same time as forming (patterning) the gate insulating film.

FIG. 2 is a plan view showing an example in which the present invention is specifically applied to a pixel transistor (thin film transistor) of a liquid crystal display device. As described above, high density is required in the thin film transistor of the liquid crystal display device, and the polycrystalline pattern defect portion 15 is apt to occur in the proximity portion between the polycrystalline silicon wiring layers 12 and 13, which causes a short circuit accident. Cheap. In FIG. 2, two polycrystalline silicon wiring layers 12 and 13 are arranged in parallel, and one polycrystalline silicon wiring layer 12 (gate electrode 12a) and the other polycrystalline silicon wiring layer 13 are provided. The spaces are closest to each other, and the pattern defect portion 15 is likely to occur.

In this embodiment, the polycrystalline silicon wiring layer 1 is used.
A polycrystalline silicon layer 16 in which respective regions of a source, a drain, and a channel which form a thin film transistor are formed is provided under layers 2 and 13 with an insulating film (gate insulating film) interposed therebetween. The source region of the polycrystalline silicon layer 16 is provided with the polycrystalline silicon wiring layer 12 through the contact hole 17,
Aluminum (Al) wiring layer 1 formed on 13
8 is electrically connected to the drain region of the polycrystalline silicon layer 16, and the drain region of the polycrystalline silicon layer 16 is a transparent electrode (ITO (Indium Titanium Nitride) formed on the polycrystalline silicon wiring layers 12 and 13 through the contact hole 19. Electrically connected to the oxide) film 20).

With this structure, in this thin film transistor, when the gate insulating film under the polycrystalline silicon wiring layers 12 and 13 is patterned, a resist film serving as a mask is provided between the polycrystalline silicon wiring layers 12 and 13. An opening is formed corresponding to the adjacent region, and the insulating film is selectively etched using this resist film as a mask (that is, the insulating film opening 14b corresponding to the opening of the resist film is formed in the gate insulating film. By doing so, the pattern defect portion 15 generated at the time of forming the polycrystalline silicon wiring layers 12 and 13 is removed by etching together with the insulating film. Thereby, the polycrystalline silicon wiring layers 12, 13
There is no short circuit accident between them.

The distance between the insulating film opening 14b and the polycrystalline silicon wiring layer 12 is determined by the alignment accuracy of the photolithography apparatus and the etching accuracy. It is preferable that the gas for etching the insulating film and the gas for etching the polycrystalline silicon wiring layers 12 and 13 have the same main component. For example, both of them are CF ₄ / O.
_It is preferable to use a _two- system gas.

FIG. 3 shows polycrystalline silicon wiring layers 12 and 13.
FIG. 2 is a graph showing the occurrence rate of short-circuit accidents (short-circuit) between the method according to the present invention and the conventional method. As described above, according to the method of the present invention, it is found that the short-circuit occurrence rate is significantly reduced. FIG. 4 shows an equivalent circuit of the test apparatus used for this evaluation, in which two polycrystalline silicon wiring layers 12 and 13 arranged in parallel are respectively connected to a power source 24 with a positive electrode 21 and a negative electrode. It is connected to 22 and the current flowing between them is measured by an ammeter 23 to determine the occurrence of a short circuit.

Next, with reference to FIGS. 5 and 6, a more specific structure of the thin film transistor of the present invention and a manufacturing method thereof will be described. FIG. 5 shows a cross-sectional structure of the thin film transistor taken along the line AA of FIG.

The thin film transistor 30 is provided on a substrate such as a quartz substrate 31. A polycrystalline silicon layer (first polycrystalline silicon layer) 32 is provided on the quartz substrate 31, and in the polycrystalline silicon layer 32, n ⁺ regions 32a and 32b and n ⁻ regions 32c, which serve as sources and drains, are formed.
32d are formed respectively. Polycrystalline silicon layer 3
A channel region is formed between the two n ⁻ regions 32c and 32d.

On the channel region of the polycrystalline silicon layer 32, a polycrystalline silicon wiring layer 34 to be a gate electrode and wiring is provided via a gate insulating film 33. A polycrystalline silicon wiring layer 41 is provided close to the polycrystalline silicon wiring layer 34. Further, an interlayer insulating film 35 made of, for example, a PSG (phosphorus silicate glass) film is provided on the quartz substrate 31. A contact hole 36 is provided in the interlayer insulating film 35.
Aluminum (Al) wiring layer 37 is electrically connected to n ⁺ region 32a of polycrystalline silicon layer 32 via 6. An interlayer insulating film 38 made of a PSG film is further formed on the interlayer insulating film 35. A contact hole 39 is formed in the interlayer insulating film 38, and a transparent electrode (ITO) is formed on the inner wall surface of the contact hole 39 and its peripheral portion.
A membrane 40) is provided. Further, on the inter-layer insulating film 38, a silicon nitride film (as a hydrogen blocking layer) formed as a hydrogen barrier layer facing the polycrystalline silicon wiring layer (gate electrode) 34 by a plasma CVD (Chemical Vapor Deposition) method ( Si ₃ N ₄ ) 41 is formed.

In this thin film transistor 30, at least the region between the adjacent polycrystalline silicon wiring layers 34 and 41 of the gate insulating film 33 is selectively removed, and the pattern defect portion of the polycrystalline silicon wiring layer thereon is removed. As a result, the short circuit accident between the polycrystalline silicon wiring layers 34 and 41 is reduced as described above.

Next, a method of manufacturing the thin film transistor 30 having the above structure will be described in detail with reference to FIGS.

First, as shown in FIG. 7A, polycrystalline silicon is deposited on the quartz substrate 31 by, for example, the CVD method and patterned to form a polycrystalline silicon layer (first polycrystalline silicon layer) (film). Thickness; 400 nm) 32 is formed.

Next, as shown in FIG. 7B, an oxide film (SiO ₂ ) (film thickness; 1n) is formed on the polycrystalline silicon layer 32.
m) / nitride film (Si ₃ N ₄ ) (film thickness: 1000 nm) /
An insulating film 33A made of a laminated film of oxide films (SiO ₂ ) (thickness: 1000 nm) to be the gate insulating film 33 is formed. Here, the oxide film (SiO ₂ ) is formed by a thermal oxidation method, and the nitride film (Si ₃ N ₄ ) is formed by LPCVD (Low Pressure).
It is formed by the CVD method.

Next, as shown in FIG. 7C, a polycrystal silicon layer (second polycrystal silicon layer) 34A (film thickness: 40) which becomes the polycrystal silicon wiring layer 34 is formed on the insulating film 33A.
0 nm) is formed by the LPCVD method. Then, although not shown, for example, CVD is performed on the polycrystalline silicon layer 34A.
A PSG film is formed by the method and an annealing treatment is performed to introduce impurities (phosphorus) into the polycrystalline silicon layer 34A to reduce the resistance.

Next, as shown in FIG. 8A, a resist film 42 having a pattern corresponding to the polycrystalline silicon wiring layer 34 is formed on the polycrystalline silicon layer 34A. Subsequently, as shown in FIG. 8B, the polycrystalline silicon layer 34A is selectively etched using the resist film 42 as a mask to form a polycrystalline silicon wiring layer 34. At this time, although not shown, the polycrystalline silicon wiring layer 41 is simultaneously formed.
(See FIG. 6). As the etching method, for example, a dry etching method using CF ₄ and O ₂ as an etching gas is used. At this point, as described above, pattern defect portions are likely to occur between the polycrystalline silicon wiring layer 34 and the polycrystalline silicon wiring layer 41, and they are connected to each other and short-circuited.

Next, after removing the resist film 42, FIG.
As shown in (c), a resist film 43 serving as a mask for etching the gate insulating film is formed by coating so as to cover the polycrystalline silicon wiring layer 34. Here, although not shown in FIG. 8C, the polycrystalline silicon wiring layers 34 and 4 are formed on the resist film 43 together with the gate insulating film pattern as described above.
The opening is formed corresponding to the adjacent region between 1 (that is, the portion where the pattern defect portion is generated). Therefore, by selectively etching the insulating film 33A using the resist film 42 as a mask, the gate insulating film 33 is formed and at the same time the pattern defect portion is removed. As an etching method, for example, CF is used as an etching gas.
A dry etching method using ₄ and O ₂ is used.

The following is the same as the conventional process. That is, as shown in FIG. 9A, the resist film 43 is removed, and subsequently, as shown in FIG. 9B, with the polycrystalline silicon wiring layer 34 as a mask, ions of an n-type impurity such as arsenic ( As ⁺ ) is implanted to form n ⁻ regions 32c and 32d to be LDD (Low Doped Drain) regions. Subsequently, although not shown, a resist film is formed so as to cover the polycrystalline silicon wiring layer 34 and the gate insulating film 33, and an n-type impurity such as arsenic ion (As ⁺ ) is similarly implanted using this resist film as a mask, , The drain region n ⁺
Regions 32a and 32b are formed. Through the above steps, the thin film transistor 30 is formed.

Next, as shown in FIG. 10A, the thin film transistor 30 is entirely covered on the quartz substrate 31.
An interlayer insulating film (PSG film) 35 is formed by the CVD method. Subsequently, as shown in FIG. 10B, a contact hole 36 is formed in the interlayer insulating film 35 by wet etching using HF, and then an aluminum wiring layer (film thickness: 1000 nm) 37 is formed by an evaporation method. Aluminum (Al) wiring layer 37 is electrically connected to n ⁺ region 32a of polycrystalline silicon layer 32 through contact hole 36. Then, as shown in FIG.
On the inter-layer insulation film 35, an inter-layer insulation film (thickness: 1000 nm) 38 which is also a PSG film is formed by the CVD method.

Next, as shown in FIG. 11A, a silicon nitride film 41 as a hydrogen blocking layer is formed on the interlayer insulating film 38 by plasma CVD so as to face the polycrystalline silicon wiring layer (gate electrode) 34. To form. Subsequently, FIG.
As shown in (b), a contact hole 39 is formed in the interlayer insulating film 38 by wet etching using HF. Finally, as shown in FIG. 12, a transparent electrode (ITO film 40) is formed on the inner wall surface of the contact hole 39 and the peripheral portion thereof by the CVD method, and heat treatment (annealing) is performed, whereby the transparent electrode shown in FIG. The thin film transistor 30 can be manufactured.

As described above, according to the manufacturing method of this embodiment,
Adjacent polycrystalline silicon wiring layer 3 of gate insulating film 33
Since the region corresponding to the region between 4 and 41 can be selectively removed, the pattern defect portion between the polycrystalline silicon wiring layers 34 and 41 can be easily removed.

The present invention has been described with reference to the examples.
The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above-described embodiment, an example in which an insulating substrate (quartz substrate) is used as the substrate of the semiconductor device (thin film transistor) of the present invention and the invention is applied to a liquid crystal display device has been described, but the substrate may be a semiconductor substrate or a liquid crystal. The present invention can be applied not only to the display device but also to other devices.

[0033]

As described above, according to the semiconductor device of the present invention, at least the region between the adjacent and adjacent polycrystalline silicon wiring layers of the gate insulating film forming the thin film transistor is selectively removed. Therefore, the pattern defect part between the polycrystalline silicon wiring layers on it is removed,
There is an effect that a short circuit accident between the polycrystalline silicon wiring layers is eliminated, a malfunction such as a liquid crystal display is eliminated, and the quality is improved.

Further, according to the method of manufacturing a semiconductor device of the present invention, after forming two or more polycrystalline silicon wiring layers, the region of the gate insulating film corresponding to the adjacent polycrystalline silicon wiring layers is selectively removed. By doing so, the pattern defect portion generated between the polycrystalline silicon wiring layers can be easily removed, and the manufacturing yield can be improved.

In particular, when an opening pattern corresponding to a region between two or more polycrystalline silicon wiring layers adjacent to and adjacent to the gate insulating film pattern is formed on the second resist film, the gate insulating film is formed. At the same time, the pattern defect portion generated between the polycrystalline silicon wiring layers can be removed, and it is not necessary to add a new manufacturing process.

[Brief description of the drawings]

FIG. 1 is a perspective view for explaining the basic principle of the present invention.

FIG. 2 is a plan view showing an example in which the present invention is applied to a liquid crystal display device.

FIG. 3 is a diagram for explaining a defect occurrence rate by comparing the present invention with a conventional method.

FIG. 4 is a circuit configuration diagram for explaining a thin film transistor evaluation method of the present invention.

5 is a cross-sectional configuration diagram for explaining the details of the thin film transistor shown in FIG.

FIG. 6 is a plan configuration diagram for explaining details of the thin film transistor shown in FIG.

7A to 7C are process drawings for explaining a method of manufacturing the thin film transistor of FIG.

FIG. 8 is a cross-sectional view for explaining a process following the process in FIG.

FIG. 9 is a cross-sectional view for explaining a step following the step of FIG.

FIG. 10 is a cross-sectional view illustrating a step following the step of FIG.

FIG. 11 is a cross-sectional view for explaining a step following FIG.

FIG. 12 is a cross-sectional view for explaining a step following FIG.

FIG. 13 is a perspective view illustrating a problem of a conventional thin film transistor.

FIG. 14 is a perspective view illustrating a problem of a conventional thin film transistor.

[Explanation of symbols]

11 Quartz Substrate 12, 13, 34, 41 Polycrystalline Silicon Wiring Layer 14a, 14b Insulating Film Opening 15 Pattern Defect 16 Polycrystalline Silicon Layer 17, 19 Contact Hole 20 ITO Film 15 Pattern Defect 16 Polycrystalline Silicon Layer 30 Thin Film Transistor 31 quartz substrate 32 polycrystalline silicon layer (first polycrystalline silicon layer) 32a, 32b n ⁺ regions 32c, 32d n ⁻ region 33 gate insulating film 34, 41 polycrystalline silicon wiring layer 34A polycrystalline silicon layer (second polycrystalline silicon layer) Polycrystalline silicon layer) 35,38 Interlayer insulating film 36,39 Contact hole 37 Aluminum wiring layer 40 ITO film 41 Silicon nitride film

Claims (4)

[Claims] 1. A semiconductor device having two or more polycrystalline silicon wiring layers forming a thin film transistor at positions close to each other on a substrate, wherein at least the gate insulating films forming the thin film transistor are adjacent to each other in close proximity to each other. A semiconductor device, wherein a region between two or more polycrystalline silicon wiring layers is selectively removed, and a pattern defect portion generated between the polycrystalline silicon wiring layers is removed. 2. A method for manufacturing a semiconductor device having two or more polycrystalline silicon wiring layers forming a thin film transistor, which are located close to each other on a substrate, wherein a source region, a drain region and a channel region are formed on the substrate. Forming a first polycrystalline silicon layer, and forming an insulating film to be a gate insulating film on the first polycrystalline silicon layer, and then forming two or more polycrystalline silicon wiring layers on the insulating film. Forming a second polycrystalline silicon layer, and forming a first resist film having a wiring pattern including a gate electrode on the second polycrystalline silicon layer.
Selectively removing the second polycrystalline silicon layer by using the resist film as a mask to form two or more polycrystalline silicon wiring layers; and after removing the first resist film, the polycrystalline silicon layer is removed. A second resist film having a gate insulating film pattern is formed on the wiring layer and the insulating film, and the insulating film is selectively removed using the second resist film as a mask to form the gate insulating film. And a step of removing a pattern defect portion generated between the polycrystalline silicon wiring layers by selectively removing a region of the gate insulating film corresponding to two or more adjacent polycrystalline silicon wiring layers. A method for manufacturing a semiconductor device, comprising: 3. A gate insulating film pattern and an opening pattern corresponding to a region between at least two adjacent and adjacent polycrystalline silicon wiring layers are formed in the second resist film, and the second resist film is formed. 3. The semiconductor according to claim 2, wherein the gate insulating film is formed by selectively removing the insulating film using the film as a mask, and at the same time, the pattern defect portion generated between the polycrystalline silicon wiring layers is removed. Device manufacturing method. 4. The opening pattern provided in the second resist film is provided in a region where the line spacing between the polycrystalline silicon wiring layers is smaller than the line width of each polycrystalline silicon wiring layer. A method for manufacturing a semiconductor device as described above.