JP4245850B2 - Manufacturing method of electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic device manufacturing method, and more particularly to an electronic device manufacturing method including a step of patterning a non-processed layer using a resist pattern.
[0002]
[Prior art]
In a thin film transistor (TFT) substrate of a liquid crystal display device, a plurality of rows of gate bus lines, a plurality of rows or columns of storage capacitor bus lines, a plurality of rows of drain (or source) bus lines, and gate bus lines are usually provided on a glass substrate. A thin film transistor is formed at each intersection of drain (or source) bus lines, and a pixel electrode is connected to the source electrode of each thin film transistor. In some cases, peripheral circuits are integrated on the same glass substrate. Patterning of each layer is performed using a resist pattern.
[0003]
Defects in the gate bus line and drain bus line cause line defects, which are fatal defects in the liquid crystal display device. However, it is not easy to create a resist pattern without defects on a glass substrate having a large area.
[0004]
FIG. 6 shows a part of a method for manufacturing an electronic device according to the prior art. 6A to 6E are cross-sectional views of the substrate. FIGS. 6B1, C1, and D1 are planes corresponding to FIGS. 6B, 6 </ b> C, and 6 </ b> D. The figure is shown.
[0005]
As shown in FIG. 6A, a film 11 to be processed is deposited on the base substrate 10. The base substrate 10 is a glass substrate in the case of a liquid crystal display device, and is, for example, a silicon substrate in the case of a semiconductor integrated circuit device. Moreover, the board | substrate which formed circuit structure elements, such as a thin-film transistor and a MOS transistor, on these board | substrates may be sufficient. The processing target film 11 is a conductive film or an insulating film. In the following description, a case where the electronic device is a liquid crystal display device and the film to be processed 11 is a metal film will be described.
[0006]
As shown in FIG. 6B, a resist pattern 12 is formed on the metal film that is the film 11 to be processed. The resist pattern 12 is formed by applying a resist film, exposing, and developing.
[0007]
As shown in FIG. 6B1, it is assumed that the resist pattern 12 has a defective portion 12x in a part thereof.
[0008]
As shown in FIG. 6C, the processing target film 11 is etched using the resist pattern 12 as a mask. Etching is wet etching or dry etching. Since the defect pattern 12x exists in the resist pattern 12, the film to be processed 11 is also processed corresponding to the resist pattern 12 to generate the defect part 11x.
[0009]
FIG. 6C1 shows a state where the defect portion 11x is generated in the film 11 to be processed in accordance with the defect portion 12x of the resist pattern. In the region where the resist pattern 12 does not exist, the processing target film 11 is etched, and the surface of the base substrate 10 is exposed.
[0010]
As shown in FIG. 6D, the resist pattern is removed using ashing or stripping solution.
[0011]
As shown in FIG. 6D1, the processed film 11 from which the resist pattern has been removed has a defect portion 11x in a portion where the defect portion has occurred in the resist pattern. As shown in the figure, when the defect portion crosses the pattern, the disconnection of the wiring or the like occurs. Even when the defect portion does not cross the pattern, the pattern formed of the film to be processed is deformed, and a defect such as an increase in resistance occurs.
[0012]
As shown in FIG. 6E, after the etching process is completed, a protective film 15 is formed so as to cover the patterned film 11 to be processed. For example, the film 11 to be processed is a gate bus line, and the protective film 15 is a gate insulating film. When the gate bus line 11 is disconnected, pixels downstream from the disconnected portion become defective, and a line defect occurs.
[0013]
As described above, the defect of the resist pattern is directly connected to the defect of the pattern of the film to be processed, and the circuit function of the obtained electronic device is impaired.
[0014]
Conventionally, in order to increase the yield of a finished product, there has been proposed a technique for forming a redundant element for recovering a circuit function by subsequent processing even when a defect occurs in a wiring or the like, and repairing a defect part in the wiring or the like. In addition, in order to repair a defect portion such as a reticle after patterning of a Cr film for a reticle, a technique for filling a reticle pattern using photochemical vapor deposition (CVD) has also been proposed (Japanese Patent Laid-Open No. 9). -297387, JP-A-8-314120, etc.).
[0015]
Even if the reticle is perfect, if irregularities or the like exist on the base substrate, irregularities may also occur on the surface of the film to be processed, and pattern defects may occur due to halation or the like.
[0016]
[Problems to be solved by the invention]
In the etching process of the film to be processed using the resist pattern, it is difficult to ensure completeness of the resist pattern. If a defect portion exists in the resist pattern, the pattern of the film to be processed is also defective after the patterning of the film to be processed.
[0017]
An object of the present invention is to provide a method for preventing a defect from being exerted on a product even if a defect portion is generated in a resist pattern.
[0018]
Another object of the present invention is to provide a method of manufacturing an electronic device including a patterning process excellent in flexibility.
[0019]
Still another object of the present invention is to provide an electronic device manufacturing method capable of improving the yield in a patterning process of a film to be processed having a large area.
[0020]
[Means for Solving the Problems]
According to one aspect of the present invention, (a) a step of forming a film to be processed on a base substrate, (b) a step of forming a resist pattern on the target film, (c) Detecting a defect portion; (d) forming a photo-CVD film having a different etching characteristic from the film to be processed and the resist in the defect portion of the resist pattern; and (e) the resist pattern and And a step of etching the film to be processed using the photo-CVD film as a mask.
[0021]
By using photo-CVD, the defective portion of the resist pattern can be repaired. A metal film can be formed by optical CVD. A resist pattern defect can be repaired by selectively forming a film having etching characteristics different from those of the film to be processed by photo-CVD. By repairing the defect portion of the resist pattern, the film to be processed can be processed normally, and the occurrence of the defect after patterning can be prevented.
[0022]
In the step of removing the film used as the mask in the step (e), the photo-CVD film is an insulating film, and only the resist pattern is removed from the film used as the mask in the step (e). The present invention is characterized in that the photo-CVD film is left .
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. Note that the case where a conductive pattern such as a gate wiring is formed on a glass substrate will be described as an example, but the present invention is not limited to this.
[0024]
As shown in FIG. 1A, a wiring layer 11 for forming a gate bus line is formed on the surface of a glass substrate 10. The glass substrate 10 is configured by depositing a silicon oxide layer on the glass substrate 10 to prevent impurity diffusion. The wiring layer 11 is made of, for example, a Cr film, a Ti / Al laminated layer, a Mo / Al laminated layer, etc., and has a film thickness of about 150 nm and a line width of about 9 μm, for example. The wiring layer becomes a film to be processed.
[0025]
As shown in FIG. 1B, a resist pattern 12 is formed on the film 11 to be processed. However, it is assumed that a defective portion 12x is generated in the resist pattern 12.
[0026]
FIG. 1B1 is a plan view of the substrate. The resist pattern 12 shown on the left side in the drawing has a defect portion 12x and has a shape in which the upper and lower portions are divided. If the next patterning process is performed as it is, the film 11 to be processed is patterned into a shape equivalent to the resist pattern 12 having a defect.
[0027]
After the resist pattern 12 is formed, the resist pattern is inspected to detect a defective portion 12x of the resist pattern.
[0028]
FIG. 3A schematically shows a configuration of a laser CVD apparatus used for resist pattern repair. The laser CVD apparatus condenses the incident laser beam by the condenser lens 21 and deposits a CVD film 27 on the base substrate 26 by the CVD source gas G1 supplied from the CVD source gas chamber 22 through the nozzle. .
[0029]
A purge gas chamber 23 is disposed around the CVD source gas chamber 22 and ejects a purge gas G2 such as an inert gas. With this configuration, the CVD source gas is supplied to the CVD growth region, and the surroundings are separated from each other by the gas curtain of the purge gas G2.
[0030]
With such a laser CVD apparatus using a gas curtain, a CVD growth film having a minimum line width of about 5 μm can be formed in an air atmosphere. For example, the thickness of the CVD-grown W film is about 0.2 μm, and the resistivity is, for example, 50 μΩcm or less.
[0031]
A metal film such as Cr (CO) ₆ , Mo (CO) ₆ , W (CO) _6, or the like can be used as a source gas with an inert gas such as Ar as a source gas, and a metal film can be grown by CVD. As the excitation light, YAG laser light having a wavelength of 355 nm can be used.
[0032]
As shown in FIG. 1C, a laser CVD film 14 of a metal film is deposited on the defective portion 12x of the resist pattern using photo CVD, preferably laser CVD, in the defective portion 12x of the resist pattern. The laser CVD film 14 is a member that defines the processing shape of the film 11 to be processed together with the resist pattern 12.
[0033]
FIG. 1C1 is a plan view of the substrate. The resist pattern 12 shown on the left side in the figure has a defect at the center and is separated vertically, but a repair film 14 formed by laser CVD covers the defect and connects the separated upper and lower patterns 12. ing. A continuous wiring pattern is formed by forming the laser CVD film 14 in the defect portion of the wiring pattern 12 separated vertically.
[0034]
As shown in FIG. 1D, the film to be processed 11 is etched using the resist pattern 12 and the CVD film 14 as a mask.
[0035]
As shown in FIG. 1 (D1), since the repair film 14 connects the upper and lower resist patterns 12, the layer to be processed 11 is patterned in a continuous shape.
[0036]
As shown in FIG. 1E, the resist pattern 12 is removed after the etching process is completed. The processed film 11 remains in a continuous shape. The CVD repair film 14 remains on the layer 11 to be processed.
[0037]
As shown in FIG. 1F, a protective film 15 is formed so as to cover the film 11 to be processed and the repair film 14. Since the repair film 14 is an insulator, even if the repair film 14 remains on the film 11 to be processed, the electrical performance is not affected.
[0038]
In the above embodiment, the CVD repair film for resist pattern repair is left as it is, but it can also be removed.
[0039]
FIG. 2A shows a state in which a resist pattern 12 is formed on the film 11 to be processed and a CVD repair film 14 is formed in a defective portion of the resist pattern 12 as in FIG. Etching is performed in this state to pattern the film 11 to be processed.
[0040]
As shown in FIG. 2B, the resist pattern 12 is removed after etching. Since the resist pattern 12 and the metal CVD repair film 14 usually have different etching characteristics, the CVD repair film 14 remains.
[0041]
Thereafter, the CVD repair film 14 is removed.
[0042]
Note that either the resist pattern or the CVD repair film may be removed first.
[0043]
FIG. 2C shows a state where the CVD repair film 14 has been removed prior to the removal of the resist pattern 12. Thereafter, the resist pattern 12 is removed.
[0044]
As shown in FIG. 2D, a protective film 15 is formed so as to cover the pattern of the processing target film 11 from which the resist pattern and the CVD repair film have been removed.
[0045]
After forming a normal mask using the resist pattern repair as described above, the film to be processed can be processed normally.
[0046]
In addition, although the repair of the defect | deletion part of the area | region which should be electrically connected was demonstrated, the repair of the pattern between the parts which should be electrically insulated is performed similarly.
[0047]
FIGS. 3B and 3C show a repair method when the contact holes H1 and H2 formed in the insulating film 12 are continuous. FIG. 3C illustrates a cross-sectional structure of FIG. A wiring layer 16 is formed on the surface of the base substrate 10 having an insulating surface. The wiring layer 16 is electrically separated at the left and right portions. An insulating protective layer 17 is formed so as to cover the wiring layer 16. A resist pattern 12 is formed on the protective layer 17.
[0048]
The openings H1 and H2 of the resist pattern 12 are configured to be formed separately. However, a continuous hole H in which the contact holes H1 and H2 are connected is formed in the resist pattern. Therefore, a metal film 14 for pattern correction is deposited by laser CVD to separate the contact holes H1 and H2.
A metal repair film 14 is formed between the contact holes H1 and H2 by laser CVD to separate the connection holes H1 and H2.
[0049]
The insulating film 17 is etched using the repaired resist pattern (and repair film) as shown in FIGS. 3B and 3C as a mask. Contact holes penetrating the insulating film 17 are formed in the shape of the contact holes H1 and H2 separated by the repair film 14.
[0050]
In the case of FIGS. 3B and 3C, if the metal repair film 14 is left as it is, the wiring formed thereafter is short-circuited. The repair film 14 is also removed after the resist pattern 12 removal step, before the resist pattern removal, or simultaneously with the removal of the resist pattern 12.
[0051]
4A and 4B illustrate structural examples of thin film transistors. FIG. 4A shows a configuration example of a bottom gate TFT, and FIG. 4B shows a configuration example of a top gate TFT.
[0052]
4A and 4B are cross-sectional views illustrating structural examples of pixel TFTs included in the display portion B. FIG.
[0053]
FIG. 4A illustrates a structure example of a bottom-gate TFT.
[0054]
The bottom gate type TFT shown in FIG. 4A has a gate electrode G formed by forming a metal film such as Cr on the transparent substrate 10 and patterning it. On the gate electrode G, SiN serving as a gate insulating film, an insulating film 33 of SiO ₂ or the like is formed further thereon, SiN serving as a channel layer, an insulating film 33 of SiO ₂ or the like is formed, Further thereon, a channel polysilicon film 35 functioning as a channel layer is deposited. Over the regions on both sides of the gate electrode G of the channel polysilicon film 35, a polysilicon high-concentration layer 37 doped at a higher concentration than the channel polysilicon film 35 is formed. On the polysilicon high concentration layer 37, a source electrode S and a drain electrode D are deposited and patterned together with the polysilicon layer 37. The pixel TFT 25 thus formed is covered with an interlayer insulating film 41 formed of a nitride film, an oxide film or the like, and is insulated and protected from the surroundings. A contact hole is opened in the interlayer insulating film 41, and a pixel electrode 45 made of ITO is formed thereon. The pixel electrode 45 is connected to the source electrode S of the pixel TFT 25.
[0055]
The polysilicon film is obtained, for example, by depositing an amorphous silicon layer and crystallizing the amorphous silicon film. As the crystallization step, it is preferable to use a laser annealing crystallization technique with an excimer laser at a low temperature using a light source of XeCl (wavelength 308 nm) or KrF (wavelength 248 nm). If the laser annealing crystallization technique is used, for example, it is possible to crystallize only the TFT portion or the peripheral circuit portion constituting the signal line driver circuit that requires high-speed operation. In this case, the area scanned with the laser beam can be reduced.
[0056]
FIG. 4B shows a structural example of a top-gate TFT.
[0057]
In the top gate TFT 25 shown in FIG. 4B, a polysilicon film 35 that functions as a channel layer is formed on the transparent substrate 10, and an insulating film such as SiN or SiO _{2 that} functions as a gate insulating film is formed thereon. 33 is deposited and patterned. A metal film such as Cr is deposited on the insulating film 33 and patterned to form the gate electrode G.
[0058]
In the source region and the drain region on the polysilicon film 35, a polysilicon high concentration layer 37 doped with a higher concentration than the channel polysilicon film 35 is formed. On the polysilicon high concentration layer 37, the source electrode S, the drain electrode D, and the polysilicon layers 35 and 37 on which the source electrode S and the drain electrode D are formed can be patterned simultaneously.
[0059]
The pixel TFT 25 thus formed is covered with an interlayer insulating film 41 formed of a nitride film, an oxide film or the like, and is insulated and protected from the surroundings. A contact hole is opened in the interlayer insulating film 41, and a pixel electrode 45 made of ITO is formed thereon. The pixel electrode 45 is connected to the source electrode S of the pixel TFT 25.
A Ti / Al / Ti laminate may be used instead of Cr. A desired region of the channel polysilicon layer 35 may be doped with a high concentration, and the polysilicon high concentration layer 37 may be omitted. A peripheral circuit TFT can also be formed in a portion other than the pixel electrode.
[0060]
FIG. 5A shows an equivalent circuit diagram of a TFT substrate formed using such a TFT. A plurality of gate bus lines GB and drain bus lines DB are arranged in parallel, and TFTs 25 are connected to the respective intersections. The source electrode of the TFT 25 is connected to the pixel electrode 45. Further, the pixel electrode 45 has a region overlapping with the storage capacitor bus line CB, and forms a storage capacitor for each pixel.
[0061]
When the disconnection X1 occurs in the gate bus line GB, a pixel on the downstream side of the disconnection portion becomes a defect. Similarly, when a disconnection X2 occurs in the drain bus line DB, a pixel downstream from the disconnection portion X2 becomes a defect. By preventing such disconnection, it is possible to prevent occurrence of line defects and produce a liquid crystal display device.
[0062]
FIG. 5B schematically shows the structure of the completed liquid crystal display device. The first substrate 31 is a TFT substrate, and the TFT 25 is formed on the surface thereof. The pixel electrode 45 connected to the TFT 25 serves as an electrode for selectively displaying each pixel. The TFT 25 is covered with an insulating layer 41. An alignment film 51 is formed to cover the insulating layer 41 and the pixel electrode 45.
[0063]
A counter substrate 61 is disposed so as to face the TFT substrate 31. A color filter 66 is formed on the surface of the counter substrate 61, and a common electrode 65 is formed thereon. An alignment film 52 is formed on the common electrode 65. The alignment films 51 and 52 are subjected to an alignment process for controlling the alignment of liquid crystal molecules.
[0064]
Polarizing plates 62 and 63 are disposed on the outer surfaces of the opposing substrates 31 and 61. A liquid crystal layer 50 is filled in a space defined by the counter substrate. In this way, a liquid crystal display device is formed.
[0065]
The electronic device manufacturing method includes: (a) a step of forming a film to be processed on a base substrate; (b) a step of forming a resist pattern on the target film; and (c) the resist pattern. (D) a step of forming a photo-CVD film having etching characteristics different from those of the film to be processed and the resist on the defect portion of the resist pattern; and (e) the resist pattern. And a step of etching the film to be processed using the photo-CVD film as a mask.
[0066]
Moreover, the manufacturing method of an electronic device including the process of removing the said resist pattern and the said photo-CVD film | membrane after the said process (e) may be sufficient.
[0067]
Furthermore, the electronic device may be a circuit including a thin film transistor, the processing target film may be a conductor film or an insulating film, and the photo-CVD film may be a metal film manufacturing method.
[0068]
Note that although the case where a liquid crystal display device is formed has been described as an example, an electronic device other than the liquid crystal display device can be manufactured. For example, it is possible to form a system-in-package wiring board for forming a multilayer wiring on a silicon substrate and wiring between integrated circuit chips. It will be apparent to those skilled in the art that the above method can be applied to various other applications.
[0069]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0070]
【The invention's effect】
By repairing defects in the resist pattern, product yield can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view and a plan view for explaining a manufacturing process of a TFT substrate according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining a manufacturing process of a TFT substrate according to a reference example of the present invention.
FIG. 3 is a perspective view schematically showing a configuration of a gas curtain type laser CVD apparatus used in an embodiment of the present invention, and a plan view and a sectional view for explaining resist pattern repair according to a modification.
FIG. 4 is a cross-sectional view illustrating a configuration example of a TFT.
FIG. 5 is a transmission circuit diagram of a TFT substrate of a liquid crystal display device and a schematic cross-sectional view of the liquid crystal display device.
FIG. 6 is a cross-sectional view and a plan view showing a conventional patterning technique.
[Explanation of symbols]
10 Glass substrate 11 Processed film
11x defect 12 resist pattern
12x defect 14 CVD repair film 15 protective film 21 condenser lens 22 source gas chamber 23 purge gas chamber

Claims (3)

(A) forming a film to be processed on the base substrate;
(B) forming a resist pattern on the film to be processed;
(C) detecting a defect portion of the resist pattern;
(D) forming a photo-CVD film having different etching characteristics from the film to be processed and the resist in the defect portion of the resist pattern;
(E) etching the film to be processed using the resist pattern and the photo-CVD film as a mask;
(F) In the method of manufacturing an electronic device including the step of removing the film used as a mask in the step (e),
The photo-CVD film is an insulating film, and in the step (f), only the resist pattern is removed from the film used as a mask in the step (e), and the photo-CVD film is left. A method for manufacturing an electronic device.   The method of manufacturing an electronic device according to claim 1, wherein the step (d) is performed by laser CVD.   The method of manufacturing an electronic device according to claim 2, wherein the step (d) is performed by laser CVD using a gas curtain.

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