JPH0917780A - Formation of element separation film of semiconductor device - Google Patents
Formation of element separation film of semiconductor deviceInfo
- Publication number
- JPH0917780A JPH0917780A JP8147483A JP14748396A JPH0917780A JP H0917780 A JPH0917780 A JP H0917780A JP 8147483 A JP8147483 A JP 8147483A JP 14748396 A JP14748396 A JP 14748396A JP H0917780 A JPH0917780 A JP H0917780A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- semiconductor device
- element isolation
- oxide film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体装置の製
造工程において、素子と素子とを隔離する素子分離膜の
形成方法に関するもので、特にＮＨ3 アニーリングを利
用した素子分離膜の形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an element isolation film for isolating elements from each other in a semiconductor device manufacturing process, and more particularly to a method of forming an element isolation film using NH 3 annealing. Is.
【０００２】[0002]
【従来の技術】半導体装置の製造工程における素子間の
電気的絶縁のために、従来は酸化マスク層を使用して素
子分離領域を局部的に選択酸化させるＬＯＣＯＳ法が使
用されてきたが、素子の活性領域を減少させるバーズビ
ークの形成が問題となり、このバーズビークを減少させ
るためにＬＯＣＯＳ法を変形させたＯＳＥＬＯ（ｏｆｆ
−ｓｅｔ ＬＯＣＯＳ）法やＭＯＳＥＬＯ（ｍｏｄｉｆ
ｉｅｄ ＯＳＥＬＯ）法が最近使用され始めている。2. Description of the Related Art In order to electrically insulate elements in a semiconductor device manufacturing process, a LOCOS method has been used in which an element isolation region is locally selectively oxidized using an oxidation mask layer. Formation of bird's beaks that reduce the active region of the
-Set LOCOS method and MOSELO (modif
The ied OSELO method has recently begun to be used.
【０００３】ところで、そのＯＳＥＬＯ法のプロセス
は、ＬＯＣＯＳ工程中に素子分離膜のフィールド酸化膜
を形成するための熱酸化工程の前に（すなわち、パッド
酸化膜および酸化防止層がパターニングされて素子分離
領域となる半導体基板が露出された状態で）スペーサ用
の窒化膜を薄く蒸着し、その窒化膜をスペーサ蝕刻して
窒化膜スペーサを形成し、次いでシリコン基板を３０〜
７０ｎｍ（ナノメートル）程度蝕刻してトレンチを形成
した後、トレンチの底部分に熱酸化を実施するプロセス
であり、窒化膜スペーサの存在により酸化防止層の側壁
の底部に食い入るバーズビークを防止するものである。By the way, the process of the OSELO method is performed before the thermal oxidation process for forming the field oxide film of the device isolation film during the LOCOS process (that is, the pad oxide film and the antioxidation layer are patterned and the device isolation is performed). A nitride film for spacers is thinly vapor-deposited (with the semiconductor substrate to be the region exposed), and the nitride film is etched to form a nitride film spacer.
This is a process in which a trench is formed by etching about 70 nm (nanometers), and then thermal oxidation is performed on the bottom portion of the trench, and the presence of a nitride film spacer prevents bird's beaks that dig into the bottom portion of the sidewall of the antioxidant layer. is there.
【０００４】[0004]
【発明が解決しようとする課題】しかし、バーズビーク
を減少するためには、窒化膜スペーサの厚さを厚くしな
ければならず、一方これがあまりに厚過ぎると、フィー
ルド酸化膜が形成される空間がせまくなって、フィール
ド酸化膜の厚さが減少してしまい、素子間の隔離効果が
低下するし、だからといって窒化膜スペーサの厚さを薄
くすると、バーズビークの形成が大きくなる問題点があ
る。However, in order to reduce the bird's beak, it is necessary to increase the thickness of the nitride film spacer. On the other hand, if the spacer is too thick, the space for forming the field oxide film is narrowed. Then, the thickness of the field oxide film is reduced and the isolation effect between the elements is reduced. Therefore, if the thickness of the nitride film spacer is reduced, the bird's beak formation becomes large.
【０００５】したがって、この発明は、素子間の必要な
隔離効果を確保し、バーズビークを減少させる、半導体
装置の素子分離膜の形成方法を提供することを目的とす
る。Therefore, an object of the present invention is to provide a method for forming an element isolation film of a semiconductor device, which secures a necessary isolation effect between elements and reduces bird's beak.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、この発明は、半導体装置の素子分離膜の形成方法に
おいて、シリコン基板を提供する段階と、上記シリコン
基板上に酸化膜を形成する段階と、上記シリコン基板を
窒素含有ガスで熱処理することにより上記酸化膜に窒素
を注入する段階を含んでなることを特徴とする。In order to achieve the above object, the present invention provides a method for forming an element isolation film of a semiconductor device, the step of providing a silicon substrate, and forming an oxide film on the silicon substrate. And a step of injecting nitrogen into the oxide film by heat-treating the silicon substrate with a nitrogen-containing gas.
【０００７】さらに、半導体装置の素子分離膜の形成方
法において、シリコン基板を提供する段階と、上記シリ
コン基板上に酸化膜を形成する段階と、上記シリコン基
板を窒素含有ガスで熱処理することにより上記酸化膜に
窒素原子を注入する段階と、上記酸化膜上に窒化膜を形
成する段階と、上記窒化膜と酸化膜をパターニングして
上記シリコン基板の素子分離領域を露出させる段階と、
上記窒化膜及び酸化膜のパターン縁部の側壁に窒化膜ス
ペーサを形成した後に、シリコン基板のその部分をエチ
ングしてトレンチを形成する段階と、その露出されたシ
リコン基板を熱酸化させる段階を含んでなることを特徴
とする。Further, in the method of forming an element isolation film of a semiconductor device, the steps of providing a silicon substrate, forming an oxide film on the silicon substrate, and heat treating the silicon substrate with a nitrogen-containing gas are performed. Implanting nitrogen atoms into the oxide film, forming a nitride film on the oxide film, and patterning the nitride film and the oxide film to expose the element isolation region of the silicon substrate,
After forming the nitride film spacers on the sidewalls of the pattern edges of the nitride film and the oxide film, etching the portion of the silicon substrate to form a trench, and thermally oxidizing the exposed silicon substrate. It is characterized in that
【０００８】[0008]
【発明の作用】この発明では、パッド酸化膜のシリコン
基板との境界付近に窒素原子を蓄積させて、フィールド
酸化膜の形成時に酸素原子がパッド酸化膜に容易に拡散
して行かないようにしている。そのため、その部分にバ
ーズビークが形成されにくい。According to the present invention, nitrogen atoms are accumulated near the boundary between the pad oxide film and the silicon substrate to prevent oxygen atoms from easily diffusing into the pad oxide film when the field oxide film is formed. There is. Therefore, bird's beak is not easily formed in that portion.
【０００９】[0009]
【発明の実施の形態】以下、添付の図面を参照して、こ
の発明の一実施形態を詳細に説明する。図１〜図５は、
この発明の一実施形態による素子分離膜の形成工程の進
行順を示す半導体装置の断面図である。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. 1 to 5
FIG. 6 is a cross-sectional view of the semiconductor device showing the order of progress of the element isolation film forming process according to the embodiment of the present invention.
【００１０】まず、図１は、シリコン基板１を酸化させ
てパッド酸化膜２を５〜５０ｎｍ（ナノメートル）の厚
さに形成して、高温での安定化のためにＮ2 ガスとＮＨ
3 またはＮＯ2 ガスに長時間露出させるアニーリング工
程を行った状態の断面図で、パッド酸化膜２のシリコン
基板１との境界付近にＮＨ3 による小量の窒素原子の層
３が存在することになる。ここに、パッド酸化膜２は、
ストレス防止を目的とするものである。この場合のＮＨ
3 アニーリングの条件は、ＮＨ3 の濃度を全体ガスの５
０％以上、温度を８００〜１１００℃、圧力を１０〜１
００ｔｏｒｒ、時間を３０分〜２時間とする。First, in FIG. 1, the silicon substrate 1 is oxidized to form a pad oxide film 2 having a thickness of 5 to 50 nm (nanometers), and N 2 gas and NH 3 are used for stabilization at high temperature.
In cross-sectional view of a state performing the 3 or prolonged exposed to an annealing step to NO 2 gas, that is a layer 3 of a small amount of nitrogen atoms present by NH 3 in the vicinity of the boundary between the silicon substrate 1 of the pad oxide film 2 Become. Here, the pad oxide film 2 is
The purpose is to prevent stress. NH in this case
3 Annealing condition is that NH 3 concentration is 5% of total gas.
0% or more, temperature 800 to 1100 ° C, pressure 10 to 1
00 torr, and time is 30 minutes to 2 hours.
【００１１】次いで、図２に示すように、上記パッド酸
化膜２の上にシリコン基板１の酸化防止層としての窒化
膜４を１００〜２００ｎｍの厚さに蒸着した後、素子分
離領域パターンマスクを使用して所定のフィールド領域
（素子分離領域）となる箇所の窒化膜４およびパッド酸
化膜２をエッチングにより除去して、パターニングす
る。この時、小量の窒素原子３が存在するパッド酸化膜
２のシリコン基板１との境界層も併せてエッチング除去
する。Next, as shown in FIG. 2, a nitride film 4 as an oxidation preventing layer of the silicon substrate 1 is vapor-deposited on the pad oxide film 2 to a thickness of 100 to 200 nm, and then an element isolation region pattern mask is formed. The nitride film 4 and the pad oxide film 2 which are to be used as a predetermined field region (element isolation region) are removed by etching and patterned. At this time, the boundary layer between the pad oxide film 2 having a small amount of nitrogen atoms 3 and the silicon substrate 1 is also removed by etching.
【００１２】次いで、図３に示すように、スペーサ用の
窒化膜を１０〜５０ｎｍの薄い厚さに蒸着した後、湿式
エッチングにより垂直な側壁部を除く残り部分を除去し
て、側壁部に窒化膜スペーサ５を形成し、追ってシリコ
ン基板１の露出部分をさらに２０〜７０ｎｍの深さにエ
ッチングして、トレンチを形成する。Next, as shown in FIG. 3, a spacer nitride film is deposited to a thin thickness of 10 to 50 nm, and the remaining portion except the vertical sidewall portion is removed by wet etching to nitride the sidewall portion. The film spacer 5 is formed, and the exposed portion of the silicon substrate 1 is further etched to a depth of 20 to 70 nm to form a trench.
【００１３】次いで、図４に示すように、高温で熱酸化
工程を実施し、シリコン基板１のトレンチ内の露出部分
を酸化させることにより、２５０〜３５０ｎｍの厚さを
有する素子分離膜としてのフィールド酸化膜６を形成す
る。Then, as shown in FIG. 4, a thermal oxidation process is performed at a high temperature to oxidize the exposed portion in the trench of the silicon substrate 1 to form a field as an element isolation film having a thickness of 250 to 350 nm. The oxide film 6 is formed.
【００１４】最後に、図５に示すように、酸化防止層と
しての窒化膜パターン４および窒化膜スペーサ５を湿式
エッチングで完全に除去した後、犠牲酸化工程を経て最
終的なフィールド酸化膜６を得る。ここに、犠牲酸化工
程は、基板の表面の損傷部位および不純物を除去する洗
浄工程として、熱酸化工程で犠牲酸化膜を形成した後再
び洗浄して犠牲酸化膜を除去する工程である。Finally, as shown in FIG. 5, after the nitride film pattern 4 and the nitride film spacer 5 as the oxidation preventing layer are completely removed by wet etching, a final field oxide film 6 is formed through a sacrificial oxidation process. obtain. Here, the sacrificial oxidation step is a step of removing the damaged portion and impurities on the surface of the substrate, which is a step of forming the sacrificial oxide film in the thermal oxidation step and then cleaning it again to remove the sacrificial oxide film.
【００１５】以上、図１〜図５による説明は、この発明
をＯＳＥＬＯ法によるプロセスに適用した場合である
が、この発明は、それ以外にも、ＭＯＳＥＬＯ法のよう
に、スペーサ窒化膜を使用しながらシリコン基板にトレ
ンチを形成した後、熱酸化工程によりフィールド酸化膜
を形成する、あらゆる局部酸化プロセスに適用すること
ができる。The above description with reference to FIGS. 1 to 5 shows the case where the present invention is applied to the process by the OSELO method. However, the present invention also uses a spacer nitride film as in the MOSELO method. However, it can be applied to any local oxidation process of forming a field oxide film by a thermal oxidation process after forming a trench in a silicon substrate.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれ
ば、窒素原子層の存在により酸素原子の拡散を抑えるの
で、バーズビークの形成を抑えながら、十分な厚さのフ
ィールド酸化膜を形成することができる。したがって、
小面積でも、分離のよい活性領域を確保することがで
き、半導体装置における素子の高集積化に寄与すること
ができる。As described above, according to the present invention, since the diffusion of oxygen atoms is suppressed by the presence of the nitrogen atom layer, it is possible to form a field oxide film having a sufficient thickness while suppressing the formation of bird's beaks. You can Therefore,
Even with a small area, an active region with good isolation can be secured, which can contribute to high integration of elements in a semiconductor device.
【図１】 この発明の一実施形態による半導体装置の素
子分離膜の形成工程における半導体装置の断面図であ
る。FIG. 1 is a sectional view of a semiconductor device in a process of forming an element isolation film of the semiconductor device according to an embodiment of the present invention.
【図２】 この発明の一実施形態による半導体装置の素
子分離膜の形成工程における半導体装置の断面図であ
る。FIG. 2 is a sectional view of the semiconductor device in a step of forming an element isolation film of the semiconductor device according to the embodiment of the present invention.
【図３】 この発明の一実施形態による半導体装置の素
子分離膜の形成工程における半導体装置の断面図であ
る。FIG. 3 is a sectional view of the semiconductor device in a step of forming an element isolation film of the semiconductor device according to the embodiment of the present invention.
【図４】 この発明の一実施形態による半導体装置の素
子分離膜の形成工程における半導体装置の断面図であ
る。FIG. 4 is a sectional view of the semiconductor device in a step of forming an element isolation film of the semiconductor device according to the embodiment of the present invention.
【図５】 この発明の一実施形態による半導体装置の素
子分離膜の形成工程における半導体装置の断面図であ
る。FIG. 5 is a sectional view of the semiconductor device in a step of forming an element isolation film of the semiconductor device according to the embodiment of the present invention.
１…シリコン基板、２…パッド酸化膜、３…窒素原子
層、４…窒化膜、５…窒化膜スペーサ、６…フィールド
酸化膜。1 ... Silicon substrate, 2 ... Pad oxide film, 3 ... Nitrogen atomic layer, 4 ... Nitride film, 5 ... Nitride film spacer, 6 ... Field oxide film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ジュー ムンシク 大韓民国 467−860 キョウンキド イチ ヨンクン ブバリュブ アミ−リ サン 136−１ ヒュンダイ エレクトロニクス インダストリイズ カンパニー リミテ ッド内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jumunshik Republic of Korea 467-860 Kyeonkiddo Ichi Yong Kun Buvalu Amy Risan 136-1 Hyundai Electronics Industries Company Limited
Claims (17)
って、 シリコン基板を提供する段階と、 上記シリコン基板上に酸化膜を形成する段階と、 上記シリコン基板を窒素含有ガスの雰囲気中で熱処理す
ることにより、上記酸化膜に窒素を注入する段階とを含
んでなることを特徴とする方法。1. A method of forming an element isolation film of a semiconductor device, comprising: providing a silicon substrate; forming an oxide film on the silicon substrate; and exposing the silicon substrate in a nitrogen-containing gas atmosphere. Injecting nitrogen into the oxide film by heat treatment.
膜の形成方法であって、 上記窒素含有ガスは、ＮＨ3またはＮＯ2であることを特
徴とする方法。2. The method for forming an element isolation film of a semiconductor device according to claim 1, wherein the nitrogen-containing gas is NH 3 or NO 2 .
膜の形成方法であって、 上記熱処理する段階は、８００℃〜１１００℃の範囲内
の温度で行われることを特徴とする方法。3. The method for forming an element isolation film of a semiconductor device according to claim 1, wherein the heat treatment step is performed at a temperature within a range of 800 ° C. to 1100 ° C.
膜の形成方法であって、 上記熱処理する段階は、３０分〜２時間の範囲の時間行
われることを特徴とする方法。4. The method for forming an element isolation film of a semiconductor device according to claim 1, wherein the heat treatment step is performed for a time in the range of 30 minutes to 2 hours.
膜の形成方法であって、 上記窒素含有ガスは、さらにＮ2 ガスを含有しているこ
とを特徴とする方法。5. The method for forming an element isolation film of a semiconductor device according to claim 2, wherein the nitrogen-containing gas further contains N 2 gas.
膜の形成方法であって、 上記窒素含有ガスは、濃度が５０％以上であることを特
徴とする方法。6. The method for forming an element isolation film of a semiconductor device according to claim 5, wherein the nitrogen-containing gas has a concentration of 50% or more.
膜の形成方法であって、 上記熱処理する段階は、１０ｔｏｒｒ〜１００ｔｏｒｒ
の範囲内の圧力の下で行われることを特徴とする方法。7. The method of forming an element isolation film of a semiconductor device according to claim 1, wherein the heat treatment is performed at 10 torr to 100 torr.
A method which is carried out under pressure in the range of.
膜の形成方法であって、 上記酸化膜の厚さは、５〜５０ｎｍであることを特徴と
する方法。8. The method for forming an element isolation film of a semiconductor device according to claim 1, wherein the oxide film has a thickness of 5 to 50 nm.
って、 シリコン基板を提供する段階と、 上記シリコン基板上に酸化膜を形成する段階と、 上記シリコン基板を窒素含有ガスの雰囲気中で熱処理す
ることにより、上記酸化膜に窒素を注入する段階と、 上記酸化膜上に窒化膜を形成する段階と、 上記窒化膜および酸化膜をパターニングして部分的に除
去することにより、上記シリコン基板の素子分離領域を
露出させる段階と、 上記窒化膜および酸化膜の除去された境界部分の側壁に
窒化膜スペーサを形成する段階と、 上記シリコン基板の露出された部分をエチングすること
により、シリコン基板にトレンチを形成する段階と、 上記トレンチ部分の露出されたシリコン基板を熱酸化さ
せる段階とを含んでなることを特徴とする方法。9. A method of forming an element isolation film of a semiconductor device, comprising: providing a silicon substrate; forming an oxide film on the silicon substrate; and exposing the silicon substrate in a nitrogen-containing gas atmosphere. Injecting nitrogen into the oxide film by heat treatment, forming a nitride film on the oxide film, and patterning and partially removing the nitride film and the oxide film to form the silicon substrate. Exposing the element isolation region, forming a nitride film spacer on the side wall of the boundary where the nitride film and the oxide film are removed, and etching the exposed part of the silicon substrate. Forming a trench in the trench, and thermally oxidizing the exposed silicon substrate in the trench portion.
離膜の形成方法であって、 上記シリコン基板に形成されたトレンチの深さは、２０
〜７０ｎｍであることを特徴とする方法。10. The method for forming an element isolation film of a semiconductor device according to claim 9, wherein the trench formed in the silicon substrate has a depth of 20.
~ 70 nm.
離膜の形成方法であって、 上記窒素含有ガスは、ＮＨ3またはＮＯ2であることを特
徴とする方法。11. The method for forming an element isolation film of a semiconductor device according to claim 9, wherein the nitrogen-containing gas is NH 3 or NO 2 .
離膜の形成方法であって、 上記熱処理する段階は、８００℃〜１１００℃の範囲内
の温度で行われることを特徴とする方法。12. The method for forming an element isolation film of a semiconductor device according to claim 9, wherein the heat treatment step is performed at a temperature within a range of 800 ° C. to 1100 ° C.
離膜の形成方法であって、 上記熱処理する段階は、３０分〜２時間の範囲の時間行
われることを特徴とする方法。13. The method for forming an element isolation film of a semiconductor device according to claim 9, wherein the heat treatment step is performed for a time in the range of 30 minutes to 2 hours.
分離膜の形成方法であって、 上記窒素含有ガスは、さらにＮ2 ガスを含有しているこ
とを特徴とする方法。14. The method for forming an element isolation film of a semiconductor device according to claim 11, wherein the nitrogen-containing gas further contains N 2 gas.
分離膜の形成方法であって、 上記窒素含有ガスは、濃度が５０％以上であることを特
徴とする方法。15. The method for forming an element isolation film of a semiconductor device according to claim 14, wherein the nitrogen-containing gas has a concentration of 50% or more.
離膜の形成方法であって、 上記熱処理する段階は、１０ｔｏｒｒ〜１００ｔｏｒｒ
の範囲内の圧力の下で行われることを特徴とする方法。16. The method for forming an element isolation film of a semiconductor device according to claim 9, wherein the heat treatment step comprises 10 torr to 100 torr.
A method which is carried out under pressure in the range of.
離膜の形成方法であって、 上記酸化膜の厚さは、５〜５０ｎｍであることを特徴と
する方法。17. The method for forming an element isolation film of a semiconductor device according to claim 9, wherein the oxide film has a thickness of 5 to 50 nm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950017885A KR100190363B1 (en) | 1995-06-28 | 1995-06-28 | Forming element isolation region in semiconductor device |
| KR1995P17885 | 1995-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0917780A true JPH0917780A (en) | 1997-01-17 |
Family
ID=19418567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8147483A Pending JPH0917780A (en) | 1995-06-28 | 1996-06-10 | Formation of element separation film of semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0917780A (en) |
| KR (1) | KR100190363B1 (en) |
| CN (1) | CN1075666C (en) |
| DE (1) | DE19625404B4 (en) |
| GB (1) | GB2302758A (en) |
| TW (1) | TW297944B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100439107B1 (en) * | 1997-12-29 | 2004-07-16 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device to prevent leakage current |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19731203A1 (en) * | 1997-07-21 | 1999-02-11 | Siemens Ag | CMOS circuit and method for its manufacture |
| CN104299984A (en) * | 2013-07-19 | 2015-01-21 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
| KR20160000007U (en) | 2014-06-24 | 2016-01-04 | 안숙희 | Bottom block of hydraulic vice |
| CN105390409B (en) * | 2014-09-04 | 2018-06-26 | 北大方正集团有限公司 | The test method and device of beak length |
| KR20190131343A (en) | 2018-05-16 | 2019-11-26 | 현대중공업 주식회사 | Ship |
| CN113838797B (en) * | 2021-11-26 | 2022-03-04 | 广州粤芯半导体技术有限公司 | Preparation method of local oxide layer and preparation method of semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0075875A3 (en) * | 1981-09-28 | 1986-07-02 | General Electric Company | Method of making integrated circuits comprising dielectric isolation regions |
| JPS61174737A (en) * | 1985-01-30 | 1986-08-06 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| US5256895A (en) * | 1987-02-24 | 1993-10-26 | Sgs-Thomson Microelectronics, Inc. | Pad oxide protect sealed interface isolation |
| US4764248A (en) * | 1987-04-13 | 1988-08-16 | Cypress Semiconductor Corporation | Rapid thermal nitridized oxide locos process |
| GB2238658B (en) * | 1989-11-23 | 1993-02-17 | Stc Plc | Improvements in integrated circuits |
| US5298451A (en) * | 1991-04-30 | 1994-03-29 | Texas Instruments Incorporated | Recessed and sidewall-sealed poly-buffered LOCOS isolation methods |
| KR960005553B1 (en) * | 1993-03-31 | 1996-04-26 | 현대전자산업주식회사 | Manufacturing method of field oxide |
| US5382533A (en) * | 1993-06-18 | 1995-01-17 | Micron Semiconductor, Inc. | Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection |
| JPH0730113A (en) * | 1993-07-09 | 1995-01-31 | Sony Corp | Manufacture of mos transistor |
| KR970003893B1 (en) * | 1993-10-25 | 1997-03-22 | 삼성전자 주식회사 | Method of isolation of the elements on the semiconductor device |
-
1995
- 1995-06-28 KR KR1019950017885A patent/KR100190363B1/en not_active IP Right Cessation
-
1996
- 1996-05-16 TW TW085105772A patent/TW297944B/zh active
- 1996-06-10 JP JP8147483A patent/JPH0917780A/en active Pending
- 1996-06-12 GB GB9612263A patent/GB2302758A/en not_active Withdrawn
- 1996-06-25 DE DE19625404A patent/DE19625404B4/en not_active Expired - Fee Related
- 1996-06-27 CN CN96110232A patent/CN1075666C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100439107B1 (en) * | 1997-12-29 | 2004-07-16 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device to prevent leakage current |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970003811A (en) | 1997-01-29 |
| DE19625404B4 (en) | 2005-12-29 |
| KR100190363B1 (en) | 1999-06-01 |
| CN1145532A (en) | 1997-03-19 |
| CN1075666C (en) | 2001-11-28 |
| TW297944B (en) | 1997-02-11 |
| GB2302758A (en) | 1997-01-29 |
| DE19625404A1 (en) | 1997-01-02 |
| GB9612263D0 (en) | 1996-08-14 |
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