JPH0730113A - Manufacture of mos transistor - Google Patents
Manufacture of mos transistorInfo
- Publication number
- JPH0730113A JPH0730113A JP19411893A JP19411893A JPH0730113A JP H0730113 A JPH0730113 A JP H0730113A JP 19411893 A JP19411893 A JP 19411893A JP 19411893 A JP19411893 A JP 19411893A JP H0730113 A JPH0730113 A JP H0730113A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate oxide
- gate electrode
- semiconductor substrate
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体基板上にゲート
酸化膜を介してゲート電極を有するＭＯＳ型トランジス
タの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor having a gate electrode on a semiconductor substrate with a gate oxide film interposed therebetween.
【０００２】[0002]
【従来の技術】ＭＯＳ型トランジスタの製造過程でゲー
ト電極を形成する際には、高エネルギの荷電粒子を利用
するドライエッチングによって多結晶Ｓｉ膜等をパター
ニングするのが、近年では一般的である。ところが、こ
のドライエッチング時に、荷電粒子の照射によるボンド
の切断やチャージアップ等によって、ゲート酸化膜が相
当な損傷を受ける。2. Description of the Related Art In forming a gate electrode in the process of manufacturing a MOS transistor, it has become common in recent years to pattern a polycrystalline Si film or the like by dry etching using high-energy charged particles. However, during this dry etching, the gate oxide film is considerably damaged due to bond breakage and charge-up due to irradiation of charged particles.
【０００３】また、ソース／ドレインを形成するための
その後のイオン注入によっても、特にゲート電極の側端
部におけるゲート酸化膜が大きな損傷を受ける。更に、
半導体基板と同一導電型で半導体基板よりも高濃度であ
り、且つソース／ドレインよりもゲート電極下に入り込
んでいる、ポケットと称されるパンチスルー防止用の拡
散領域を、斜めイオン注入によって形成する際にも、ゲ
ート電極の側端部におけるゲート酸化膜が損傷を受け
る。Subsequent ion implantation for forming the source / drain also causes great damage to the gate oxide film, particularly at the side end portions of the gate electrode. Furthermore,
A diffusion region for preventing punch-through called a pocket, which has the same conductivity type as that of the semiconductor substrate and has a higher concentration than that of the semiconductor substrate, and which is located below the source / drain under the gate electrode, is formed by oblique ion implantation. Also at this time, the gate oxide film on the side end portion of the gate electrode is damaged.
【０００４】ゲート酸化膜が損傷を受けると、ＴＤＤＢ
特性等のゲート酸化膜の耐圧特性が劣化して、主にドレ
イン近傍の高電界領域とゲート電極との間でリーク電流
が流れる。そこで、従来は、ゲート電極を形成した後
に、酸素雰囲気を含むファーネス中で酸化を行って、ゲ
ート電極の側端部におけるゲート酸化膜を補強してい
た。When the gate oxide film is damaged, TDDB
The breakdown voltage characteristics of the gate oxide film such as characteristics are deteriorated, and a leak current mainly flows between the high electric field region near the drain and the gate electrode. Therefore, conventionally, after forming the gate electrode, oxidation is performed in a furnace containing an oxygen atmosphere to reinforce the gate oxide film at the side end portion of the gate electrode.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来のファー
ネス中における処理では、単に追酸化を行っているだけ
で、ゲート酸化膜の膜質を十分には回復させることがで
きず、ゲート酸化膜の耐圧を十分には確保することが難
しかった。従って、従来の方法では、信頼性の高いＭＯ
Ｓ型トランジスタを製造することが難しかった。However, in the conventional treatment in the furnace, the film quality of the gate oxide film cannot be sufficiently recovered by simply performing additional oxidation, and the breakdown voltage of the gate oxide film is not sufficiently recovered. It was difficult to secure enough. Therefore, in the conventional method, a highly reliable MO is provided.
It was difficult to manufacture S-type transistors.
【０００６】[0006]
【課題を解決するための手段】請求項１のＭＯＳ型トラ
ンジスタの製造方法は、ゲート電極１３を形成した後
に、Ｎ2 Ｏを主成分とする雰囲気を含むファーネス中
で、前記ゲート電極１３の側端部と半導体基板１１との
境界部分を酸窒化する工程を有している。According to a first aspect of the present invention, there is provided a method of manufacturing a MOS transistor, wherein after the gate electrode 13 is formed, the side of the gate electrode 13 is exposed in a furnace containing an atmosphere containing N 2 O as a main component. There is a step of oxynitriding the boundary portion between the end portion and the semiconductor substrate 11.
【０００７】請求項２のＭＯＳ型トランジスタの製造方
法は、前記酸窒化を施したゲート酸化膜１２を覆って、
絶縁膜１６から成るＬＤＤ構造用の側壁を前記ゲート電
極１３に形成する工程を有している。According to a second aspect of the present invention, there is provided a method of manufacturing a MOS transistor, which covers the oxynitrided gate oxide film 12,
There is a step of forming a sidewall for the LDD structure made of the insulating film 16 on the gate electrode 13.
【０００８】[0008]
【作用】請求項１のＭＯＳ型トランジスタの製造方法で
は、ゲート電極１３の側端部と半導体基板１１との境界
部分を酸窒化しているので、この境界部分におけるゲー
ト酸化膜１２の膜質が改善されると共に、この境界部分
におけるゲート酸化膜１２がバーズビーク状に厚くなっ
てゲート−ドレイン間の電界を弱めることができ、ＴＤ
ＤＢ特性等のゲート酸化膜１２の耐圧特性が向上する。In the method of manufacturing a MOS transistor according to claim 1, since the boundary portion between the side end portion of the gate electrode 13 and the semiconductor substrate 11 is oxynitrided, the film quality of the gate oxide film 12 at this boundary portion is improved. At the same time, the gate oxide film 12 at this boundary portion becomes thicker in a bird's beak shape, and the electric field between the gate and the drain can be weakened.
The breakdown voltage characteristics of the gate oxide film 12 such as the DB characteristics are improved.
【０００９】また、ゲート電極１３の側端部下における
ゲート酸化膜１２と半導体基板１１との界面付近１９に
窒素が含有され、半導体基板１１の主にドレイン近傍の
高電界領域からゲート酸化膜１２へホットキャリアが注
入されて界面準位や電子トラップが形成されるのを窒素
が抑制するので、ホットキャリア耐性も向上する。Nitrogen is contained in the vicinity 19 of the interface between the gate oxide film 12 and the semiconductor substrate 11 below the side end portion of the gate electrode 13, so that the high electric field region of the semiconductor substrate 11 mainly near the drain to the gate oxide film 12. Since nitrogen suppresses the injection of hot carriers and the formation of interface states and electron traps, hot carrier resistance is also improved.
【００１０】なお、Ｎ2 Ｏを主成分とする雰囲気中で酸
窒化を行っているので、Ｎ2 のみを含む雰囲気の場合の
様に窒化が進行し過ぎることがなく、大きな応力が発生
することがない。また、ファーネス中で処理を行ってい
るので、高速窒化の場合の様な急熱急冷がなく、このこ
とによっても、大きな応力が発生することがない。従っ
て、応力の発生による信頼性の低下はない。Since oxynitriding is performed in an atmosphere containing N 2 O as a main component, nitriding does not proceed excessively as in an atmosphere containing only N 2 and a large stress is generated. There is no. Further, since the treatment is carried out in the furnace, there is no rapid heating and quenching as in the case of high-speed nitriding, and this does not cause a large stress. Therefore, there is no decrease in reliability due to the generation of stress.
【００１１】請求項２のＭＯＳ型トランジスタの製造方
法では、半導体基板１１との界面付近１９が酸窒化され
たゲート酸化膜１２を残したまま、絶縁膜１６から成る
ＬＤＤ構造用の側壁を形成しているので、ホットキャリ
ア耐性が高く、ホットキャリアの注入による相互コンダ
クタンスの劣化等が少ない。In the method of manufacturing a MOS transistor according to the second aspect of the present invention, the side wall for the LDD structure formed of the insulating film 16 is formed while leaving the gate oxide film 12 which is oxynitrided in the vicinity 19 of the interface with the semiconductor substrate 11. Therefore, resistance to hot carriers is high, and deterioration of mutual conductance due to injection of hot carriers is small.
【００１２】[0012]
【実施例】以下、ＬＤＤ構造のＭＯＳ型トランジスタの
製造に適用した本発明の一実施例を、図１を参照しなが
ら説明する。本実施例でも、図１（ａ）に示す様に、シ
リコン基板等である半導体基板１１の表面にゲート酸化
膜１２を形成し、多結晶シリコン膜等をエッチングして
ゲート酸化膜１２上にゲート電極１３を形成するまで
は、従来公知の工程を実行する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of an LDD structure MOS transistor will be described below with reference to FIG. Also in this embodiment, as shown in FIG. 1A, a gate oxide film 12 is formed on the surface of a semiconductor substrate 11 such as a silicon substrate, and a polycrystalline silicon film or the like is etched to form a gate on the gate oxide film 12. Conventionally known processes are performed until the electrode 13 is formed.
【００１３】しかし、本実施例では、次に、Ｎ2 Ｏを主
成分とする雰囲気を含み温度が９５０℃前後であるファ
ーネス中で、ゲート電極１３下におけるチャネル長方向
の中央部を除いて、全体を酸窒化する。これによって、
図１（ｂ）に示す様に、ゲート酸化膜１２のうちで、ゲ
ート電極１３下におけるチャネル長方向の両端部つまり
ゲート電極１３の側端部下の部分がバーズビーク状に厚
くなると共に、ゲート電極１３下以外の部分が数ｎｍ厚
くなり、ゲート電極１３の表面にも、膜厚が数ｎｍの酸
窒化された酸化膜１４が形成される。However, in the present embodiment, next, in a furnace containing an atmosphere containing N 2 O as a main component and having a temperature of about 950 ° C., except for the central portion in the channel length direction below the gate electrode 13, Oxynitriding the whole. by this,
As shown in FIG. 1B, in the gate oxide film 12, both end portions in the channel length direction below the gate electrode 13, that is, the portions below the side end portions of the gate electrode 13 are thickened in a bird's beak manner and the gate electrode 13 is formed. The portion other than the lower portion is thickened by several nm, and the oxynitrided oxide film 14 having a thickness of several nm is also formed on the surface of the gate electrode 13.
【００１４】また、ゲート電極１３下におけるチャネル
長方向の中央部を除いて、ゲート酸化膜１２と半導体基
板１１との界面付近にも、数原子％の窒素が含有され
る。なお、酸窒化のうちの酸化の割合を高めるために
は、雰囲気にＯ2 を添加し、酸窒化のうちの窒化の割合
を高めるためには、雰囲気にＮ2 を添加すればよい。In addition, except for the central portion in the channel length direction under the gate electrode 13, several atomic% of nitrogen is contained near the interface between the gate oxide film 12 and the semiconductor substrate 11. Note that O 2 is added to the atmosphere in order to increase the proportion of oxidation in oxynitriding, and N 2 is added to the atmosphere in order to increase the proportion of nitriding in oxynitriding.
【００１５】次に、酸窒化したゲート酸化膜１２及び酸
化膜１４を残したまま、ゲート電極１３をマスクにした
不純物のイオン注入を行って、図１（ｃ）に示す様に、
ＬＤＤ構造用の低濃度拡散領域１５を形成する。Next, ion implantation of impurities is performed using the gate electrode 13 as a mask while leaving the oxynitrided gate oxide film 12 and oxide film 14 as shown in FIG. 1 (c).
A low concentration diffusion region 15 for the LDD structure is formed.
【００１６】次に、図１（ｄ）に示す様に、酸化膜１６
をＣＶＤ法で全面に堆積させ、酸化膜１６、１４及びゲ
ート酸化膜１２の全面をエッチバックして、酸化膜１６
から成る側壁をゲート電極１３に形成する。そして、ゲ
ート電極１３と酸化膜１６とをマスクにした不純物のイ
オン注入を行って、ソース／ドレインとしての高濃度拡
散領域１７を形成する。最後に、活性化アニールで高濃
度拡散領域１７及び低濃度拡散領域１５の不純物を電気
的に活性化させて、ＬＤＤ構造のＭＯＳ型トランジスタ
１８を完成させる。Next, as shown in FIG. 1 (d), an oxide film 16 is formed.
Is deposited on the entire surface by a CVD method, and the entire surfaces of the oxide films 16 and 14 and the gate oxide film 12 are etched back to form the oxide film 16
The side wall made of is formed on the gate electrode 13. Then, ion implantation of impurities is performed using the gate electrode 13 and the oxide film 16 as a mask to form the high-concentration diffusion region 17 as the source / drain. Finally, activation annealing is performed to electrically activate the impurities in the high-concentration diffusion region 17 and the low-concentration diffusion region 15 to complete the LDD-structure MOS transistor 18.
【００１７】以上の様な実施例では、ファーネス中で酸
窒化を行っているので、ゲート電極１３の側端部と半導
体基板１１との境界部分におけるゲート酸化膜１２が追
酸化によって補強されるのみならず、この境界部分にお
けるゲート酸化膜１２の膜質が改善されて、ＴＤＤＢ特
性等の耐圧特性が向上する。In the above-mentioned embodiments, since oxynitriding is performed in the furnace, the gate oxide film 12 at the boundary between the side end of the gate electrode 13 and the semiconductor substrate 11 is only reinforced by additional oxidation. Of course, the film quality of the gate oxide film 12 at this boundary portion is improved, and the breakdown voltage characteristics such as the TDDB characteristics are improved.
【００１８】また、ゲート電極１３下におけるチャネル
長方向の中央部を除いて、ゲート酸化膜１２と半導体基
板１１との界面付近１９にも、数原子％の窒素が含有さ
れるので、半導体基板１１の主にドレイン近傍の高電界
領域からゲート酸化膜１２へホットキャリアが注入され
て界面準位や電子トラップが形成されるのを窒素が抑制
し、ホットキャリア耐性も向上する。Also, except for the central portion in the channel length direction below the gate electrode 13, the vicinity 19 of the interface between the gate oxide film 12 and the semiconductor substrate 11 also contains several atomic% of nitrogen, so that the semiconductor substrate 11 In addition, nitrogen suppresses the injection of hot carriers into the gate oxide film 12 mainly from the high electric field region near the drain to form the interface states and electron traps, and the hot carrier resistance is also improved.
【００１９】なお、以上の実施例は本発明をＬＤＤ構造
のＭＯＳ型トランジスタの製造に適用したものである
が、本発明は非ＬＤＤ構造のＭＯＳ型トランジスタの製
造にも適用することができる。Although the above-described embodiments apply the present invention to the manufacture of MOS type transistors of LDD structure, the present invention can also be applied to the manufacture of MOS type transistors of non-LDD structure.
【００２０】[0020]
【発明の効果】請求項１のＭＯＳ型トランジスタの製造
方法では、ゲート電極の側端部と半導体基板との境界部
分におけるゲート酸化膜の耐圧特性が向上し、ホットキ
ャリア耐性も向上するので、信頼性の高いＭＯＳ型トラ
ンジスタを製造することができる。According to the method of manufacturing a MOS transistor of the first aspect, the withstand voltage characteristic of the gate oxide film at the boundary between the side end of the gate electrode and the semiconductor substrate is improved, and the hot carrier resistance is also improved. A highly efficient MOS transistor can be manufactured.
【００２１】請求項２のＭＯＳ型トランジスタの製造方
法では、絶縁膜から成るＬＤＤ構造用の側壁を形成して
も、ホットキャリアの注入による相互コンダクタンスの
劣化等が少ないので、信頼性の高いＬＤＤ構造のＭＯＳ
型トランジスタを製造することができる。In the method of manufacturing a MOS transistor according to a second aspect of the present invention, even if a side wall for an LDD structure made of an insulating film is formed, deterioration of mutual conductance due to injection of hot carriers is small, and therefore a highly reliable LDD structure is obtained. MOS
Type transistors can be manufactured.
【図１】本発明の一実施例を工程順に示す側断面図であ
る。FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.
１１ 半導体基板 １２ ゲート酸化膜 １３ ゲート電極 １６ 酸化膜 11 semiconductor substrate 12 gate oxide film 13 gate electrode 16 oxide film
Claims (2)
成分とする雰囲気を含むファーネス中で、前記ゲート電
極の側端部と半導体基板との境界部分を酸窒化する工程
を有するＭＯＳ型トランジスタの製造方法。1. A MOS type having a step of oxynitriding a boundary portion between a side end portion of the gate electrode and a semiconductor substrate in a furnace containing an atmosphere containing N 2 O as a main component after forming the gate electrode. Manufacturing method of transistor.
て、絶縁膜から成るＬＤＤ構造用の側壁を前記ゲート電
極に形成する工程を有する請求項１記載のＭＯＳ型トラ
ンジスタの製造方法。2. The method of manufacturing a MOS type transistor according to claim 1, further comprising the step of forming a sidewall for an LDD structure made of an insulating film on the gate electrode so as to cover the oxynitrided gate oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19411893A JPH0730113A (en) | 1993-07-09 | 1993-07-09 | Manufacture of mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19411893A JPH0730113A (en) | 1993-07-09 | 1993-07-09 | Manufacture of mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0730113A true JPH0730113A (en) | 1995-01-31 |
Family
ID=16319220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19411893A Pending JPH0730113A (en) | 1993-07-09 | 1993-07-09 | Manufacture of mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0730113A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0821405A2 (en) * | 1996-07-25 | 1998-01-28 | Nec Corporation | MOSFET gate insulation and process for production thereof |
| EP0789400A3 (en) * | 1996-02-07 | 1998-11-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| US5990517A (en) * | 1997-03-06 | 1999-11-23 | Fujitsu Limited | Semiconductor memory device containing nitrogen in a gate oxide film |
| US6232187B1 (en) | 1996-05-22 | 2001-05-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US6498374B1 (en) * | 1999-07-01 | 2002-12-24 | Kabushiki Kaisha Toshiba | MOS semiconductor device having gate insulating film containing nitrogen |
| KR20030057875A (en) * | 2001-12-29 | 2003-07-07 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US6670636B2 (en) | 2000-06-15 | 2003-12-30 | Seiko Epson Corporation | Substrate device, method of manufacturing the same, and electro-optical device |
| DE19625404B4 (en) * | 1995-06-28 | 2005-12-29 | Hyundai Electronics Industries Co., Ltd., Ichon | Method for producing a field oxide layer in a semiconductor device |
| KR100762224B1 (en) * | 2001-06-29 | 2007-10-01 | 주식회사 하이닉스반도체 | Method for manufacturing transistor of semiconductor device |
| CN100426525C (en) * | 1996-02-07 | 2008-10-15 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| US7507632B2 (en) | 2006-02-06 | 2009-03-24 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
-
1993
- 1993-07-09 JP JP19411893A patent/JPH0730113A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19625404B4 (en) * | 1995-06-28 | 2005-12-29 | Hyundai Electronics Industries Co., Ltd., Ichon | Method for producing a field oxide layer in a semiconductor device |
| EP0789400A3 (en) * | 1996-02-07 | 1998-11-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| US5972783A (en) * | 1996-02-07 | 1999-10-26 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device having a nitrogen diffusion layer |
| CN100426525C (en) * | 1996-02-07 | 2008-10-15 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| US6232187B1 (en) | 1996-05-22 | 2001-05-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| EP0821405A3 (en) * | 1996-07-25 | 1998-07-29 | Nec Corporation | MOSFET gate insulation and process for production thereof |
| US6057217A (en) * | 1996-07-25 | 2000-05-02 | Nec Corporation | Process for production of semiconductor device with foreign element introduced into silicon dioxide film |
| EP0821405A2 (en) * | 1996-07-25 | 1998-01-28 | Nec Corporation | MOSFET gate insulation and process for production thereof |
| US7005393B2 (en) | 1997-03-06 | 2006-02-28 | Fujitsu Limited | Method of fabricating a semiconductor device containing nitrogen in an oxide film |
| US6979658B2 (en) | 1997-03-06 | 2005-12-27 | Fujitsu Limited | Method of fabricating a semiconductor device containing nitrogen in a gate oxide film |
| US5990517A (en) * | 1997-03-06 | 1999-11-23 | Fujitsu Limited | Semiconductor memory device containing nitrogen in a gate oxide film |
| US6498374B1 (en) * | 1999-07-01 | 2002-12-24 | Kabushiki Kaisha Toshiba | MOS semiconductor device having gate insulating film containing nitrogen |
| US6670636B2 (en) | 2000-06-15 | 2003-12-30 | Seiko Epson Corporation | Substrate device, method of manufacturing the same, and electro-optical device |
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