JPH09149636A - Switching power device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the loss at the time of rectification and current returning operation by turning a MOS transistor for rectification on and turning an inversion-side MOS transistors off at the time of rectification, and turning both MOS transistors on at the time other than this. SOLUTION: MOS transistors M1 -M4 are enhancement MOS transistors which are turned on by high levels and off by low levels, and constitute a full-bridge inverter. And M1 and M4 , and M2 and M3 form pairs, and the primary winding of a transformer T1 is driven through a capacitor C1 inserted for preventing the polarized magnetism of the transformer T1 . Besides, MOS transistors M5 , M6 being devices for synchronous rectification become on the inversion side, and are so controlled that they may be on in periods other than controlled-to-off periods. And rectifying operation is performed in the on-periods, and a current is supplied to a load RL through a smoothing circuit consisting of an inductance L1 and a capacitor C1 , and a return current is caused to flow after the rectifying operation. As the result, it becomes possible to reduce the loss of a power device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device, and more particularly to a switching power supply device in which a center tap type full-wave rectification circuit is composed of a synchronous rectification circuit.

[0002]

2. Description of the Related Art As conventional technology related to switching power supply devices, for example, "Switching Regulator Design Know-how" by Akira Hasegawa, April 10, 1985 QC
Publishing Co., Ltd. First edition issue Page 28 Figure 1-13 (a)
Techniques of various circuit systems as described in (e) to (e) are known. And, especially as a circuit system suitable for large capacity, half bridge, full bridge circuit is used,
A center tap type full-wave rectifier circuit is often used.

In a power supply device having a center tap type full-wave rectifier circuit, efforts are made to minimize the loss due to the forward voltage drop of the semiconductor by using a Schottky diode as the rectifier element. The diode functions not only for the rectifying operation but also for flowing a return current due to the inductance of the output filter after the rectifying operation.

In order to improve the efficiency of the power supply device, it is desired to improve the efficiency of this rectifying portion, which accounts for half of the total loss of the power supply device, and a method of performing synchronous rectification using a MOS transistor is also considered. However, even in this case, a diode for flowing a return current is required, and loss due to this diode occurs, which makes it difficult to improve efficiency.

Further, there is a resonance power supply device as a power supply device capable of improving efficiency. As a conventional technique related to this type of power supply device, for example, "Product-&-Applicat.
ionsHandbook 1993-94 ”Unitrode Integrated Cincuits
The technology described on pages 9-201, etc. of Corpovation is known. This resonance type power supply device has a small switching loss and can be downsized by increasing the switching frequency. However, in the example of the above document, the efficiency is 75%.
%.

In addition to the above, "Electronic Technology: Switching Power Supply Design Handbook" published by Nikkan Kogyo Shimbun Co., Ltd. 1989 Vo
Various circuits described on pages 14 to 15 of l.31 No. 3 are known.

[0007]

In the prior art in which the synchronous rectification is performed using the MOS transistor described above, the MOS transistor is controlled to be turned on only during the rectifying operation and turned off at other times. . Then, in this conventional technique, the return current after the rectifying operation flows through the body diode parasitic on the MOS transistor, or through a separately provided diode for flowing the return current.

As a result, according to this prior art, when the return current is passed through the body diode, a loss of 7 to 8 times the loss during the ON operation of the rectifying MOS transistor occurs, and in order to avoid this loss. It is necessary to make the off period extremely short, which causes a problem that the operating range of the switching power supply device becomes narrow. Further, when a freewheeling diode is provided and a freewheeling current is passed through this diode, a diode having substantially the same capacity as in the rectifying operation is required, which causes a disadvantage in cost. Furthermore, in order to flow a return current, MO
There is also a method of providing an S transistor, but in this case as well,
It is disadvantageous in terms of size and cost.

An object of the present invention is to solve the above-mentioned problems of the prior art and to have a rectifier circuit capable of reducing the loss during rectification and the loss during recirculation operation, suppressing an increase in the amount of material and downsizing. It is to provide a possible switching power supply device.

More specifically, the loss during rectification is 1/100 times that of a rectifier circuit using a Schottky diode or the like.
It is reduced to 4 to 1/5 and the loss at reflux is 1 / 8-
It is to provide a switching power supply device that can be reduced to 1/10.

[0011]

According to the present invention, the object is to configure a rectifier circuit by a center tap type synchronous rectifier circuit using a MOS transistor, and to turn on a MOS transistor for rectifying during rectifying operation. Inversion side MO
This is achieved by turning off the S transistor and turning on both MOS transistors during the other operation period.

Further, in addition to the above, the object is to provide a further wound gate drive winding on the center tap winding of the transformer, or have a gate drive winding for applying the same primary side voltage as the main transformer. This is achieved by providing a separate transformer, providing a diode for connecting the gate and source of the rectifying MOS transistor, and driving the diode by the MOS transistor gate drive winding.

Further, the above-mentioned object is to connect with a switch composed of a second MOS transistor instead of the above-mentioned diode for connecting between the gate and the source, and to connect one of the M for rectification.
This is achieved by turning on the second MOS transistor connected to the other rectifying MOS transistor during the rectifying operation period of the OS transistor and turning it off during the other operating period.

It is natural that the loss can be reduced by using a synchronous rectification circuit using MOS transistors as the rectification circuit, and the most characteristic point of the present invention is that the MOS transistors are sufficiently turned on. The control is to reduce the loss during the reflux operation by utilizing the characteristic that the impedance becomes low.

Generally, in a synchronous rectifier circuit, an inverter provided on the primary side of a transformer and a rectifying MOS transistor are turned on and off in synchronization with each other. Normally, the rectifying MOS transistor is turned on for a rectifying period. It is controlled to be turned on and turned off during the reflux period. When such control is performed, the return current flows through the body diode of the MOS transistor, causing a loss.

According to the present invention, the rectifying MOS transistor is turned on during the return period and a return current is passed through the rectifying MOS transistor to reduce loss. That is, the path through which the return current flows is the MOS transistor after the rectification operation and the MOS transistor on the inverting rectification side. Therefore, by turning on the MOS transistors on both sides during the return operation, the low impedance when the MOS transistor is turned on is achieved. By the effect, it is possible to reduce the loss in the MOS transistor that flows the return current.

In order to perform the rectifying operation, the MOS on the inversion side is
The transistor is off during the rectifying operation,
It is necessary to control so that it turns on when the recirculation operation is started. Such an operation can be performed by level-shifting and using the output voltage of the gate drive winding wound on the same transformer. For this reason,
According to the present invention, the gate winding provided in the transformer and the gate of the MOS transistor are capacitively coupled, and the level shift is performed using the diode. Also, the present invention
In order to ensure the off operation of the MOS transistor, the diode can be replaced with another MOS transistor.

The synchronous rectifier circuit is generally constructed by using MOS transistors. If the MOS transistor is an N-channel type, it turns on when a voltage exceeding the threshold voltage higher than the source potential is applied to the gate, and turns off when the voltage is lowered. The synchronous rectifier circuit performs rectification by controlling on / off of a rectifying MOS transistor according to the output voltage of the transformer. This control is possible by turning on and off the MOS transistor by the output voltage of the transformer.
It is also possible to use a signal for turning on and off the S transistor. Then, by generating a control signal for turning on and off the rectifying MOS transistor at the timing of performing the freewheeling operation and driving the rectifying MOS transistor, it is possible to reduce the loss during the freewheeling.

According to the present invention, by providing the gate drive winding in the main transformer used as a power supply, the rectifying MOS transistor can be driven without providing a special drive circuit. Further, according to the present invention, the voltage of the gate winding provided in the transformer is level-shifted by the combination of the capacitor and the diode, and the rectification side MOS during rectification
The transistors are turned on, the inverting side MOS transistor is turned off, and both MOS transistors are turned on during the return.

When the gate voltage becomes negative, the gate voltage is clamped by the diode,
The source-to-source voltage becomes almost 0 V, and the MOS transistor is turned off. At this time, a positive charge on the gate side is accumulated in the capacitor, and when the gate winding voltage returns to 0 V, a positive voltage is applied to the gate between the gate and the source, turning on the rectifying MOS transistor. Becomes Of course, even if the gate winding turns positive, M for rectification
The OS transistor is turned on. It is also possible to separately provide a gate drive transformer and perform the same operation. In this case, the same drive voltage as that of the main transformer is applied to the primary side of the gate drive transformer.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a switching power supply device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a switching power supply device according to a first embodiment of the present invention, and FIG. 2 is a diagram showing operation waveforms of respective parts for explaining the operation of FIG. In FIG. 1, T ₁ is a transformer, M _{1 to} M ₆ are MOS transistors, D _{1 to} D ₆ are body diodes which are parasitic elements of MOS transistors, L ₁ is a smoothing inductance, and C ₁ is a transformer for preventing magnetic bias. Capacitor, C ₂ is a smoothing capacitor, C ₃ is a snubber capacitor, R ₁ is a snubber resistor, R
_L is the load.

In the circuit shown in FIG. 1, MOS transistors M _{1 to} M ₄ are enhancement type MOS transistors which are turned on at a high level and turned off at a low level, and form a full-bridge inverter. These transistors M ₁ ~M ₄ is controlled by a gate drive signal V ₁ ~V ₄ to the primary winding of the transformer T _1, via a capacitor C ₁ for biased magnetization prevention of the transformer T _1, Power supply voltage +
A current i _T having a required duty is supplied from V _I and −V _I. The current flowing in the secondary winding of the transformer T ₁ by this current is synchronously rectified by the MOS transistors M ₅ and M _{6 for} synchronous rectification, and the rectified direct current is the inductance L ₁ that constitutes the output smoothing filter. It is supplied to the load R _L via the capacitor C ₂ . The output voltage V _O supplied to the load R _L of this power supply device is the power supply voltage + V _I , −
And V _I, and the duty of the current i _T flows to the primary winding of the transformer T _1, determined by a winding ratio of the transformer T _1.

The operation waveform shown in FIG. 2 shows the waveform of each position and each signal shown in FIG. 1, and V _{1 to} V ₆ are the gate drive waveforms of M _{1 to} M ₆ . Also, H shown along with the waveforms shown as V _{1 to} V ₆ shows a high level, L shows a low level, and the transistors M _{1 to} M ₆ turn on at a high level and turn off at a low level. Further, in FIG. 2, t _{1 to} t ₇ are periods representing the operation state.

In the circuit shown in FIG. 1, the MOS transistors M _{1 to} M ₄ forming the inverter are M ₁ , M ₄ and M _2.
And M ₃ is paired to drive the primary winding of the transformer T ₁ via the capacitor C ₁ to be inserted to prevent the DC magnetic deviation of the transformer T _1. MOS transistors M _5, M ₆ is a synchronous rectification element, becomes inverted side is controlled to be turned on for the period other than the period are controlled to be off, commutation period is in this ON state The operation is performed to supply the current to the load _RL via the smoothing circuit including the inductance L ₁ and the capacitor C _2, and at the same time, the operation of flowing the return current after the rectifying operation is performed.

Next, the operation of the power supply device according to the first embodiment of the present invention will be described for each operation period with reference to FIGS.

The period t ₁ is a period in which the MOS transistors M ₁ and M ₄ forming the inverter are turned on by the gate drive voltages V ₁ and V ₄ , and the transformer T ₁ is started to be driven.
This is a period in which the current on the secondary side of the transformer T ₁ is switched from the current i ₃ to i ₄ . In this period t ₁ , the transformer T ₁
Although the voltages v ₁ -v ₂ on the primary side of
The voltages v3 and v4 on the secondary side of ₁ have not changed. The reason is that the current i ₃ on the secondary side of the transformer T ₁ decreases and the current i ₃ decreases.
_{This is because 4} increases and, as a result, a short-fall current appears to flow on the secondary side of the transformer T ₁ and is not output as a terminal voltage. The secondary side terminal voltage of the transformer T ₁ occurs when the commutation from the current i ₃ to the current i ₄ ends, and this time point becomes the starting point of the period t ₂ .

The period t ₇ is a period in which the same operation as that of the above-mentioned period t ₁ is performed, and the period t ₄ is a period before the start of the inversion side rectification period t ₅ and drives the transformer T ₁ . The same operation as in the period t ₁ is performed except that the direction of the current i _T is different and the relationship between the currents i ₃ and i ₄ is reversed.

The periods t ₂ and t ₅ are periods during which the rectifying operation is performed, and the current i _L is supplied to the inductance L ₁ through the rectifying MOS transistors M ₅ and M ₆ to supply power to the load.
In the period t ₂ , the MOS transistors M ₁ and M _{4 of} the inverter are turned on, and the current i _T flows through the transformer T ₁ . A current i ₄ flows on the secondary side of the transformer T ₁ and the rectifying MOS
A current i _L flows through the transistor M ₆ . Also, the period t
_{In 5} , the MOS transistors M ₂ and M _{3 of} the inverter are turned on, and a current in the direction opposite to the current i _T is passed through the transformer T ₁ . A current i ₃ flows through the secondary side of the transformer T _{1, and} a current i _L flows through the rectifying MOS transistor M ₅ . The operation of flowing the current i _L through the rectifying MOS transistor M ₅ is
It is the same as in the case of the period t ₂ except that the current i _T is inverted.

In the period t ₃ , all the MOS transistors M _{1 to} M ₄ of the inverter are turned off. Therefore, it does not flow a current i _T to the primary side of the transformer T ₁ In the period t _3, must become the secondary side of the current transformer T ₁ also 0A and. However, the current i _L flowing in the inductance L ₁ tends to continue flowing due to the magnetic energy stored in the inductance, and therefore the current must flow in the secondary side of the transformer T ₁ . During this period t ₃ , the above-mentioned transformer T ₁
The contradiction between the primary side and the secondary side of the above is eliminated by operating so as to balance so that the difference between the secondary side currents i ₃ and i ₄ becomes 0A. The current i _L of the inductance L ₁ flowing between the time t ₃ is referred to as a return current of L _1, the relationship between the current i _L of the transformer T ₁ of the secondary current i _3, i ₄ and the inductance L ₁ is As shown in the formula (1), it can be expressed as i _L = i ₃ + i ₄ (1).

The secondary currents i ₃ and i ₄ of the transformer T ₁ during this period t ₃ flow through the rectifying MOS transistors M ₅ and M ₆ . In the period t ₃ , the MOS transistor M ₅ ,
When both MOS transistors of M ₆ are off,
The secondary currents i ₃ and i ₄ of the transformer T ₁ will pass through the body diodes D ₅ and D ₆ of the MOS transistors M ₅ and M ₆ . The body diode is a parasitic diode of a MOS transistor and is a silicon diode. Therefore, the voltage drop in the forward direction is 0.7V to 1.0V.
There is about V, and the power consumption is about twice as large as that in the case where the rectifier circuit is composed of Schottky diodes.

In the first embodiment of the present invention, this period t
_{In FIG. 3} , the gate drive voltages V ₅ and V ₆ of the rectifying MOS transistors M ₅ and M ₆ are kept at a high level to turn on both transistors. As a result, the return current flows through the MOS transistors M ₅ and M ₆ that are in the ON state, and the power loss during the return operation period of this period t ₃ can be significantly reduced. Generally, the purpose of using a MOS transistor for synchronous rectification is to reduce power consumption as compared with a Schottky diode. MO
The forward voltage drop of the S-transistor is smaller than that of the Schottky diode, and is usually 1 /
It is about 4 to 1/5. Therefore, in the first embodiment of the present invention, the power consumed during the return operation period of t ₃ is reduced from 1/8 to 1/10 of the case where the rectifying MOS transistors M ₅ and M ₆ are turned off. And can be greatly reduced.

The period t ₆ is a recirculation operation period during inversion rectification, and its operation is basically the same as the period t ₃ .

In order to realize the highly efficient rectifying operation as described above, the rectifying MOS transistor M ₅ ,
It is necessary to optimally set the driving conditions for M ₆ . Rectification operation in order to be reliably performed in the period t ₂ described above, the gate drive voltage V ₅ of the MOS transistor M ₅ for rectifying a low level, it is necessary to ensure the off operation of the MOS transistor M ₅ Similarly, in order to guarantee the off operation of the MOS transistor M ₆ during the period t _{5 in} which the inversion operation is performed, the rectification MOS is provided at the gate drive timing shown as V ₅ and V _{6 in} FIG. It drives the transistors M ₅ and M ₆ .

If both the rectifying MOS transistors M ₅ and M ₆ are simultaneously turned on in the periods t ₂ and t ₅ , the secondary side of the transformer T ₁ will be in a short-fall state, causing an abnormal current to flow. It will be damaged. Therefore, it is desirable that the gate drive voltages V ₅ and V ₆ for the rectifying MOS transistors M ₅ and M ₆ have a relationship in which the gate drive voltages of the MOS transistors M _{1 to} M ₄ forming the inverter are inverted. The gate drive voltage V _{5 is} obtained by inverting the voltages V ₁ and V _4.
Therefore, it is optimum to use the inverted gate drive voltages V ₂ and V ₃ as the gate drive voltage V ₆ .

In the operation of the first embodiment of the present invention described above, the periods t ₁ , t ₄ , and t ₇ are periods in which the return current of the inductance L ₁ flowing through the transformer T ₁ is switched, and the rectifying MOS is used. The transistors M ₅ and M ₆ may be on or off for a period. Therefore, the above-mentioned relationship between the gate drive voltages V ₁ , V ₄ and V ₆ and the relationship between the gate drive voltages V ₂ , V ₃ and V ₅ are strict during the period of t ₁ , t ₄ and t _7. It doesn't have to be.

FIG. 3 is a circuit diagram showing a configuration of a switching power supply device according to a second embodiment of the present invention, and FIG. 4 is a diagram showing operation waveforms of respective parts for explaining the operation of FIG. In FIG. 3, D ₇ and D ₈ are diodes, C ₄ and C ₅ are capacitors, and other symbols are the same as those in FIG. The second embodiment of the present invention shown in FIG. 3 is the rectifying MO shown in FIG.
A configuration example of an example of a specific way of giving the gate drive voltage V _5, V ₆ for the S transistor, the circuit configuration of the primary side of the transformer T ₁ is omitted since it is identical with FIG.

In the second embodiment of the present invention shown in FIG. 3, when the rectifying MOS transistor M ₆ performs a rectifying operation, the rectifying MOS transistor M ₅ on the inversion side is turned off, and the MOS transistor is turned off during the other period. The operation of turning on both M ₅ and M ₆ is the same as in the case of the first embodiment of the present invention described with reference to FIGS. 1 and 2. Therefore, in the following, the generation and application of the gate drive voltage to the rectifying MOS transistors M ₅ and M ₆ will be mainly described.

During the period t ₂ shown in FIG. 4, when the voltage v ₅ of the gate winding with respect to the MOS transistor M ₅ becomes negative, the MOS transistor M ₅ passes through the capacitor C _4.
Gate voltage v ₇ becomes negative. Then, when the diode D ₇ becomes conductive, electric charge is accumulated in the capacitor C ₄ ,
A voltage is generated such that the transformer T ₁ side of the capacitor C ₄ is negative and the gate side of the MOS transistor M ₅ is positive, the gate voltage v ₇ of the MOS transistor M ₅ is held negative, and the MOS transistor M ₅ is maintained during the period t _{2. 5} is
Keep off. On the other hand, during this period t ₂ , MO
S transistor voltage of the gate winding for M ₆ v ₆ is changed in the positive direction, the gate voltage v ₈ of the MOS transistor M ₆ is further changed in the positive direction, the MOS transistor M ₆ continues the on state.

At the start of the period t ₃ , the terminal voltage v ₅ of the transformer T ₁ changes to 0V from the above state. This allows
Gate voltage v ₇ of the MOS transistor M ₅ is changed to positive, the MOS transistor M ₅ is turned on, during the period t _3, holding the ON state. On the other hand, this period t ₃
In, MOS transistor M voltage v ₆ gate winding for ₆ will vary to 0V, and the gate voltage v ₈ of the MOS transistor M ₆ is not in the negative, the MOS transistor M ₆ continues the on state.

In the period t ₅ after the next period t ₄ , the terminal voltage v ₅ of the transformer T ₁ changes to positive and the terminal voltage v ₆ changes to negative. With this change, the gate voltage v ₇ of the MOS transistor M ₅ further changes to positive and MO
The gate voltage v ₈ of the S transistor M ₆ changes to negative, and the MOS transistor M ₆ is turned off. At this time, the operation of accumulating charges in the capacitor C ₅ via the diode D ₈ is the same as the operation of accumulating charges in the capacitor C ₄ in the period t ₂ .

At the beginning of the period t ₆ , the terminal voltage v ₆ of the transformer T ₁ changes to 0V from the above state. This allows
Gate voltage v ₈ of the MOS transistor M ₆ is changed to the positive, the MOS transistor M ₆ is turned on during the period t _6, holds the ON state. On the other hand, this period t ₆
In, MOS transistor gate voltage of the winding relative to M ₅ v ₅ will vary to 0V, and the gate voltage v ₇ of the MOS transistor M ₅ is not in the negative, the MOS transistor M ₅ continues the on state.

The subsequent operation is the repetition of the foregoing, with the exception of the period t _2, t _5, MOS transistors M _5, M ₆ is turned on, in the period t _2, MOS transistor M ₆ is turned on, M ₅ is off, and during the period t ₅ , the MOS transistor M
₆ is off and M ₅ is on. That is, the power supply device according to the second embodiment of the present invention shown in FIG. 3 performs the same operation as that of the first embodiment of the present invention described with reference to FIGS. 1 and 2.

FIG. 5 is a circuit diagram showing a configuration of a switching power supply device according to a third embodiment of the present invention, and FIG. 6 is a diagram showing operation waveforms of respective parts for explaining the operation of FIG. In FIG. 5, T ₂ is a gate driving transformer, and other reference numerals are the same as those in FIG. The third embodiment of the present invention shown in FIG. 5 is a configuration example showing another method of applying a gate drive voltage to the rectifying MOS transistor shown in FIG. 3, and a circuit configuration on the primary side of the transformer T _1. Are omitted because they are the same as in FIG.

[0045] Figure 5, the power supply device according to a third embodiment of the present invention shown in FIG. 6, the transformer T ₂ of the for a different gate drive also have a gate windings provided on the primary side of the transformer T ₂ The same drive voltage as that of the main transformer T ₁ (referred to as the main transformer for distinguishing from the gate driving transformer) is applied.

A comparison between the operation waveforms described with reference to FIG. 4 and the operation waveforms shown in FIG. 6 reveals that there are differences in the waveforms during the periods t ₁ , t ₄ , and t ₇ . That is, the gate voltages v ₇ and v ₈ do not change in the cases of FIG. 4 in the periods t ₁ , t ₄ and t ₇ , whereas they change in the case of FIG. The transistors M ₅ and M ₆ are switched. When switched as shown in FIG. 4, the currents i ₃ , i ₄
The periods t ₁ , t ₄ , and t ₇ , which are the commutation operation periods of the above, are the periods following the periods t ₃ and t ₆ in which both the MOS transistors M ₅ and M ₆ are in the ON state and the commutation ends, and the period t _At the beginning of ₁ , t ₄ , t ₇ , both MOS transistors M ₅ , M ₆ are switched. In the case of the second embodiment of the invention described in FIG. 3,
If the timing of this switch operation is delayed, the transformer T
The secondary side of ₁ remains short-circuited and the transformer T ₁ k
The voltages v ₃ , v ₄ , v ₅ , v ₆ on the secondary side cannot be generated, and an abnormal current continues to flow, resulting in a power failure.

Therefore, in the case of the embodiments described with reference to FIGS. 3 and 4, it is desired that the MOS transistors M ₅ and M ₆ be in the ON state with a certain impedance.
It is necessary that the gate voltage is generated at the beginning of the flow of the abnormal current and the MOS transistors M ₅ and M ₆ are switched.

The third embodiment of the present invention shown in FIGS. 5 and 6 is capable of improving the above-mentioned points.
Since the switch can be completed at the start of the commutation operation of the OS transistor, the abnormal operation as in the case of the embodiments described with reference to FIGS. 3 and 4 does not occur.

FIG. 7 is a circuit diagram showing the configuration of the switching power supply device according to the fourth embodiment of the present invention. In FIG. 7, M ₉ and M ₁₀ are MOS transistors, and other symbols are the same as those in FIG. The operation waveform of this circuit is exactly the same as that shown in FIG.

A fourth embodiment of the present invention shown in FIG. 7 is a diode D in the second embodiment described with reference to FIG.
_Since the second MOS transistors M ₉ and M ₁₀ are provided in parallel with ₇ and D ₈ , the off operation of the MOS transistors M ₅ and M ₆ can be made more reliable.

In the circuit described with reference to FIG. 3, when the voltage v ₅ of the gate drive winding changes to a negative value, if there is an overshoot in this voltage, the capacitor c4 will be charged with an unnecessarily large voltage, and the MOS transistor will be charged. In some cases, M ₅ cannot maintain the off state.

In the switching power supply device according to the fourth embodiment of the present invention, when the MOS transistor M ₅ should be turned off, the second MOS transistor M ₉ is turned on, so that there is a large overshoot in the voltage v _5. Even in such a case, stable operation can be guaranteed.

In the fourth embodiment of the present invention described above, the diodes D ₇ and D ₈ are the same as the MOS transistor M.
The body diode of ₉ and M ₁₀ can be used in common.

The above-described fourth embodiment of the present invention can also be applied to the third embodiment of the present invention described with reference to FIG. 5, and similar effects can be obtained.

[0055]

As described above, according to the present invention, in performing the synchronous rectification by the center tap type full-wave rectifier circuit, the rectifying MOS transistor of the rectifying MOS transistor is operated during the period when the reflux current of the inductance of the output filter flows. By turning on both arms, it is possible to significantly reduce the loss of the power supply device. Further, according to the present invention, as compared with the case where a Schottky diode for freewheeling and a MOS transistor are newly provided, it is possible to significantly reduce the size and reduce the cost.

Furthermore, according to the present invention, by the gate winding provided in the transformer instead of the special gate driving circuit,
The rectifying MOS transistor can be driven by a simple circuit, and by providing another transformer for driving the gate, the rectifying MOS transistor can be surely turned off.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a switching power supply device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of respective parts for explaining the operation of FIG.

FIG. 3 is a circuit diagram showing a configuration of a switching power supply device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing operation waveforms of respective parts for explaining the operation of FIG.

FIG. 5 is a circuit diagram showing a configuration of a switching power supply device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing operation waveforms of respective parts for explaining the operation of FIG.

FIG. 7 is a circuit diagram showing a configuration of a switching power supply device according to a fourth embodiment of the present invention.

[Explanation of symbols]

_{M 1 ~M 6, M 9,} M 10 MOS transistors T _1, T ₂ trans D ₁ to D ₆ body diode D ₇ of the MOS transistors, D ₈ diodes C _4, C ₅ capacitor C ₁ magnetic deviation prevention capacitor R ₁ snubber Resistance C ₃ Snubber capacitor L ₁ Smoothing inductance C ₂ Smoothing capacitor _RL Load

Claims (1)

[Claims] 1. A switching power supply device having an inverter provided on the primary side of a transformer and a center tap type full-wave synchronous rectification circuit provided on the secondary side of the transformer, wherein the rectification circuit is composed of two switch elements. ,
At the time of rectifying operation, turn on the switch element that performs rectification,
A switching power supply device characterized in that a switching element on the inverting side is turned off, and both switching elements are turned on during other operation periods.