JPH09134839A - Laminated ceramic passive device - Google Patents

Laminated ceramic passive device

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Publication number
JPH09134839A
JPH09134839A JP29098695A JP29098695A JPH09134839A JP H09134839 A JPH09134839 A JP H09134839A JP 29098695 A JP29098695 A JP 29098695A JP 29098695 A JP29098695 A JP 29098695A JP H09134839 A JPH09134839 A JP H09134839A
Authority
JP
Japan
Prior art keywords
electrode
external
shape
internal
passive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29098695A
Other languages
Japanese (ja)
Inventor
Keiichi Noi
慶一 野井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP29098695A priority Critical patent/JPH09134839A/en
Publication of JPH09134839A publication Critical patent/JPH09134839A/en
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a laminated ceramic passive device from being damaged even if an anomalous voltage is applied by a method wherein the total thickness of the uppermost layer and lowermost layer of a ceramic layer is set smaller than the thickness of a part of the ceramic layer sandwiched in between inner electrodes, and an insulating layer is formed on all the surface of a device except its outer electrodes. SOLUTION: Ceramic layers 1a, 2, and 1b and inner electrodes 3a and 3b are alternately laminated, and the one ends of the inner electrodes 3a and 3b are connected to the opposed outer electrodes 4 respectively. The total thickness of the uppermost and the lowermost ceramic layer, 1a and 1b, is set smaller than the thickness of the ceramic layer 2 sandwiched in between the inner electrodes 3a and 3b, and an insulating film 5 is formed on all the surface of a laminated ceramic passive device except the outer electrodes 4. The ceramic layers 1a, 1b, and 2 contain SrTiO3 as a main component or SrTiO3 where Sr is partially substituted with one or more elements selected out of Ca, Mg, and Ba, whereby the laminated ceramic passive device of this constitution can be possessed of the characteristics of both a capacitor and a varistor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電子機器や電気機
器で発生するノイズ、パルス、静電気などの異常高電
圧、高周波ノイズからIC,LSIなどの半導体素子お
よび電子機器や電気機器の回路を保護する目的で用いら
れる積層セラミック受動素子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention protects semiconductor devices such as ICs and LSIs and circuits of electronic devices and electric devices from abnormal high voltage such as noise, pulse and static electricity generated in electronic devices and electric devices and high frequency noise. The present invention relates to a monolithic ceramic passive element used for the purpose of

【0002】[0002]

【従来の技術】近年電子機器や電気機器は小型化、多機
能化を実現するためにIC,LSIなどの半導体素子が
広く用いられ、それに伴って電子機器や電気機器のノイ
ズ、パルス、静電気などの異常高電圧に対する耐力は低
下している。そこでこれら電子機器や電気機器のノイ
ズ、パルス、静電気などの異常高電圧に対する耐力を確
保するためにフィルムコンデンサ、電解コンデンサ、半
導体セラミックコンデンサ、積層セラミックコンデンサ
などが用いられているが、これらは、電圧の比較的低い
ノイズや高周波ノイズの吸収、抑制には優れた特性を示
すが、高い電圧のパルスや静電気に対してはその効果を
示さず、半導体素子の誤動作や破壊を引き起こすことが
ある。
2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been widely used for electronic devices and electric devices in order to realize miniaturization and multifunctional functions. The withstand voltage against abnormally high voltage is low. Therefore, film capacitors, electrolytic capacitors, semiconductor ceramic capacitors, monolithic ceramic capacitors, etc. are used to ensure resistance to abnormally high voltages such as noise, pulses, and static electricity of these electronic devices and electric devices. It has excellent characteristics for absorbing and suppressing relatively low noise and high frequency noise, but it does not show its effect for high voltage pulses and static electricity, and may cause malfunction or destruction of semiconductor elements.

【0003】また一方、高い電圧のパルスや静電気を吸
収、抑制するためにはSiC,ZnO系バリスタが用い
られているが、電圧の比較的低いノイズや高周波ノイズ
の吸収、抑制には効果を示さず半導体素子の誤動作を引
き起こすことがある。
On the other hand, SiC and ZnO type varistors are used for absorbing and suppressing high voltage pulses and static electricity, but they are effective for absorbing and suppressing noise of relatively low voltage and high frequency noise. However, it may cause malfunction of the semiconductor element.

【0004】これら両者の欠点を補完するものとして特
開昭57−27001号公報、特開昭57−35303
号公報に開示されているようなSrTiO3系バリスタ
が開発され使用されている。
As a complement to these two drawbacks, JP-A-57-27001 and JP-A-57-35303 are known.
An SrTiO 3 based varistor as disclosed in Japanese Patent Publication has been developed and used.

【0005】[0005]

【発明が解決しようとする課題】積層型SrTiO3
バリスタに関しては前記従来例で提示されているように
様々な材料組成、製造方法が開発されてきたが、いずれ
の場合もプロセス的に複雑であったりして耐環境特性に
劣り実用化のレベルに達していないという問題点を有し
ていた。また得られた素子の特性は電源ラインに加わる
高い電圧のパルスや静電気を吸収、抑制するのにはその
効果を示すが、信号ラインに加わる高周波ノイズの吸
収、抑制は不充分であるといった問題点を有していた。
Regarding the laminated SrTiO 3 type varistor, various material compositions and manufacturing methods have been developed as shown in the above-mentioned conventional example, but in any case, the process is complicated. However, there was a problem in that the environment resistance was poor and the practical level was not reached. Also, the characteristics of the obtained device show its effect in absorbing and suppressing high voltage pulses and static electricity applied to the power supply line, but the problem that absorption and suppression of high frequency noise applied to the signal line is insufficient. Had.

【0006】本発明は前記従来の問題点を解決するもの
で、信号ラインに加わる高周波ノイズの吸収、抑制が可
能でしかも静電気パルスなどの異常電圧が加わっても壊
れず、耐環境特性、特に耐湿性に優れた積層セラミック
受動素子を得ることを目的とするものである。
The present invention solves the above-mentioned problems of the prior art. It is capable of absorbing and suppressing high-frequency noise applied to a signal line and does not break even when an abnormal voltage such as an electrostatic pulse is applied, and has environmental resistance characteristics, particularly humidity resistance. The object is to obtain a monolithic ceramic passive element having excellent properties.

【0007】[0007]

【課題を解決するための手段】本発明の積層セラミック
受動素子はセラミック層と内部電極層が交互に積層され
るように2層の内部電極層を設け、この2層の内部電極
層のそれぞれの一端を対向する外部電極に接続し、最上
層と最下層のセラミック層の厚みの合計が前記内部電極
層によって挟まれるセラミック層の厚みより小さくなる
ように構成し、前記素子の外部電極を除く表面全体に絶
縁性の被膜を形成し、これにより初期の目的を達成する
ものである。
The laminated ceramic passive element of the present invention is provided with two internal electrode layers so that ceramic layers and internal electrode layers are alternately laminated, and each of the two internal electrode layers is provided. One end is connected to the opposing external electrode, the total thickness of the uppermost and lowermost ceramic layers is configured to be smaller than the thickness of the ceramic layers sandwiched by the internal electrode layers, and the surface of the element excluding the external electrodes An insulative film is formed on the entire surface, thereby achieving the initial purpose.

【0008】[0008]

【発明の実施の形態】本発明の請求項1の構成によれ
ば、積層セラミック受動素子の内部電極層によって挟ま
れるセラミック層が1層だけであるため電極間距離を大
きくでき静電容量を小さくすることができる。また、前
記積層セラミック受動素子の最上層と最下層のセラミッ
ク層の厚みの合計が前記内部電極層によって挟まれるセ
ラミック層の厚みより小さいため、電極の両端に加わる
電圧は前記素子の内部電極と対向する外部電極間に加わ
ることになるが、前記素子の外部電極を除く表面全体に
絶縁性の被膜を形成することにより素子表面の抵抗を高
め、前記積層セラミック受動素子の対向する内部電極間
で素子を機能させることができる。
According to the structure of claim 1 of the present invention, since there is only one ceramic layer sandwiched by the internal electrode layers of the monolithic ceramic passive element, the distance between the electrodes can be increased and the capacitance can be reduced. can do. Also, since the total thickness of the uppermost and lowermost ceramic layers of the monolithic ceramic passive element is smaller than the thickness of the ceramic layers sandwiched by the internal electrode layers, the voltage applied across the electrodes faces the internal electrodes of the element. The resistance of the element surface is increased by forming an insulative coating on the entire surface of the element except the external electrodes, and the element is provided between the opposing internal electrodes of the monolithic ceramic passive element. Can function.

【0009】また、内部電極層の形状を種々変えること
により有効電極面積を使用目的に応じて変えることがで
き、電極間距離を大きくし有効電極面積を小さくするこ
とにより静電容量を小さくすることができる。
Further, the effective electrode area can be changed according to the purpose of use by variously changing the shape of the internal electrode layer, and the electrostatic capacitance can be reduced by increasing the distance between the electrodes and decreasing the effective electrode area. You can

【0010】これにより静電容量が小さくなるのに伴い
ノイズ減衰率が最大になる共振周波数を高くすることが
でき、信号ラインに乗ってくる高周波ノイズを吸収、抑
制することができる。また、有効電極面の形状を種々変
えることにより静電容量を変えることなく吸収できるノ
イズエネルギーの大きさを調節することができる。
As a result, it is possible to increase the resonance frequency at which the noise attenuation rate is maximized as the electrostatic capacitance becomes smaller, and it is possible to absorb and suppress the high frequency noise riding on the signal line. Further, by varying the shape of the effective electrode surface, the amount of noise energy that can be absorbed can be adjusted without changing the electrostatic capacitance.

【0011】さらに、セラミック層の主成分をSrTi
3または前記SrTiO3のSrの一部をCa,Mg,
Baのうち少なくとも一つ以上の元素で置換したものを
用いることにより、コンデンサとバリスタの両方の特性
を持たせることができ、これにより静電気パルスなどの
立ち上がりが急峻な異常高電圧が印加されても同素子を
破壊することがなくなる。
Further, the main component of the ceramic layer is SrTi.
O 3 or part of Sr of the SrTiO 3 is replaced with Ca, Mg,
By using Ba substituted with at least one element, it is possible to have characteristics of both a capacitor and a varistor, and even if an abnormal high voltage with a sharp rise such as an electrostatic pulse is applied by this. The element will not be destroyed.

【0012】(実施形態1)まず、第1成分としてSr
CO3,CaCO3,TiO2を(Sr0.98Ca0.02
0.995TiO3の組成比になるようにして99.2モル
%、第2成分としてNb 25を0.3モル%、第3成分
としてMnCO3を0.2モル%、Cr23を0.1モ
ル%、第4成分としてSiO2を0.2モル%秤量し、
ボールミルなどにより2OHr混合、粉砕し、乾燥した
後空気中で800℃で2Hr仮焼し、再びボールミルな
どにより8OHr混合、粉砕し平均粒径が1.0μm以
下になるようにする。こうして得られた粉末にブチラー
ル系樹脂などの有機バインダーと有機溶剤を混合してス
ラリー状とし、ドクター・ブレード法などのシート成形
法により厚さ50μm程度のグリーンシート1を得る。
(Embodiment 1) First, Sr is used as the first component.
COThree, CaCOThree, TiOTwo(Sr0.98Ca0.02)
0.995TiOThree99.2 mol as the composition ratio of
%, Nb as the second component TwoOFive0.3 mol%, the third component
As MnCOThree0.2 mol%, CrTwoOThree0.1 mo
%, SiO as the fourth componentTwo0.2 mol% is weighed,
Mix with 2OHr using a ball mill, crush and dry
After that, it was calcined in air at 800 ° C for 2 hours and then ball-milled again.
The average particle size is 1.0 μm or less after mixing and crushing 8OHr.
So that it is below. Butyler on the powder thus obtained
Organic resin and other organic binders and organic solvents
Sheet forming such as doctor blade method with rally shape
A green sheet 1 having a thickness of about 50 μm is obtained by the method.

【0013】次に、前記グリーンシート1を所定の枚数
積層して図1ならびに図2に示す最下層の無効層1b
(0.4mm厚)を形成し、その上にPdなどからなる一
方の電極が長方形である形状の内部電極3aをスクリー
ン印刷などにより印刷、乾燥し、さらにその上に有効層
2用に前記グリーンシート1を所定枚数積層し、1.2
mm厚とした後、再びPdなどからなる他方の電極が外部
電極に接続される部分を底辺とする三角形である形状の
内部電極3bをスクリーン印刷などにより印刷、乾燥す
る。その際、内部電極3aと3bとは対向して相異なる
端縁に至るように印刷する。最後に前記グリーンシート
1を所定枚数積層して最上層の無効層1a(0.4mm
厚)を形成し、加熱しながら加圧、圧着し、所定の形状
に切断する。
Next, a predetermined number of the green sheets 1 are laminated to form a lowermost ineffective layer 1b shown in FIGS.
(0.4 mm thick) is formed, and an internal electrode 3a made of Pd or the like in which one of the electrodes is rectangular is printed by screen printing or the like and dried, and the green layer for the effective layer 2 is further formed thereon. Lay a specified number of sheets 1 to 1.2
After the thickness is set to mm, the internal electrode 3b having a triangular shape whose bottom is a portion where the other electrode made of Pd or the like is connected to the external electrode is printed and dried by screen printing or the like. At this time, printing is performed so that the internal electrodes 3a and 3b face each other and reach different edges. Finally, a predetermined number of the green sheets 1 are stacked to form the uppermost invalid layer 1a (0.4 mm
(Thickness), pressurize and press-bond while heating, and cut into a predetermined shape.

【0014】次に空気中で800℃で20Hr脱脂仮焼
し、例えばN2:H2=9:1の還元性雰囲気中で121
0℃で10Hr焼成した後、空気中で930℃で2Hr
再酸化する。その後、内部電極3aならびに3bを異な
る端縁に露出させた両端面にAgなどからなる外部電極
4用ペーストを塗布し、空気中で700℃で10分焼成
する。その後、エポキシ樹脂などからなる電気絶縁性物
質5を外部電極を除く素子の表面全体に塗布し、150
℃で30分熱処理し硬化させる。
Next, defatting calcining is performed in air at 800 ° C. for 20 hours, and for example 121 in a reducing atmosphere of N 2 : H 2 = 9: 1.
After baking for 10 hours at 0 ° C, 2 hours at 930 ° C in air
Reoxidize. After that, a paste for the external electrode 4 made of Ag or the like is applied to both end surfaces of the internal electrodes 3a and 3b exposed at different edges, and the paste is baked in air at 700 ° C. for 10 minutes. Then, an electrically insulating substance 5 made of epoxy resin or the like is applied to the entire surface of the element except the external electrode,
Heat at 30 ° C. for 30 minutes to cure.

【0015】次に前記外部電極4用ペースト上に例えば
電解法でNiメッキさらに半田メッキを施して外部電極
4を形成する。
Next, the external electrode 4 is formed on the external electrode 4 paste by, for example, Ni plating and solder plating by an electrolytic method.

【0016】なお、本実施形態で示した積層セラミック
受動素子の形状はW3.20mm×D1.60mm×T2.
00mmの大きさに形成された1×3タイプと呼ばれるも
のである。このようにして得られた積層セラミック受動
素子の初期特性および信頼性試験の結果を(表1)に示
す。
The shape of the monolithic ceramic passive element shown in this embodiment is W3.20 mm × D1.60 mm × T2.
It is called a 1 × 3 type formed to a size of 00 mm. The initial characteristics and reliability test results of the monolithic ceramic passive element thus obtained are shown in (Table 1).

【0017】[0017]

【表1】 [Table 1]

【0018】(表1)の電気的特性については、前記積
層セラミック受動素子に0.1mAの電流が流れた時に
素子の両端に加わる電圧をV0.1mAで示し、静電容量お
よびtanδは1kHzで測定した値を示した。また、信
頼性試験については85℃,85RH%,課電率90
%,500時間後の変化率を示した。ここで課電率とは
素子に印加する電圧を素子の持つ初期のV0.1mAで割っ
た値のことである。
Regarding the electrical characteristics of (Table 1), the voltage applied across the element when a current of 0.1 mA flows through the monolithic ceramic passive element is represented by V 0.1 mA , and the capacitance and tan δ are 1 kHz. The measured value is shown. Also, for the reliability test, 85 ° C, 85RH%, charge rate 90
%, The rate of change after 500 hours is shown. Here, the charge rate is a value obtained by dividing the voltage applied to the element by the initial V 0.1 mA of the element.

【0019】(実施形態2)以下、実施形態2を図3お
よび図4を用いて説明する。前記実施形態1と同様にし
て内部電極層3aおよび3bの形状は両方の電極が外部
電極に接続される部分を底辺とする三角形である積層セ
ラミック受動素子を得た後、外部電極4の部分に有機物
系のレジストを塗布した後乾燥し、Siを主成分とする
アルコキシド溶液からなるコーティング剤に前記積層セ
ラミック受動素子をディップし、100℃で予備乾燥し
た後トルエンなどの有機溶剤などに浸漬し前記レジスト
を溶解除去し、その後250℃で10分焼き付けて被膜
6aおよび6bを形成する。
(Second Embodiment) A second embodiment will be described below with reference to FIGS. 3 and 4. In the same manner as in Embodiment 1, the internal electrode layers 3a and 3b have a triangular shape whose bases are the portions where both electrodes are connected to the external electrodes. After applying an organic resist, it is dried, and the laminated ceramic passive element is dipped in a coating agent composed of an alkoxide solution containing Si as a main component, pre-dried at 100 ° C., and then immersed in an organic solvent such as toluene. The resist is dissolved and removed, and then baked at 250 ° C. for 10 minutes to form coatings 6a and 6b.

【0020】次に前記外部電極上に例えば電解法でNi
メッキさらに半田メッキを施す。このようにして得られ
た積層セラミック受動素子の初期特性および信頼性試験
の結果を(表2)に示す。また図3において6aおよび
6bはコーティング剤によって形成された被膜である。
Next, Ni is formed on the external electrodes by, for example, an electrolytic method.
Plating Further solder plating is applied. The results of the initial characteristics and the reliability test of the monolithic ceramic passive device thus obtained are shown in (Table 2). Further, in FIG. 3, 6a and 6b are coating films formed by a coating agent.

【0021】[0021]

【表2】 [Table 2]

【0022】なお、実施形態1,2ではセラミック粉体
の組成については一部の組合せについてのみ示したが、
SrTiO3を主成分としコンデンサとバリスタの両方
の機能を有するものであればどのような組成であっても
かまわない。また、無効層1a,1bおよび有効層2は
薄いシートを積層して形成したが、厚いシート1枚で形
成してもかまわない。
In the first and second embodiments, the composition of the ceramic powder is shown only for some combinations.
Any composition may be used as long as it has SrTiO 3 as a main component and functions as both a capacitor and a varistor. Further, the ineffective layers 1a and 1b and the effective layer 2 are formed by laminating thin sheets, but one thick sheet may be formed.

【0023】また、実施形態1,2で示した電気絶縁性
物質は一部の種類についてのみ示したが、電気絶縁性が
あればどのようなものであってもかまわない。
Although the electrically insulating substances shown in the first and second embodiments are shown only for some kinds, any substance may be used as long as it has an electrically insulating property.

【0024】また、実施形態1,2で示した内部電極3
a,3bおよび外部電極4はPdやAgといった貴金属
だけでなくCuやNi,Crといった卑金属および卑金
属の酸化物やそれらの混合物であってもかまわない。
Further, the internal electrode 3 shown in the first and second embodiments.
The a, 3b and the external electrode 4 may be not only a noble metal such as Pd or Ag, but also a base metal such as Cu, Ni or Cr, an oxide of a base metal, or a mixture thereof.

【0025】[0025]

【発明の効果】以上に示したように本発明によれば積層
セラミック受動素子のセラミック層と内部電極層が交互
に積層され前記内部電極層によって挟まれるセラミック
層が1層だけであり、素子表面に電気絶縁性の被膜を形
成することにより、電極間距離を最大限に大きくでき静
電容量を小さくすることができる。
As described above, according to the present invention, the ceramic layers and the internal electrode layers of the monolithic ceramic passive element are alternately laminated, and only one ceramic layer is sandwiched between the internal electrode layers. By forming an electrically insulative coating on, the interelectrode distance can be maximized and the capacitance can be reduced.

【0026】また、前記積層セラミック受動素子の最上
層と最下層のセラミック層の厚みの合計を前記内部電極
層によって挟まれるセラミック層の厚みより小さくする
ことにより電極の両端に加わる電圧は前記素子の内部電
極と対向する外部電極間に加わることになるが、前記素
子の外部電極を除く表面全体に絶縁性の被膜を形成する
ことにより素子表面の抵抗が高くなっているので、前記
積層セラミック受動素子の対向する内部電極間で素子を
機能させることができる。
Also, by making the total thickness of the uppermost and lowermost ceramic layers of the monolithic ceramic passive element smaller than the thickness of the ceramic layers sandwiched by the internal electrode layers, the voltage applied across the electrodes is Although it will be applied between the external electrodes facing the internal electrodes, the resistance of the element surface is increased by forming an insulating coating on the entire surface of the element excluding the external electrodes, so that the multilayer ceramic passive element The device can function between the internal electrodes facing each other.

【0027】また、内部電極層の形状を種々変えること
により有効電極面積を使用目的に応じて容易に変えるこ
とができ、電極間距離を大きくし有効電極面積を小さく
することにより静電容量を小さくすることができる。
Further, the effective electrode area can be easily changed according to the purpose of use by variously changing the shape of the internal electrode layer, and the electrostatic capacitance can be reduced by increasing the distance between the electrodes and decreasing the effective electrode area. can do.

【0028】これにより静電容量が小さくなるのに伴い
ノイズ減衰率が最大になる共振周波数を高くすることが
でき、信号ラインに乗ってくる高周波ノイズを吸収、抑
制することができる。また、有効電極面の形状を種々変
えることにより静電容量を変えることなく吸収できるノ
イズエネルギーの大きさを調節することができる。
As a result, it is possible to increase the resonance frequency at which the noise attenuation rate is maximized as the electrostatic capacitance becomes smaller, and it is possible to absorb and suppress the high frequency noise riding on the signal line. Further, by varying the shape of the effective electrode surface, the amount of noise energy that can be absorbed can be adjusted without changing the electrostatic capacitance.

【0029】さらに、セラミック層の主成分をSrTi
3または前記SrTiO3のSrの一部をCa,Mg,
Baのうち少なくとも一つ以上の元素で置換したものを
用いることにより、コンデンサとバリスタの両方の特性
を持たせることが出来る。これにより静電気パルスなど
の立ち上がりが急峻な異常電圧が印加されても素子が破
壊することがなくなる。また、有効電極面積を小さくす
ることにより電流密度が高まるためαを大きくすること
ができ、tanαを小さくし制限電圧を低くすることが
できるとともにサージ耐量、エネルギー耐量を大きくす
ることができる。
Further, the main component of the ceramic layer is SrTi.
O 3 or part of Sr of the SrTiO 3 is replaced with Ca, Mg,
By using a material in which at least one element of Ba is substituted, both characteristics of the capacitor and the varistor can be provided. This prevents the element from being destroyed even when an abnormal voltage such as an electrostatic pulse having a sharp rise is applied. Further, by decreasing the effective electrode area, the current density is increased, so that α can be increased, and tan α can be decreased to reduce the limiting voltage, and at the same time, the surge resistance and energy resistance can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態1における積層セラミック受
動素子の構成を示す断面図
FIG. 1 is a sectional view showing the structure of a monolithic ceramic passive element according to Embodiment 1 of the present invention.

【図2】同実施形態1の内部電極の形状を示す平面図FIG. 2 is a plan view showing the shape of internal electrodes according to the first embodiment.

【図3】本発明の実施形態2における積層セラミック受
動素子の構成を示す断面図
FIG. 3 is a sectional view showing the structure of a monolithic ceramic passive element according to Embodiment 2 of the present invention.

【図4】同実施形態2における内部電極の形状を示す平
面図
FIG. 4 is a plan view showing the shape of internal electrodes according to the second embodiment.

【符号の説明】[Explanation of symbols]

1 グリーンシート 1a 最上層の無効層 1b 最下層の無効層 2 有効層 3a 内部電極 3b 内部電極 4 外部電極 5 絶縁性被膜 1 Green Sheet 1a Top Ineffective Layer 1b Bottom Ineffective Layer 2 Effective Layer 3a Internal Electrode 3b Internal Electrode 4 External Electrode 5 Insulating Film

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】 セラミック層と内部電極層が交互に積層
されるように2層の内部電極層を設け、この2層の内部
電極層のそれぞれの一端を対向する外部電極に接続し、
最上層と最下層のセラミック層の厚みの合計が前記内部
電極層によって挟まれるセラミック層の厚みより小さく
なるように構成し、前記素子の外部電極を除く表面全体
に絶縁性の被膜を形成したことを特徴とする積層セラミ
ック受動素子。
1. Two internal electrode layers are provided so that ceramic layers and internal electrode layers are alternately laminated, and one end of each of the two internal electrode layers is connected to an opposing external electrode,
The total thickness of the uppermost and lowermost ceramic layers is configured to be smaller than the thickness of the ceramic layers sandwiched by the internal electrode layers, and an insulating coating is formed on the entire surface of the element excluding the external electrodes. A monolithic ceramic passive element.
【請求項2】 内部電極層の形状は一方の電極が一端が
外部電極に接続された長方形であり、他方の電極が前記
外部電極と相対向する外部電極に接続された部分を底辺
とする三角形である請求項1記載の積層セラミック受動
素子。
2. The internal electrode layer has a shape of a rectangle in which one electrode is connected to an external electrode at one end, and a triangle whose base is a portion where the other electrode is connected to the external electrode facing the external electrode. The monolithic ceramic passive device according to claim 1, wherein
【請求項3】 内部電極層の形状は一方の電極が一端が
外部電極に接続された長方形であり、他方の電極が前記
外部電極と相対向する外部電極に接続された部分を底辺
とし他の二辺が内部に湾曲した曲線からなる略三角形で
ある請求項1記載の積層セラミック受動素子。
3. The shape of the internal electrode layer is a rectangle in which one electrode is connected to the external electrode at one end, and the other electrode is connected to the external electrode opposite to the external electrode with the bottom as the base. The monolithic ceramic passive element according to claim 1, wherein the two sides are substantially triangular and each has a curved line inward.
【請求項4】 内部電極層の形状は一方の電極が一端が
外部電極に接続された長方形であり、他方の電極が前記
外部電極と相対向する外部電極に接続された部分を底辺
とし他の二辺が外部に湾曲した曲線からなる略三角形で
ある請求項1記載の積層セラミック受動素子。
4. The shape of the internal electrode layer is a rectangle in which one electrode is connected to an external electrode at one end, and the other electrode is connected to the external electrode opposite to the external electrode with the base being the other portion. The monolithic ceramic passive element according to claim 1, wherein the two sides are substantially triangular and each has a curved line that curves outward.
【請求項5】 内部電極層の形状は両方の内部電極が相
対向するそれぞれの外部電極に接続された部分を底辺と
する三角形である請求項1記載の積層セラミック受動素
子。
5. The monolithic ceramic passive element according to claim 1, wherein the shape of the internal electrode layer is a triangle whose base is a portion where both internal electrodes are connected to respective external electrodes facing each other.
【請求項6】 内部電極層の形状は両方の内部電極が相
対向するそれぞれの外部電極に接続された部分を底辺と
し他の二辺が内部に湾曲した曲線からなる略三角形であ
る請求項1記載の積層セラミック受動素子。
6. The shape of the internal electrode layer is a substantially triangular shape in which a portion where both internal electrodes are connected to respective external electrodes facing each other is a base and the other two sides are curved curves inward. A laminated ceramic passive device as described.
【請求項7】 内部電極層の形状は両方の内部電極が相
対向するそれぞれの外部電極に接続された部分を底辺と
し他の二辺が外部に湾曲した曲線からなる略三角形であ
る請求項1記載の積層セラミック受動素子。
7. The shape of the internal electrode layer is a substantially triangular shape in which a portion where both internal electrodes are connected to respective external electrodes facing each other is a base and the other two sides are curved lines that curve outward. A laminated ceramic passive device as described.
【請求項8】 内部電極層の形状は一方の電極が外部電
極に接続された部分を底辺とする三角形であり、他方の
電極が外部電極に接続された部分を底辺とし他の二辺が
内部に湾曲した曲線からなる略三角形である請求項1記
載の積層セラミック受動素子。
8. The shape of the internal electrode layer is a triangle whose base is a portion where one electrode is connected to the external electrode, and the other two sides are internal when the portion where the other electrode is connected to the external electrode is a base. The monolithic ceramic passive element according to claim 1, wherein the monolithic ceramic passive element has a substantially triangular shape with a curved line.
【請求項9】 内部電極層の形状は一方の電極が外部電
極に接続された部分を底辺とする三角形であり、他方の
電極が外部電極に接続された部分を底辺とし他の二辺が
外部に湾曲した曲線からなる略三角形である請求項1記
載の積層セラミック受動素子。
9. The shape of the internal electrode layer is a triangle whose base is a portion where one electrode is connected to the external electrode, and the other side is an external portion where the base is a portion where the other electrode is connected to the external electrode. The monolithic ceramic passive element according to claim 1, wherein the monolithic ceramic passive element has a substantially triangular shape with a curved line.
【請求項10】 内部電極層の形状は一方の電極が外部
電極に接続された部分を底辺とし他の二辺が内部に湾曲
した曲線からなる略三角形であり、他方の電極が外部電
極に接続された部分を底辺とし他の二辺が外部に湾曲し
た曲線からなる略三角形である請求項1記載の積層セラ
ミック受動素子。
10. The shape of the internal electrode layer is a substantially triangular shape having a curve in which one electrode is connected to the external electrode as a base and the other two sides are curved inward, and the other electrode is connected to the external electrode. 2. The monolithic ceramic passive device according to claim 1, wherein the laminated ceramic passive element has a substantially triangular shape with the curved portion being the outer side and the other two sides being curved outward.
【請求項11】 セラミック層の主成分がSrTiO3
またはこのSrTiO3のSrの一部をCa,Mg,B
aのうちの少なくとも一つ以上の元素で置換したもので
あり、かつコンデンサとバリスタの両方の特性を持つも
のである請求項1〜10のいずれか一つに記載の積層セ
ラミック受動素子。
11. The main component of the ceramic layer is SrTiO 3
Alternatively, a part of Sr of this SrTiO 3 is replaced by Ca, Mg, B
11. The monolithic ceramic passive element according to claim 1, wherein the monolithic ceramic passive element is substituted with at least one element of a and has characteristics of both a capacitor and a varistor.
JP29098695A 1995-11-09 1995-11-09 Laminated ceramic passive device Pending JPH09134839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29098695A JPH09134839A (en) 1995-11-09 1995-11-09 Laminated ceramic passive device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29098695A JPH09134839A (en) 1995-11-09 1995-11-09 Laminated ceramic passive device

Publications (1)

Publication Number Publication Date
JPH09134839A true JPH09134839A (en) 1997-05-20

Family

ID=17762991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29098695A Pending JPH09134839A (en) 1995-11-09 1995-11-09 Laminated ceramic passive device

Country Status (1)

Country Link
JP (1) JPH09134839A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100371056B1 (en) * 2000-10-09 2003-02-06 한국과학기술연구원 Fabrication method of SrTiO3 SMD-type varistor-capacitor multifunctional device
WO2016093153A1 (en) * 2014-12-10 2016-06-16 東光株式会社 Electronic component and method of manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100371056B1 (en) * 2000-10-09 2003-02-06 한국과학기술연구원 Fabrication method of SrTiO3 SMD-type varistor-capacitor multifunctional device
WO2016093153A1 (en) * 2014-12-10 2016-06-16 東光株式会社 Electronic component and method of manufacturing same
US10879005B2 (en) 2014-12-10 2020-12-29 Murata Manufacturing Co., Ltd. Electronic component and method of manufacturing same

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