JPH09129818A - Compound semiconductor device provided with buil-in temperature control element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device wherein a chemical compound semiconductor chip is provided, and a current flowing in the chip can be limited, and also thermal runaway and deterioration of characteristics are prevented. SOLUTION: In this device, a lead frame 14 is sandwiched between a semiconductor chip 12 and a PTC (positive temperature coefficient thermistor) 13, which are encapsulated in the same package. When the temperature of the chip 12 rises, the temperature of the PTC 13 also rises. When the temperature of the PTC 13 exceeds a specific temperature which quickly changes the resistance, the PTC resistance value becomes several hundreds times large, so that the resistance value between the compound semiconductor chip 12 and outer electrode terminals becomes large. Hence a current becomes hard to flow in the compound semiconductor chip 12, and its operation is limited, so that deterioration of characteristics and breakdown at the time of high temperature can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device having a temperature control element built therein, and more particularly to a semiconductor device in which a circuit current of the semiconductor device increases (thermal runaway) when a temperature exceeds a certain temperature. PTC (Positive Temperature Coefficient ther) whose resistance value rises at a slightly lower temperature
mistor) is attached to the semiconductor device.

[0002]

2. Description of the Related Art Conventional temperature control means for a semiconductor device is as follows: Conventional method 1: A method in which a temperature sensor is built in the same package and its operation is controlled from the outside of the semiconductor device by its external output (JP-A-4- 102365), Conventional method 2: a method of providing a superconducting layer inside the element and controlling operation by a resistance value that increases with temperature rise (see Japanese Patent Laid-Open No. 1-281768), conventional method 3: negative A method of forming a semiconductor device having a low temperature coefficient by forming a circuit by combining elements having a temperature coefficient of (see Japanese Patent Laid-Open No. 4-11778) .- Conventional method 4: A bimetal (temperature switch) is provided in a power supply circuit. A method of incorporating it is known. Hereinafter, the above-mentioned conventional method 1
4 will be described with reference to the drawings.

(Conventional method 1) FIG. 4 is a "perspective view showing the internal structure of a diode" for explaining the conventional method 1.
This diode 41 includes a semiconductor pellet 42 and a temperature sensor.
The element 45 and the same copper base 46 are mounted on the tower, and the temperature sensor
Signal is taken out from the lead terminal 43 of the diode 41. In FIG. 4, 44 is a bonding wire, 47 is a bonding agent having good thermal conductivity, and 48 is a resin.
In this conventional method 1, the temperature of the PN junction of the diode 41 can be detected, and the temperature condition inside the diode 41 can be known.

(Conventional Method 2) FIG. 5 is a “cross-sectional view showing a semiconductor device” for explaining the conventional method 2. 57 in FIG.
Is a superconducting layer, and this superconducting layer 57 is connected between the emitter layer 51 and the emitter electrode 54 so as to be in series with the current path, as shown in FIG. In FIG. 5, 52 is a base layer, 53 is a collector layer, 55 is a base electrode,
56 is a collector electrode.

In the semiconductor device shown in FIG. 5, in normal use (when used below the critical current and below the critical temperature),
Emitter electrode 54, superconducting layer 57, emitter layer 51, base layer
2 in the current path through 52, collector layer 53, and collector electrode 56
The next current flows. Here, if a short-circuit current tries to flow for some reason, the critical current is exceeded, so superconducting layer 57 prevents superconducting breakdown and increases the resistance, preventing a short-circuit current from flowing and increasing the temperature during the thermal runaway process. Then, the resistance is greatly increased around the critical temperature, and this can be prevented.

(Conventional method 3) FIGS. 6A and 6B are views for explaining the conventional method 3, wherein FIG. 6A is a circuit diagram thereof and FIG.
FIG. 11 is a cross-sectional view of “a semiconductor device in the case of being configured with a planar NPN transistor and a P-channel field effect transistor” in Conventional Method 3.

In the semiconductor device according to the conventional method 3, as shown in FIG.
As shown in (B), a P-channel field-effect transistor (hereinafter referred to as "P-FE") composed of a P-type semiconductor drain 72, a P-type semiconductor base 68, a P-channel 73, and an insulator 74.
(Abbreviated as "T") is connected to the drain gate by the drain gate electrode 75, and the channel of the P-FET is always open. Also, the collector 67 of the N-type semiconductor and the base of the P-type semiconductor. -68, NPN by emitter 69 of N type semiconductor
A transistor (hereinafter abbreviated as "NPN-Tr") is configured. At this time, the base of the P-type semiconductor of NPN-Tr
Since 68 is the source of the P-FET, FIG. 6 (A)
Circuit configuration.

In the circuit of FIG. 6A, the current from the base 63 of the NPN-Tr to the emitter 62 is equal to the drain-source current of the P-FET. In this case, P-FET
Since the temperature coefficient of the drain-source current of N is negative,
When the PN-Tr has the same configuration, the temperature coefficient of the current from the base to the emitter of the NPN-Tr alone is shown in FIG. 6 (A).
The temperature coefficient from the drain / gate terminal 66 to the emitter 62 of the circuit is reduced. This makes it more difficult for destruction due to thermal runaway to occur than the NPN-Tr alone.

(Conventional Method 4) FIG. 7 is a diagram for explaining Conventional Method 4, and is a perspective view showing the internal structure of a semiconductor device using a bimetal as a switch. As shown in FIG. 7, the semiconductor device 81 of the conventional method 4 has a semiconductor pellet 8
2, lead terminal 83, bonding wire 84, copper base 8
5. It is composed of a bimetal (temperature switch) 86 and a ceramic 87, and the temperature switch made of the bimetal 86 is built in the power supply circuit.

[0010]

By the way, in the conventional semiconductor device having a temperature control function, the conventional method 1 requires an external control device such as an external monitor, so that the entire device becomes large. There is a problem. Further, in the conventional method 2, there is a problem that it is difficult to manufacture a superconducting layer having an inflection point of the resistance value on the semiconductor element at a temperature higher than the maximum operating temperature + 50 ° C.

On the other hand, the conventional method 3 has a problem in that it is not possible to form an element having a negative temperature coefficient in a compound semiconductor made of a III-V group wafer. Further, in the conventional method 4, since the difference in the temperature shrinkage of the metal is utilized, the bimetal cannot be fixed in the package, and therefore the mold package cannot be used as the package. There was a problem.

The present invention has been made in view of the problems of the above-mentioned conventional methods 1 to 4, and its object is to:
It is an object of the present invention to solve the above problems and to provide a compound semiconductor device capable of limiting the current flowing through the compound semiconductor chip at a certain temperature or higher and suppressing its operation to prevent thermal runaway and deterioration of characteristics. .

[0013]

According to the present invention, there is provided a semiconductor device comprising:
Temperature control is performed between a semiconductor device including a compound semiconductor element and a lead terminal for supplying a current to the semiconductor device in terms of a circuit, and structurally in the same package. An element (PTC) is provided, and the circuit current of the semiconductor element is controlled according to the temperature change of the compound semiconductor substrate.
As a result, the above-mentioned object compound semiconductor device is provided.

That is, according to the present invention, "a semiconductor chip composed of a semiconductor element formed on a compound semiconductor substrate and a temperature control element are connected between a power supply terminal of the semiconductor chip and an external power supply terminal, and these are connected by a resin. The compound semiconductor device is characterized by being enclosed in the same package according to ".
(Claim 1) is the gist.

According to the present invention, "a metal pattern serving as an external terminal and an internal terminal serving as an electrode of the temperature controlling element itself are provided on the temperature controlling element, and an electrode of a semiconductor chip made of a semiconductor element and a bonding wire. The compound semiconductor device is characterized in that it is electrically connected by-and is covered with a resin. "(Claim 2).

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail below with reference to embodiments of a compound semiconductor device incorporating a temperature control element according to the present invention.

As described above, the present invention is characterized in that the semiconductor device including the compound semiconductor chip is provided with the temperature control element between the bias supply terminals, and the circuit current of the semiconductor chip changes with the temperature change of the compound semiconductor substrate. It is designed to be controlled together. The temperature control element used in the present invention has a PTC (Positive Characteristic Servo) which is made of a material whose resistance increase temperature is in the range of 100 to 200 ° C. and whose resistance value changes from several Ω to several kΩ. Mista) is preferred.

[0018]

Since the compound semiconductor device according to the present invention is provided with the PTC (positive temperature coefficient thermistor) as described above, the resistance value of the PTC becomes several hundred times or more at a certain temperature or higher. Therefore, above that temperature, the current flowing through the compound semiconductor chip can be limited, and the operation is suppressed to prevent thermal runaway and deterioration of characteristics.

[0019]

EXAMPLES Next, the present invention will be specifically described with reference to examples of the present invention, but the present invention is not limited to the following examples and does not deviate from the gist of the present invention. Various changes and modifications are possible within the range.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention.
(First Embodiment) FIG. 2 is a cross-sectional view of a semiconductor device, and FIG. 2 is a schematic view of the structure of the semiconductor device of FIG. 1 and a power supply attached to each power supply terminal.

In the semiconductor device 11 according to the first embodiment, as shown in FIG.
As shown in, the compound semiconductor chip (hereinafter simply referred to as “chip 1
2 ") and the PTC 13 sandwich the lead frame 14 so that the temperature of the PTC 13 can be almost the same as the temperature of the entire chip 12. 15 in FIG.
Is a bonding wire, and 16 is a resin.

Next, in the semiconductor device 11 according to the first embodiment, the cause of a certain dangerous temperature outside the guaranteed temperature, which causes thermal runaway and deterioration of characteristics (use outside the guaranteed temperature, mounting defect) , Over-input, over-voltage, etc.)
The operation will be described. In this explanation, the semiconductor device 11
The guaranteed upper limit of the temperature is 80 ℃, and the dangerous lower limit is 120.
℃, chip 12 drive voltage V _D = 4V, current consumption I _D = 400m
Also, the PTC 13 is made of a material whose resistance value sudden change temperature is 120 ° C. and its resistance value changes from several Ω to 1 kΩ, and the upper limit current of the V _D power supply to be used is 600 mA. .

In this case, when the temperature of the semiconductor device 11 is lower than 120 ° C., the resistance value of the PTC 13 is several Ω, so that the semiconductor device 11
The current consumption of 11 is within the allowable current value of the V _D power supply used. On the other hand, when the temperature of the semiconductor device 11 exceeds 120 ° C., the resistance value of the PTC 13 exceeds 1 KΩ, so that the V _D power supply used is about 100 minutes of the current required for the chip 12 to operate. Only about 1 can be supplied to the chip 12. Therefore, the chip 12 stops operating. As described above, in the semiconductor device 11 according to the first embodiment shown in FIGS. 1 and 2, the operation is stopped at a certain temperature or higher, and there is an advantage that thermal runaway and characteristic deterioration can be prevented.

(Embodiment 2) FIG. 3 shows another embodiment of the present invention.
FIG. 6 is a diagram illustrating a semiconductor device according to (Example 2),
(A) is a sectional view of the semiconductor device, and (B) is a top view of the semiconductor device.

The semiconductor device 31 according to the second embodiment is shown in FIG.
As shown in (A) and (B), a metal pattern 35 serving as an external terminal on the PTC 33 and an internal terminal serving as an electrode of the PTC 33 itself.
36 is provided, is electrically connected to the electrode of the compound semiconductor chip 32 by the bonding wire 34, and is covered with the resin 37.

Therefore, the semiconductor device 31 according to the second embodiment.
Then, there is an advantage that the temperature of the PTC 33 becomes closer to that of the compound semiconductor chip 32 as compared with the first embodiment. In addition,
Since the function of limiting the current is the same as that of the first embodiment, the description thereof will be omitted.

[0027]

As described in detail above, according to the present invention, in a semiconductor device composed of a compound semiconductor chip, a PTC is built in between bias supply terminals, and the resistance value of the PTC becomes several hundreds at a certain temperature or higher. Since it has been doubled,
Above that temperature, the current flowing through the compound semiconductor chip can be limited, and the operation thereof can be suppressed to prevent thermal runaway and deterioration of characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment (Example 1) of the present invention.

2A and 2B are a configuration diagram of the semiconductor device of FIG. 1 and a schematic diagram in which a power source is attached to each power source terminal.

3A and 3B are diagrams illustrating a semiconductor device according to another embodiment (Embodiment 2) of the present invention, in which (A) is a cross-sectional view of the semiconductor device and (B) is a semiconductor device of (A). Top view.

FIG. 4 is a perspective view showing the internal structure of the diode, which is a view for explaining the conventional method 1.

FIG. 5 is a view for explaining the conventional method 2, which is a cross-sectional view of the semiconductor device.

6A and 6B are diagrams illustrating Conventional Method 3, in which FIG. 6A is a circuit diagram thereof and FIG. 6B is a cross-sectional view of a semiconductor device in Conventional Method 3.

FIG. 7 is a perspective view showing the internal structure of a semiconductor device using a bitametal as a switch for explaining the conventional method 4;

[Explanation of symbols]

 11 semiconductor device 12 chip (compound semiconductor chip) 13 PTC 14 lead frame 15 bonding wire-16 resin 31 semiconductor device 32 compound semiconductor chip 33 PTC 34 bonding wire-35 metal pattern (external terminal) 36 internal terminal (PTC) Electrode) 37 Resin 41 Diode 42 Semiconductor pellet 43 Lead terminal 44 Bonding wire 45 Temperature sensor element 46 Copper base 47 Bonding agent 48 Resin 51 Emitter layer 52 Base layer 53 Collector layer 54 Emitter electrode 55 Base Electrode 56 Collector Electrode 57 Superconducting Layer 61 Collector 62 Emitter 63 Base 64 Gate 65 Drain 66 Drain Gate Terminal 67 N-type Semiconductor Collector 68 P-type Semiconductor Base 69 N-type Semiconductor Emitter 70 Insulator 71 Emitter electrode 72 P-type semiconductor drain 73 P channel 74 Insulator 75 Drain gate electrode 81 Semiconductor device 82 Semiconductor pellet 83 Lead terminal 84 Bonding wire-85 Copper base 86 Bimetal (temperature switch) 87 Ceramic

Claims (3)

[Claims] 1. A semiconductor chip composed of a semiconductor element formed on a compound semiconductor substrate and a temperature control element are connected between a power supply terminal of the semiconductor chip and an external power supply terminal, and these are packaged in the same package with a resin. A compound semiconductor device, characterized in that it is encapsulated inside. 2. A metal pattern serving as an external terminal and an internal terminal serving as an electrode of the temperature controlling element itself are provided on the temperature controlling element, and an electric wire is electrically connected to an electrode of a semiconductor chip including the semiconductor element and a bonding wire. A compound semiconductor device characterized in that the compound semiconductor device is configured to be connected to a substrate and covered with a resin. 3. The compound semiconductor device according to claim 1, wherein a PTC (Positive Characteristic Thermistor) having a resistance increase temperature in the range of 100 to 200 ° C. is used as the temperature control element.