JPH09116140A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a MOS-FET whose gate oxide film has the improved reliability. SOLUTION: A nondoped polycrystalline silicon layer 11 and a doped polycrystalline silicon layer 3 which are formed on a semiconductor substrate 1 are etched so as to have the shape of gate electrode to form a gate electrode 3a. The side walls of the gate electrode 3a are oxidized. An oxide film which is formed so as to cover the gate electrode 3a is etched back as far as the surface of the gate electrode 3a is exposed to form side wall spacers 7a on the side walls of the gate electrode 3a. Impurity ions are implanted into the surface of the semiconductor substrate 1 to form source/drain regions 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device improved to improve reliability of a gate oxide film. The present invention also relates to a method for manufacturing such a semiconductor device.

[0002]

2. Description of the Related Art MOS field effect transistors (hereinafter referred to as M
The gate oxide film is becoming thinner along with the miniaturization of OSFET). Therefore, the reliability of the gate oxide film is becoming more and more important. One of the causes of deterioration of the gate oxide film is plasma damage during etching. Therefore, in particular, development of a process for recovering damage to the gate etching portion is essential. As one of them, it has recently been found that the "sidewall oxidation process" is effective. This method is
This is a process of recovering the damaged portion by performing thermal oxidation and supplying oxygen to the damaged portion at the gate edge.

[0003]

The problems of the conventional sidewall oxidation process will be described below.

Referring to FIG. 20, a gate oxide film 2 having a film thickness of 90Å is formed on a first conductivity type silicon substrate 1, and then an n type doped polysilicon layer 3 is formed, for example, 300.
0Å Accumulate. On the n-type doped polysilicon layer 3,
By photolithography, a positive type resist film 4 patterned into the plane shape of the gate electrode is formed.

Referring to FIGS. 20 and 21, resist film 4 is formed.
Using as a mask, the n-type doped polysilicon layer 3 is etched to form the gate electrode 3a. At this time, the edge portion of the gate electrode 3a is damaged by etching. This damage is especially
Enter big. After that, the resist film 4 is removed.

Referring to FIG. 22, side wall of gate electrode 3a
Oxidation, for example at 850 ° C., N _Two10 in the atmosphere
Minutes, O_TwoThe gate electrode 3a is covered for 30 minutes in an atmosphere.
An overlying oxide 5 is formed. By this process,
The damage on the edge of the pole 3a is recovered. Damage times
The reason for recovery is that oxygen was supplied to the damaged area and
It is generally thought that the bonding bond will be restored.
Have been.

At this time, the upper surface of the gate electrode 3a made of n-type doped polysilicon is acceleratedly oxidized. For example, in the heat treatment under the above-mentioned conditions, the silicon substrate 1
While an oxide film of about 30Å is formed above, the surface of the gate electrode 3a is oxidized by about 600Å to 700Å.

Referring to FIG. 23, low-concentration second-conductivity-type source ions are implanted in the surface of silicon substrate 1 by implantation of low-concentration second-conductivity-type impurity ions.
The drain region 6 is formed.

Referring to FIG. 24, oxide film 7 is deposited, for example, 1500 Å so as to cover gate electrode 3a.

Referring to FIGS. 24 and 25, gate electrode 3
The oxide film 7 is entirely etched back until the surface of a and the surface of the low-concentration second conductivity type source / drain region 6 are exposed to form a sidewall oxide 5a and a sidewall spacer 7a. At this time, the thickness of the gate electrode 3a, which is an n-type doped polysilicon layer, is reduced by about 600 to 700Å and becomes 2300 to 2400Å.

Referring to FIG. 26, high-concentration source / drain regions 8 and a low-concentration second conductivity type diffusion layer 9 for improving junction leakage and hot carriers are formed by ion implantation. At this time, if the ion implantation for forming the low-concentration second conductivity type diffusion layer 9 is performed at, for example, P, 50 keV or more (4 × 10 ¹³ ), the ions penetrate through the gate electrode 3a and the gate oxide film 2 is formed. The reliability of the device deteriorates and the transistor characteristics change.

Further, referring to FIG. 27, salicide 10
However, there is a problem that the silicide on the source / drain regions rises up on the gate electrode 3a and the silicide on the gate electrode 3a and the silicide on the source / drain regions 6 and 8 are short-circuited.

The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device improved so that the reliability of the gate oxide film is not deteriorated and the transistor characteristics are not changed. The purpose is to

It is another object of the present invention to provide a semiconductor device improved so that the silicide on the source / drain region and the silicide on the gate electrode will not be short-circuited.

Another object of the present invention is to provide a method of manufacturing such a semiconductor device.

[0016]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, first, a gate oxide film, a doped polysilicon layer, and a non-doped polysilicon layer are formed on a semiconductor substrate. , Forming in this order. The non-doped polysilicon layer and the doped polysilicon layer are etched into the shape of a gate electrode to form a gate electrode. The side wall of the gate electrode is oxidized. An oxide film for forming a sidewall spacer is formed on the semiconductor substrate so as to cover the gate electrode. The oxide film is etched back until the surface of the gate electrode is exposed, thereby forming a sidewall spacer on the sidewall of the gate electrode. Impurity ions are implanted into the surface of the semiconductor substrate to form source / drain regions.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, first, a gate oxide film, a doped polysilicon layer and an antioxidant film are formed on a semiconductor substrate.
Form in this order. The antioxidant film and the doped polysilicon layer are patterned to form a gate electrode. The side wall of the gate electrode is oxidized. An oxide film for forming a sidewall spacer is formed on the semiconductor substrate so as to cover the gate electrode. The oxide film is etched back until the surface of the antioxidant film is exposed, thereby forming sidewall spacers on the sidewalls of the gate electrode. Impurity ions are implanted into the surface of the semiconductor substrate to form source / drain regions.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, first, a gate oxide film, a doped polysilicon layer and a non-doped polysilicon are formed on a semiconductor substrate having an n well and a p well. The layers are formed in this order. The non-doped polysilicon layer and the doped polysilicon layer are patterned to form a first gate electrode on the p well and a second gate electrode on the n well. The n-well side is masked, and low-concentration n-type source / drain regions are formed in the surface of the semiconductor substrate on both sides of the first gate electrode. The sidewalls of the first and second gate electrodes are oxidized. The p-well side is masked and p-type source / drain regions are formed on both sides of the second gate electrode.

In the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, first, a gate oxide film, a doped polysilicon layer and an antioxidant film are formed on a semiconductor substrate.
Form in this order. The antioxidant film and the doped polysilicon layer are patterned to form a gate electrode. The sidewall of the gate electrode is oxidized to form a sidewall oxide. An oxide film is formed on the semiconductor substrate so as to cover the gate electrode. The oxide film is etched back until the surface of the antioxidant film is exposed, whereby sidewall spacers having the same height as the surface of the antioxidant film are formed on the sidewalls of the gate electrode. Source / drain regions are formed in the surface of the semiconductor substrate on both sides of the gate electrode. The antioxidant film is removed. Silicide is formed on the surfaces of the gate electrode and the source / drain regions.

In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, first, a gate oxide film, a doped polysilicon layer and a first silicon nitride film are formed in this order on a semiconductor substrate. . The first silicon nitride film and the doped polysilicon layer are patterned to form a gate electrode. The side wall of the gate electrode is oxidized. A second silicon nitride film is formed on the semiconductor substrate so as to cover the gate electrode. The second and first silicon nitride films are entirely etched back until the surface of the doped polysilicon layer is exposed, thereby forming sidewall spacers on the sidewalls of the gate electrode.

A semiconductor device according to a sixth aspect of the present invention includes a semiconductor substrate. A gate electrode is provided on the semiconductor substrate with a gate oxide film interposed.
An oxide is provided on the side wall of the gate electrode. An antioxidant film is provided on the gate electrode. A sidewall spacer is provided on the sidewall of the gate electrode with the oxide interposed. Source / drain regions are provided on both sides of the gate electrode in the surface of the semiconductor substrate.

In the present invention, it is preferable that the anti-oxidation film is formed of a nitride film. A semiconductor device according to a seventh aspect of the present invention includes a semiconductor substrate. A gate electrode is provided on the semiconductor substrate with a gate oxide film interposed. An oxide is provided on the side wall of the gate electrode. A sidewall spacer is provided on the sidewall of the gate electrode with the oxide interposed. Source / drain regions are provided on both sides of the gate electrode in the surface of the semiconductor substrate. The upper end of the sidewall spacer is higher than the surface of the gate electrode. The surfaces of the gate electrode and the source / drain regions are silicided.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
The figure will be described.

Embodiment 1 of the Invention Referring to FIG. 1, a gate oxide film 2 is deposited on a first conductivity type silicon substrate 1, for example, 90 Å, and then an n-type doped polysilicon layer 3 is formed. , For example 3000 Å is deposited. After that, a non-doped polysilicon layer 11 of, for example, about 100 Å is deposited by a film thickness that is oxidized by sidewall oxidation of a gate electrode described later. After that, a resist pattern 4 having a planar pattern of the gate electrode is formed on the silicon substrate 1 by photolithography.

Referring to FIGS. 1 and 2, the non-doped polysilicon layer 11 and the n-type doped polysilicon layer 3 are patterned using the resist pattern 4 as a mask,
The gate electrode 3a is formed. Then, the resist pattern 4 is removed.

2 and 3, oxide 5 is formed by oxidizing the side wall of gate electrode 3a. At this time, since only the non-doped polysilicon layer 11 is oxidized on the upper portion of the gate electrode 3a, accelerated oxidation does not occur. As a result, as will be described later, the reduction in the film thickness of the gate electrode at the time of forming the sidewall is suppressed to the minimum. Impurity ions are implanted into the surface of the silicon substrate 1 to form the low concentration source / drain regions 6.

Next, although not shown, an oxide film for forming a sidewall spacer is formed on the silicon substrate 1 so as to cover the gate electrode 3a. Etch back the oxide film until the surface of the gate electrode 3a is exposed,
Thereby, referring to FIG. 4, sidewall oxide 5a and sidewall spacer 7a are formed on the sidewall of gate electrode 3a.

Referring to FIG. 4, impurity ions are implanted into the surface of silicon substrate 1 using sidewall spacers 7a as a mask to form high-concentration source / drain regions 8 and low-concentration second conductivity type diffusion layers 9. Form and complete MOSFET. At this time, since the film thickness of the gate electrode 3a is sufficiently thick, the implanted species do not penetrate through the gate electrode a.
As a result, it is possible to increase the margin for preventing penetration of the implanted electrode into the gate electrode.

Embodiment 2 of the Invention Referring to FIG. 5, a gate oxide film 2, a doped polysilicon layer 3, and an anti-oxidation film 12 are deposited on the first conductivity type silicon substrate 1 by 100Å. As the antioxidant film 12, for example, Si ₃ N ₄ , WSi ₂ or the like is used. A resist pattern 4 having a planar pattern of the gate electrode is formed on the antioxidant film 12 by photolithography.

Referring to FIGS. 5 and 6, using resist pattern 4 as a mask, oxidation preventing film 12 and doped polysilicon layer 3 are etched to form gate electrode 3a.

Referring to FIG. 7, the sidewall of gate electrode 3a is oxidized to form sidewall oxide 5. At this time, the surface of the gate electrode 3a is protected by the anti-oxidation film 11 and thus is not oxidized. Therefore, the reduction of the film thickness of the gate electrode 3a is prevented.

Impurity ions are implanted into the surface of the silicon substrate 1 to form low concentration source / drain regions 6.

Thereafter, although not shown, an oxide film for forming a sidewall spacer is formed on the silicon substrate 1 so as to cover the gate electrode 3a. Etch back the oxide film until the surface of the antioxidant film 11 is exposed,
Thereby, referring to FIG. 8, sidewall spacers 7 are formed on the sidewalls of the gate electrode 3a. Impurity ions are implanted to form a high concentration second conductivity type insulating layer and a low concentration second conductivity type diffusion layer 9.

Referring to FIG. 9, interlayer insulating film 14 is formed on silicon substrate 1 so as to cover gate electrode 3a. A resist pattern 4 having a predetermined shape is formed by photolithography. When the contact hole 14a is formed in the interlayer insulating film 14 using the resist pattern 4 as a mask, in the conventional device, on the gate electrode 3a,
Since the film thickness of the interlayer insulating film 14 is smaller than that on the source / drain regions, there is a concern that the gate electrode 3a may be over-etched. However, in the embodiment of the present invention,
Since the antioxidant film 12 is formed on the gate electrode 3a, an effect of preventing overetching (effect of a stopper) can be obtained. The antioxidant film 12 on the contact
Can be removed during contact etching.

Further, in order to use the anti-oxidation film 12 also as the anti-reflection film of the gate photolithography, the anti-oxidation film 12 is a nitride film and has a limited film thickness, for example, about 360Å.
When it is set, a further effect (antireflection) is obtained.

Embodiment 3 of the Invention Since steps up to the photolithography are the same as those in Embodiment 1 of the invention, description thereof will not be repeated.

Referring to FIG. 10, the etching of doped polysilicon layer 3 is stopped immediately before the surface of gate oxide film 2 is exposed. At this time, the remaining film of the doped polysilicon layer 3 is, for example, about 50 to 200 Å. This reduces the damage given to the gate oxide film 2. The reason that the damage to the gate oxide film 2 is reduced is that the etching species do not directly hit the gate oxide film. In the method of completely exposing the gate oxide film 2, the gate oxide film 2 as an insulator is electrically charged and easily damaged when the gate oxide film 2 is exposed. However, the third embodiment of the present invention. Then, since the etching is stopped immediately before the gate oxide film 2 is exposed, such a problem is prevented.

The unetched portion is shown in FIG.
Since the oxide film 5 is oxidized when it is formed, no additional steps are required.

Thereafter, the MOSFET is completed by going through the same process as in the first embodiment of the invention.

Fourth Embodiment of the Invention An embodiment of the present invention relates to application of the present invention to a CMOSFET.

In the PMOS, since the B system having a large diffusion coefficient is generally used to form the source / drain regions, the punch through margin is smaller than that of the NMOS. Embodiment 4 of the present invention relates to a method for improving this.

Referring to FIG. 12, a semiconductor substrate provided with p well 15 and n well 16 is prepared. A gate oxide film 2, a doped polysilicon layer 3 and a non-doped polysilicon layer are formed on a semiconductor substrate. The doped polysilicon layer and the non-doped polysilicon layer are patterned to form a first gate electrode 3a on the p well 15 and a second gate electrode 3b on the n well 16. After that, the n-well 16 side is masked with the resist 4. Using the resist 4 as a mask, a low concentration n-type source / drain region 17 is formed on the surface of the p well 15. The resist 4 is removed. Referring to FIG. 13, the sidewalls of first gate electrode 3a and second gate electrode 3b are oxidized to form oxide 5. At this time, the first and second
The non-doped polysilicon layer 10 formed on the gate electrodes 3a and 3b is also oxidized and becomes an oxide.

Referring to FIG. 14, the p-well 15 side is masked with a resist 4, impurity ions are implanted into the surface of the n-well 16, and p-type source / source is formed on both sides of the second gate electrode 3b.
A drain region 18 is formed. As a result, the side wall oxidation is less heat-treated in the PMOS than in the NMOS, and the implantation species are less likely to enter due to the side wall oxidation.
As a result, shallow junctions are possible. As a result, CMOS
The formation can be performed effectively.

Embodiment 5 of the Invention Referring to FIG. 15, as in Embodiment 2 of the invention, MO
Form SFET. Next, referring to FIGS. 15 and 16, the antioxidant film 11, for example, a nitride film is formed on the gate electrode 3a.
Dry-etch until the surface of is exposed.

Referring to FIG. 17, salicide is formed on the surface of source / drain region 6 and the surface of gate electrode 3a.

Referring to FIG. 16, since the height of sidewall spacer 7a is higher than the surface of gate electrode 3a, a short circuit between gate electrode 3a and silicon substrate 1 due to salicide rise is suppressed.

Embodiment 6 of the Invention Embodiment 2 of the invention until the sidewall oxide 5a is formed
Therefore, the description thereof will not be repeated. In Embodiment 6 of the present invention, the anti-oxidation film 11 is formed of a Si ₃ N ₄ film which also serves as an anti-reflection film.

Referring to FIG. 18, a nitride film 19 is formed on the silicon substrate 1 so as to cover the gate electrode 3a.
Deposit 500Å.

Referring to FIGS. 18 and 19, nitride film 19 is formed.
Is entirely etched back until the surface of the gate electrode 3a is exposed to form the sidewall spacer 19a.
Since the antioxidant film 11 is formed of the silicon nitride film,
Removal of Antioxidant Film 11 and Sidewall Spacer 19a
Can be formed simultaneously.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device in a first step in the order of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 3 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 5 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing a semiconductor device according to the second embodiment of the invention.

FIG. 6 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 7 is a cross-sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device in the second embodiment of the invention.

FIG. 8 is a sectional view of a semiconductor device in a fourth step of the order of the method for manufacturing a semiconductor device according to the second embodiment of the invention.

FIG. 9 is a sectional view of the semiconductor device in a fifth step of the order of the method for manufacturing the semiconductor device in the second embodiment of the invention.

FIG. 10 is a sectional view of a semiconductor device in a first step in the order of a method for manufacturing a semiconductor device according to a third embodiment of the invention.

FIG. 11 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device in the third embodiment of the invention.

FIG. 12 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device in the fourth embodiment of the invention.

FIG. 13 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device in the fourth embodiment of the invention.

FIG. 14 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device in the fourth embodiment of the invention.

FIG. 15 is a sectional view of the semiconductor device in a first step in the order of the method for manufacturing the semiconductor device according to the fifth embodiment of the invention.

FIG. 16 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device in the fifth embodiment of the present invention.

FIG. 17 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device in the fifth embodiment of the present invention.

FIG. 18 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device in the sixth embodiment of the invention.

FIG. 19 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device in the sixth embodiment of the invention.

FIG. 20 is a first sequence of a conventional semiconductor device manufacturing method.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 21 is a second order of the conventional semiconductor device manufacturing method.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 22 is a third order of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 23 is a fourth sequence of the conventional semiconductor device manufacturing method;
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 24 is the fifth order of the conventional semiconductor device manufacturing method;
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 25 is a sixth order of the order of the conventional semiconductor device manufacturing method.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 26 is a seventh part of the order of the conventional semiconductor device manufacturing method.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 27 is an eighth sequence of the conventional semiconductor device manufacturing method.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

[Explanation of symbols]

1 semiconductor substrate, 2 gate oxide film, 3 doped polysilicon layer, 11 non-doped polysilicon layer, 3a
Gate electrode, 7a Sidewall spacer, 6,7
Source / drain region.

Claims (9)

[Claims] 1. A step of forming a gate oxide film, a doped polysilicon layer and a non-doped polysilicon layer in this order on a semiconductor substrate, and the non-doped polysilicon layer and the doped polysilicon layer, A step of forming a gate electrode by etching into a shape of a gate electrode; a step of oxidizing a sidewall of the gate electrode; and an oxidation step of forming a sidewall spacer on the semiconductor substrate so as to cover the gate electrode. Forming a film, etching back the oxide film until the surface of the gate electrode is exposed, thereby forming a sidewall spacer on the sidewall of the gate electrode, and impurities on the surface of the semiconductor substrate. A step of implanting ions to form source / drain regions, a method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching of the doped polysilicon layer is stopped immediately before the surface of the gate oxide film is exposed. 3. A step of forming a gate oxide film, a doped polysilicon layer and an antioxidant film on a semiconductor substrate in this order, and a step of patterning the antioxidant film and the doped polysilicon layer to form a gate. Forming an electrode; oxidizing a sidewall of the gate electrode; forming an oxide film for forming a sidewall spacer on the semiconductor substrate so as to cover the gate electrode; Etching back the oxide film until the surface of the barrier film is exposed, thereby forming a sidewall spacer on the sidewall of the gate electrode, and implanting impurity ions into the surface of the semiconductor substrate to form source / drain regions. And a step of forming a semiconductor device. 4. A step of forming a gate oxide film, a doped polysilicon layer and a non-doped polysilicon layer in this order on a semiconductor substrate having an n-well and a p-well, and the non-doped polysilicon. Patterning the layer and the doped polysilicon layer, forming a first gate electrode on the p-well and forming a second gate electrode on the n-well, and masking the n-well side. Forming low-concentration n-type source / drain regions on both sides of the first gate electrode in the surface of the semiconductor substrate, and oxidizing side walls of the first and second gate electrodes. Masking the p-well side and forming p-type source / drain regions on both sides of the second gate electrode. 5. A step of forming a gate oxide film, a doped polysilicon layer and an antioxidant film on a semiconductor substrate in this order, and patterning the antioxidant film and the doped polysilicon layer to form a gate Forming an electrode; oxidizing a sidewall of the gate electrode to form a sidewall oxide; forming an oxide film on the semiconductor substrate so as to cover the gate electrode; and the antioxidant film. Etching back the oxide film until the surface of the semiconductor substrate is exposed, thereby forming a sidewall spacer having the same height as the surface of the antioxidant film on the side wall of the gate electrode. A step of forming source / drain regions on both sides of the gate electrode, a step of removing the antioxidant film, a step of forming the gate electrode and the saw. / Manufacturing method of a semiconductor device on the surface of the drain region comprising forming a silicide, a. 6. A step of forming a gate oxide film, a doped polysilicon layer and a first silicon nitride film on a semiconductor substrate in this order, and the first silicon nitride film and the doped polysilicon. Patterning the layer to form a gate electrode, oxidizing the sidewalls of the gate electrode, and forming a second silicon nitride film on the semiconductor substrate to cover the gate electrode, Completely etching back the second and first silicon nitride films until the surface of the doped polysilicon layer is exposed to form sidewall spacers on sidewalls of the gate electrode. Production method. 7. A semiconductor substrate, a gate electrode provided on the semiconductor substrate with a gate oxide film interposed, an oxide provided on a sidewall of the gate electrode, and provided on the gate electrode. An anti-oxidation film, a sidewall spacer provided on the side wall of the gate electrode with the oxide interposed, and a source / side spacer provided on both sides of the gate electrode in the surface of the semiconductor substrate. A semiconductor device comprising: a drain region. 8. The semiconductor device according to claim 7, wherein the oxide film is formed of a nitride film. 9. A semiconductor substrate, a gate electrode provided on the semiconductor substrate with a gate oxide film interposed, an oxide provided on a sidewall of the gate electrode, and the oxide with the oxide interposed. A sidewall spacer provided on a sidewall of the gate electrode; and source / drain regions provided on both sides of the gate electrode in a surface of the semiconductor substrate. A semiconductor device, which is higher than a surface of a gate electrode, and surfaces of the gate electrode and the source / drain regions are silicided.