JPH0837300A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor device from decresing in threshold voltage and increasing in flat band voltage by a method wherein impurity ions with accelerating energy large enough to penetrate through one layer out of a multilayered resist film formed on a semiconductor layer are injected into the semiconductor layer to decrease it in resistance after at least one layer out of the multilayered resist film is formed. CONSTITUTION:An amorphous carbon film 29 serving as an antireflection film is formed on a silicon layer 13 which becomes a gate electrode taking advantage of a sputtering method. When the antireflection amorphous carbon film 29 is provided, ions enhanced in accelerating energy can be injected. In this case, ions are made to penetrate into the silicon layer 13 passing though the amorphous carbon film 29. Consequently, the silicon layer 13 can be lessened in resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for implanting ions into a semiconductor layer.

[0002]

2. Description of the Related Art A conventional example will be described by taking a method of manufacturing a complementary MOS field effect transistor (hereinafter referred to as CMOS) as an example.

As shown in FIG. 8A, the silicon substrate 1
A thin oxide film 2 and a silicon nitride (SiN) film 3 are sequentially formed on top.

As shown in FIG. 8B, a resist film 4 is formed, and is patterned by using a photolithography technique to be removed from the n-channel transistor forming region, and a p-type impurity such as boron is implanted. Then, the p-well 5 is formed and the resist film 4 is removed.

As shown in FIG. 8C, a resist film 6 having an opening in a p-channel transistor formation region is formed and an n-well 7 is formed by implanting an n-type impurity such as phosphorus.

As shown in FIG. 9 (a), a resist film 8 is applied and patterned to remain in a region which becomes an element active region, and the SiN film 3 is anisotropically etched using this as a mask. The resist film 8 is removed.

As shown in FIG. 9B, a resist film 9 is formed, patterned to remove it from the p-well 5, and boron is ion-implanted to form a channel stop 10.

As shown in FIG. 9C, thermal oxidation is performed to form a thick field oxide film 11.

As shown in FIG. 10A, the SiN film 3 is removed by using phosphoric acid, and a gate oxide film 12 and a silicon layer 13 to be a gate electrode are laminated.

As shown in FIG. 10B, the silicon layer 1
In order to reduce the resistance of No. 3, a resist film 14 having an opening is formed on the p-well 5, and phosphorus is ion-implanted into the silicon layer 13 in the n-channel transistor formation region to make it n-type.

As shown in FIG. 10C, contrary to the above, a resist film 15 having an opening is formed on the n-well 7, and boron fluoride or boron is ion-implanted into the silicon layer 13 to make it a p-type. To do.

As shown in FIG. 11A, the resist film 1
6 is applied and patterned by using a photolithography technique to remain on the gate electrode formation region.
The resist film formed at this time has a finer pattern due to higher integration of transistors, so a multilayer resist film effective in terms of flatness and antireflection may be used. Using the resist pattern as a mask, the silicon film 13 is etched to form the gate electrode 17, and the resist film 16 is removed.

The case of manufacturing a field effect transistor having a single drain structure will be described below.

As shown in FIG. 11B, the n-well 5
A resist film 18 having an opening is formed thereon, and boron fluoride or boron is ion-implanted to form a p-type source / drain 19.

As shown in FIG. 11C, p-well 5
A resist film 20 having an opening above is formed, phosphorus or arsenic is ion-implanted to form an n-type source / drain 21, and the resist film 20 is removed.

Below, LDD (Lightly Doped Drain)
A case of manufacturing a field effect transistor having a structure will be described.

After proceeding to the step shown in FIG. 11A, as shown in FIG. 12A, a resist film 22 having an opening is formed on the p-well 5, and phosphorus is ion-implanted at a low concentration and shallowly. Then, the LDD region 23 is formed.

The resist film 22 is removed, an insulating film is formed on the entire surface, and anisotropic etching is performed to form a sidewall insulating film 24 on the side wall of the gate electrode 17, as shown in FIG. .

A resist film 25 having an opening is formed on the p-well 5, and arsenic is ion-implanted to form an n-type source / drain 26.

As shown in FIG. 12C, the n-well 7
A resist film 27 having an opening above is formed, boron fluoride or boron is ion-implanted to form a p-type source / drain 28, and the resist film 27 is removed.

Although not shown, in both the single drain structure and the LDD structure, an insulating film is formed on the entire surface to form contact holes on the source / drain, and then the contact holes are filled to form electrodes / wirings. Form.

[0022]

As semiconductor devices have been highly integrated and transistors have been miniaturized, vertical thinning has been advanced. As the film becomes thinner, various problems occur.

First, in the ion implantation step, the acceleration energy has to be lowered in order to prevent the ions from penetrating the thin film to be ion-implanted, so that there is a problem that throughput decreases.

FIG. 13 is a graph showing the relationship between the acceleration energy and the processing time in an ion implanter. In addition,
The dose amount is 1 × 10 ¹⁵ cm ^-2 . As is clear from this figure, when the ion implantation is performed at a low acceleration energy, the processing time significantly increases and the throughput decreases.

Second, in a MOS field effect transistor, when impurities are ion-implanted into a silicon substrate by using a gate electrode as a mask to form a source / drain, the impurity ions channel the gate electrode and penetrate into a channel region, and This is a problem of lowering the threshold voltage V _th of the field effect transistor (Akihiro Nita
yama, Hiroshi Takato, and Riichiro Shirota, New De
gradation Phenomena Induced by Ion-Implantation Cha
nneling in Short Channel Transistor, Extended Abst
racts of the 18th (1986 International) Conference
on Solid State Devices and Materials, Tokyo, 1986)
.

The third problem is that when p-type impurities are ion-implanted into the gate electrode of a p-channel MOS field effect transistor, the ions penetrate into the gate oxide film or the channel region to raise the flat band voltage V _fb ( Philip J. Tobin, Frank K. Baker and James R.
Pfiester, The Effect of Silicon Gate Microstructur
e and Gate Oxide Process on Threshold Voltage Inst
abilities in p ⁺ −Gate p−chammel MOSFET's with F
luorine, IEEE TRANSATIONS ON ELECTRON DEVICES, vo
l. 39, No. 7, July 1992).

As one of the solutions to the problem of such ion penetration, there is a method of reducing the acceleration energy of ion implantation, but as described above, the throughput is reduced, which is not preferable.

An object of the present invention is to eliminate these drawbacks, and even if the ions are implanted with sufficiently high acceleration energy, the ions channel the gate electrode when forming the source / drain of the MOS field effect transistor, for example. Of the gate oxide film or the channel region when the ions are implanted into the gate electrode, thereby lowering the threshold voltage or flat band voltage. It is an object of the present invention to provide a method for manufacturing a MOS field effect transistor that does not rise or has a high throughput.

[0029]

SUMMARY OF THE INVENTION The above-mentioned object is to ion-implant an impurity into the semiconductor layer with an acceleration energy that penetrates at least one layer of the multilayer resist film formed on the semiconductor layer. Then, it is achieved by a method of manufacturing a semiconductor device including a step of reducing the resistance of the semiconductor layer. Then, the low-resistance semiconductor layer manufactured by this method is patterned using the etching mask made of the above-mentioned multilayer resist film to form a MO film.
The gate electrode of the S-type field effect transistor may be formed, and the gate electrode 17 is formed on the semiconductor substrate 1 using this method, and at least the etching mask made of the above-mentioned multilayer resist film is formed on the gate electrode 17. The source / drain 19/21 may be formed by ion-implanting impurities into the semiconductor substrate 1 with one layer left.

The multi-layer resist film may be composed of two layers, the lower layer may be an amorphous carbon film, the upper layer may be a normal resist film, and the multi-layer resist film may be composed of three layers and the lower layer. Is a flattening resist film,
The intermediate layer may be a spin-on-glass (SOG) film, the upper layer may be a normal resist film, the multilayer resist film may be three layers, the lower layer may be an amorphous carbon film, and the intermediate layer may be spin-on. Glass (SOG)
It is a film, and the upper layer may be an ordinary resist film.

[0031]

With the miniaturization of transistors, thinning in the vertical direction is progressing, and it is necessary to implant ions with low acceleration energy so as not to penetrate the thin film.
Therefore, if a multi-layer resist film is formed on the thin film and the ions penetrating the multi-layer resist film enter the thin film, it is possible to perform ion implantation with high acceleration energy and improve the throughput. If the resistance of the gate electrode of the MOS field effect transistor is reduced by this method,
Even if the ions are implanted with high acceleration energy, the ions do not penetrate into the gate oxide film or the channel region, and the resistance can be reduced with high throughput.

When ion-implanting with the gate electrode as a mask for forming the source / drain of the MOS field effect transistor, the multilayer resist film formed when the gate electrode is etched is left on the gate electrode. If the ion implantation is carried out at 1, even if the ions are implanted with high acceleration energy, the ions will not channel through the gate electrode and penetrate into the channel region.

In recent years, with the miniaturization of transistors, it is necessary to form a fine pattern. Therefore, a multilayer resist film effective in terms of flatness and antireflection has been used. Therefore, the multilayer resist of the present invention is used. The use of the membrane does not immediately lead to an increase in the number of steps.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a CMOS field effect transistor according to four embodiments of the present invention will be described below with reference to the drawings.

First Example A case where both the gate electrode of the p-channel MOS field effect transistor and the gate electrode of the n-channel MOS field effect transistor are n-type doped will be described.

Referring to FIG. 10A, the same process as the conventional technique is performed to form the shape shown in FIG.

Referring to FIG. 1A, an amorphous carbon film 29 serving as an antireflection film is formed on the silicon layer 13 serving as a gate electrode by a sputtering method. Note that the antireflection film is indispensable when patterning a fine pattern.

Next, impurity phosphorus is ion-implanted to make the silicon layer 13 an n-type conductive layer. When the amorphous carbon film 29 is not formed, the ion implantation into the silicon layer 13 is carried out with an acceleration energy of about 20 KeV when the thickness of the silicon layer 13 is 1000Å. On the other hand, the antireflection amorphous carbon film 29 is set to 0.5.
When formed to a thickness of μm, the acceleration energy is 150 to
Ions can be implanted by increasing the pressure to 160 KeV. In this case, the ions penetrate the amorphous carbon film 29 and enter the silicon layer 13 to reduce the resistance of the silicon layer 13. Further, it is possible to change the acceleration energy at the time of ion implantation by changing the film thickness of the amorphous carbon film 29, and the throughput is dramatically improved by increasing the acceleration energy.

Referring to FIG. 1B, a resist film 16 is formed and patterned by using a photolithography technique to remain on the gate electrode formation region and the field oxide film 11 surrounding the CMOS formation region.

See FIG. 1C. Amorphous carbon film 29 is formed by dry etching using oxygen gas with resist film 16 as a mask.
Is further etched, and the silicon layer 13 is etched by a dry etching method using a mixed gas of chlorine and oxygen to form a gate electrode 17.

Referring to FIG. 2A, a resist film 20 is formed, and is patterned by using the photolithography technique to be removed from the p-well 5. When forming a MOS field effect transistor having a single drain structure, phosphorus or arsenic is ion-implanted in this state to form the n-type source / drain 21.

The acceleration energy of ion implantation is 10 to 20 KeV in the prior art so that the gate electrode 17 does not penetrate.
However, when the amorphous carbon film 29 is formed as in the present invention, about 20 KeV to 15
It can be increased up to about 0 KeV, and the selection range of acceleration energy is increased. In addition, since punch-through occurs stochastically, the probability can be lowered, which greatly contributes to the improvement of yield.

Referring to FIG. 2B, a resist film 18 is formed, and is patterned by using a photolithography technique to be removed from the n-well 7, and boron is ion-implanted to p-type source / drain 1.
9 is formed.

Referring to FIG. 2C, the amorphous carbon film 29 is removed to form an insulating film 30, which is patterned to form the source / drain 19.
21, a contact hole 31 is formed, an aluminum film is formed on the insulating film 30 including the inside of the contact hole 31, and then the aluminum film is patterned to form an n-type source / drain 21 and a p-type source / drain 19 respectively. An electrode 32 that contacts is formed. There is no problem if the amorphous carbon film 29 is left, but in this case, the step difference of the gate becomes large.

Second Example A case of manufacturing a CMOS field effect transistor having an LDD structure will be described.

See FIG. 3A. In the step shown in FIG. 2A of the first example, instead of the step of ion-implanting phosphorus or arsenic at a high concentration, the step shown in FIG.
As shown in FIG. 3, phosphorus or arsenic is ion-implanted at a low concentration to form an n-type low impurity concentration region (LDD) 23 in the n-channel transistor formation region.

See FIG. 3B. Using a CVD method, a silicon oxide insulating film is formed on the entire surface, and anisotropic etching is performed until the amorphous carbon film 29 is exposed to form sidewall insulation on the side wall of the gate electrode 17. The film 24 is formed. If a parallel plate type plasma etching device is used to irradiate and etch methane trifluoride gas plasma, the insulating film and the gate electrode 17 are etched.
Since the selection ratio with respect to the upper amorphous carbon film 29 is sufficiently large, the amorphous carbon film 29 is less thinned.

Referring to FIG. 3C, a resist film 25 having an opening is formed on the p-well 5, and the gate electrode 17, the amorphous carbon film 29 and the sidewall insulating film 24 on the p-well 5 are used as a mask to form arsenic. Are ion-implanted to form the n-type source / drain 26.

In the same manner, boron is ion-implanted into the n-well 7 to form the p-type source / drain 28, and then the amorphous carbon film 29 is formed by using a mixed solution of hydrogen peroxide solution and sulfuric acid. Peel off. Note that there is no problem if the amorphous carbon film 29 is left, but in that case, the step on the gate electrode 17 becomes large.

The following steps are the same as in the first example.

Third Example A case will be described in which a p-type gate electrode is formed on a p-channel transistor and an n-type gate electrode is formed on an n-channel transistor.

Refer to FIG. 5A. After the steps up to the step shown in FIG. 10A of the conventional example are performed, an amorphous carbon film 29 serving as an antireflection film is formed to 0.5 μm.
It is formed to a thickness. A resist film 14 is formed, and is patterned using a photolithography technique.
-Removing from above the well region 5. Next, phosphorus is ion-implanted to make the silicon layer 13 on the p-well 5 an n-type conductive layer. When phosphorus is ion-implanted at an acceleration energy of 70 to 100 KeV, the silicon layer 13 on the p-well 5 is
Phosphorus ions are implanted in the silicon layer 13 on the n-well 7 if the thickness of the resist film 14 is 0.4 μm or more.
Phosphorus ions are not implanted in the.

5B, the resist film 14 is peeled off, a new resist film 15 is formed, and the resist film 15 is patterned and removed from the n-well region 7. It is generally known that, when fluorine is introduced during ion implantation for forming a p-type gate electrode, boron easily penetrates through the silicon layer 13 and the flat band voltage V _fb increases. Therefore, only boron ion implantation is required, and the acceleration energy must be low. In order to ion-implant boron into the silicon layer 13 having a thickness of 1000 Å, it has conventionally been necessary to implant with acceleration energy of 15 KeV or less. On the other hand, as in the present invention, the amorphous carbon film 29 is formed on the silicon layer 13.
Is about 0.5 μm thick, 120
Ions can be implanted with an acceleration energy of about KeV, and the throughput is dramatically improved.

Even if boron is ion-implanted at an acceleration energy of about 120 KeV, the thickness of the resist film 15 is 0.5.
μm, and the thickness of the amorphous carbon film 29 is 0.5.
If the thickness is μm, boron is not ion-implanted into the silicon layer 13 on the p-well 5.

If the same steps as the steps shown in FIG. 1B of the first example are performed thereafter, the gate electrode of the p-channel transistor will be a p-type gate electrode and the gate electrode of the n-channel transistor will be a gate electrode. A CMOS field effect transistor having an n-type gate electrode is formed.

Fourth Example A case of patterning a gate electrode using a three-layer resist film will be described.

See FIG. 6A. After performing the steps shown in FIG. 10A of the conventional example, three layers of a resist film 33, an SOG film 34 and a resist film 35 are laminated to form an upper resist film 35. Pattern and p
-Removing from above the well region 5. Then, phosphorus is ion-implanted to make the silicon layer 13 in the p-well region 5 n-type.

Referring to FIG. 6B, the resist film 35 is removed, a new resist film 36 is formed, and the resist film 36 is patterned and removed from above the n-well region 7. Next, boron is ion-implanted to make the silicon layer 13 in the n-well region 7 p-type.

Referring to FIG. 6C, the resist film 36 is removed, a new resist film 37 is formed, and this is patterned to remain in the gate electrode forming region.

Referring to FIG. 7A, the SOG film 34, the resist film 33, and the silicon layer 13 are etched using the resist film 37 as a mask to leave the silicon layer 13 in the gate electrode formation region.

See FIG. 7B. In the same manner as the process of the first example shown in FIGS. 2A and 2B, the n-type source / drain 21 is formed in the p-well region 5, and n P-type source / drain 19 in the well region 7
To form.

See FIG. 2C. After removing the resist film 37, the SOG film 34, and the resist film 33, an insulating film 30 is formed in the same manner as in the process of the first example shown in FIG. A hole 31 is formed and an electrode 32 is formed in the contact hole 31.

[0063]

As described above, in the method of manufacturing a semiconductor device according to the present invention, impurities are ion-implanted into the semiconductor layer to reduce the resistance, and then an etching mask made of a multilayer resist film is formed on the semiconductor layer. In contrast to the conventional method of forming and patterning the semiconductor layer, the resistance of the semiconductor layer is reduced by ion-implanting with acceleration energy that penetrates at least one layer of the multilayer resist film in a state where the layer is formed. Therefore, the ion implantation can be performed with high acceleration energy, and the throughput is significantly improved.

If impurities are ion-implanted into the gate electrode of the MOS field effect transistor by using this method, even if the ions are implanted with high acceleration energy, the ions escape to the gate oxide film or the channel region and a flat band voltage is generated. If the ion implantation for forming the source / drain is carried out with at least one layer of the multi-layer resist film used when patterning the gate electrode being left on the gate electrode, high acceleration energy will not occur. Even if the ion implantation is performed, the ions do not channel the gate electrode and penetrate into the channel region to lower the threshold voltage, and a MOS field effect transistor having excellent characteristics can be manufactured.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a CMOS field effect transistor according to the present invention.

FIG. 2 is a manufacturing process diagram of a CMOS field effect transistor according to the present invention.

FIG. 3 is a manufacturing process diagram of a CMOS field effect transistor having an LDD structure according to the present invention.

FIG. 4 is a manufacturing process diagram of a CMOS field effect transistor having an LDD structure according to the present invention.

FIG. 5 is a manufacturing process diagram of a CMOS field effect transistor in which the gate electrodes of the p-channel transistor and the n-channel transistor have different conductivity types.

FIG. 6 is a manufacturing process diagram of a CMOS field effect transistor when a three-layer resist film is used.

FIG. 7 is a manufacturing process diagram of a CMOS field effect transistor when a three-layer resist film is used.

FIG. 8 is a manufacturing process diagram of a CMOS field effect transistor according to a conventional technique.

FIG. 9 is a manufacturing process diagram of a CMOS field effect transistor according to a conventional technique.

FIG. 10 is a manufacturing process diagram of a CMOS field effect transistor according to a conventional technique.

FIG. 11 is a manufacturing process diagram of a CMOS field effect transistor according to a conventional technique.

FIG. 12 is a manufacturing process diagram of a MOS field effect transistor having an LDD structure according to a conventional technique.

FIG. 13 is a graph showing a relationship between acceleration energy of ion implantation and processing time.

[Explanation of symbols]

1 Silicon substrate 2 Oxide film 3 Silicon nitride film 4/6/8/9/14/15/16/18/20/20
25.27.33.35.36.37 Resist film 5 p-well 7 n-well 10 Channel stop 11 Field oxide film 12 Gate oxide film 13 Silicon layer 17 Gate electrode 19.28 P-type source / drain 21.26 n-type source / drain 23 LDD region 24 Sidewall insulating film 29 Amorphous carbon film 30 Insulating film 31 Contact hole 32 Electrode 34 SOG film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical location H01L 21/027 21/8238 27/092 H01L 21/30 574 27/08 321 D 321 E

Claims (6)

[Claims] 1. A resistance of the semiconductor layer is reduced by ion-implanting impurities into the semiconductor layer with acceleration energy that penetrates the at least one layer in a state where at least one layer of a multilayer resist film is formed on the semiconductor layer. A method of manufacturing a semiconductor device, comprising the steps of: 2. A gate of a MOS field effect transistor by patterning a low resistance semiconductor layer manufactured by using the method for manufacturing a semiconductor device according to claim 1 by using an etching mask made of the multilayer resist film. A method of manufacturing a semiconductor device, comprising the step of forming an electrode. 3. A semiconductor device according to claim 2, wherein a gate electrode is formed on the semiconductor substrate, and at least one layer of an etching mask made of the multilayer resist film remains on the gate electrode. A method of manufacturing a semiconductor device, comprising a step of ion-implanting an impurity into a substrate to form a source / drain. 4. The multilayer resist film comprises two layers, the lower layer is an amorphous carbon film, and the upper layer is a normal resist film, or
3. The method for manufacturing a semiconductor device according to 3. 5. The multilayer resist film is composed of three layers, a lower layer is a planarizing resist film, an intermediate layer is a spin-on-glass (SOG) film, and an upper layer is a normal resist film. Item 4. A method of manufacturing a semiconductor device according to item 1, 2 or 3. 6. The multi-layered resist film comprises three layers, the lower layer is an amorphous carbon film, the intermediate layer is a spin-on-glass (SOG) film, and the upper layer is a normal resist film. 1. The method for manufacturing a semiconductor device according to 1, 2, or 3.