JPH088357A - Electronic device and manufacture thereof - Google Patents
Electronic device and manufacture thereofInfo
- Publication number
- JPH088357A JPH088357A JP6135543A JP13554394A JPH088357A JP H088357 A JPH088357 A JP H088357A JP 6135543 A JP6135543 A JP 6135543A JP 13554394 A JP13554394 A JP 13554394A JP H088357 A JPH088357 A JP H088357A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- chip
- hole
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基板の一方の面にチッ
プを搭載し、他方の面にバンプを形成する電子部品およ
び電子部品の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component in which a chip is mounted on one surface of a substrate and bumps are formed on the other surface, and a method of manufacturing the electronic component.
【０００２】[0002]
【従来の技術】電子部品を形成するための基板として、
基板の一方の面にチップを搭載し、この一方の面に形成
された電極と他方の面に形成されたランドをスルーホー
ルにより電気的に接続し、かつランドの表面にバンプ
（突出電極）を形成したものが知られている。このよう
な基板を用いた電子部品は、その小型化と高密度化が可
能になることから、近年、次第に普及する傾向にある。2. Description of the Related Art As a substrate for forming electronic parts,
The chip is mounted on one surface of the substrate, the electrodes formed on this one surface are electrically connected to the lands formed on the other surface by through holes, and bumps (protruding electrodes) are formed on the surface of the lands. What is formed is known. Since electronic components using such a substrate can be miniaturized and highly densified, in recent years, the electronic components tend to be widely used.
【０００３】上記のような基板として、米国特許第５２
１６２７８号明細書に記載されたものが知られている。
次に図６、図７、図８、図９を参照して、その構造を説
明する。図６は従来の電子部品の基板の上面図、図７は
同下面図であって、上記米国特許第５２１６２７８号明
細書の内容を判りやすく図示したものである。図６にお
いて、基板１の上面中央はチップが搭載されるアイラン
ド２になっており、このアイランド２の周囲に合計８個
の第２の電極３が形成されている。第２の電極３の外方
にはスルーホール４が形成されており、第２の電極３と
スルーホール４はリード５により接続されている。As the above substrate, US Pat. No. 52 is used.
The thing described in the 16278 specification is known.
Next, the structure will be described with reference to FIGS. 6, 7, 8 and 9. FIG. 6 is a top view of a substrate of a conventional electronic component, and FIG. 7 is a bottom view of the same, showing the contents of US Pat. No. 5,216,278 for easy understanding. In FIG. 6, the center of the upper surface of the substrate 1 is an island 2 on which chips are mounted, and a total of eight second electrodes 3 are formed around the island 2. A through hole 4 is formed outside the second electrode 3, and the second electrode 3 and the through hole 4 are connected by a lead 5.
【０００４】図７において、基板１の下面のスルーホー
ル４を含むエリアには小形の第３の電極６が形成されて
おり、また第３の電極６の側方にはランド７が形成され
ている。第３の電極６とランド７はリード８により接続
されている。In FIG. 7, a small third electrode 6 is formed in the area including the through hole 4 on the lower surface of the substrate 1, and a land 7 is formed on the side of the third electrode 6. There is. The third electrode 6 and the land 7 are connected by a lead 8.
【０００５】図８は図６および図７に示す基板１を用い
た従来の電子部品の断面図、図９は図８のＡ部分の部分
断面図である。基板１のアイランド２上にはチップ９が
搭載されており、またチップ９の上面の第１の電極と基
板１の上面の第２の電極３はワイヤ１０で接続されてい
る。またランド７の表面には、ハンダ材料によりバンプ
２０が形成されている。スルーホール４の内面には、基
板１の上面のリード５と基板１の下面の第３の電極６を
導通させるためにメッキ部２１が形成されている。Ｍは
チップ９を封止する合成樹脂である。FIG. 8 is a sectional view of a conventional electronic component using the substrate 1 shown in FIGS. 6 and 7, and FIG. 9 is a partial sectional view of a portion A of FIG. A chip 9 is mounted on the island 2 of the substrate 1, and a first electrode on the upper surface of the chip 9 and a second electrode 3 on the upper surface of the substrate 1 are connected by a wire 10. Bumps 20 are formed on the surface of the land 7 with a solder material. A plated portion 21 is formed on the inner surface of the through hole 4 to electrically connect the lead 5 on the upper surface of the substrate 1 and the third electrode 6 on the lower surface of the substrate 1. M is a synthetic resin that seals the chip 9.
【０００６】[0006]
【発明が解決しようとする課題】電子部品の小型化・高
密度化を向上させるためには、第２の電極３およびラン
ド７はより多く形成する必要がある。ここで、第２の電
極３はチップ９の第１の電極とワイヤ１０で接続するた
めのものであり、したがって小形でよいものであるが、
ランド７はその表面にバンプ２０が形成されるものであ
り、したがって図示するようにランド７は第２の電極３
よりもかなり大形に形成される。In order to improve the miniaturization and high density of electronic parts, it is necessary to form more second electrodes 3 and lands 7. Here, the second electrode 3 is for connecting to the first electrode of the chip 9 by the wire 10, and therefore may be small in size.
The bumps 20 are formed on the surface of the land 7, and therefore the land 7 is formed on the second electrode 3 as shown in the figure.
It is much larger than
【０００７】このように第２の電極３は小形であるた
め、その配置は比較的自由に設定されるが、ランド７は
大形であるため、その配置設計の自由度は電極３のそれ
よりもかなり小さいものである。しかも上記従来のもの
は、図７に示すように、ランド７は第３の電極６とは分
離して別体で形成されており、両者をリード８で接続す
る構造となっていたため、１個のランド７を形成するた
めに必要を面積Ｓ１は相当大きくなり、したがってラン
ド７の配置設計の自由度が益々制限されるとともに、ラ
ンド７の総数も制限され、ひいては図８に示す電子部品
の小型化・高密度化が困難になるという問題点があっ
た。As described above, since the second electrode 3 is small, its layout can be set relatively freely, but since the land 7 is large, the degree of freedom in its layout design is higher than that of the electrode 3. Is also quite small. Moreover, in the above-mentioned conventional one, as shown in FIG. 7, the land 7 is formed separately from the third electrode 6 and has a structure in which both are connected by the lead 8. The area S1 required to form the land 7 is considerably large, and thus the degree of freedom in the layout design of the land 7 is further limited, and the total number of the lands 7 is also limited. There was a problem that it was difficult to achieve high density and high density.
【０００８】そこで本発明は、ランドを形成するために
必要な面積を小さくし、より一層の電子部品の小型化・
高密度化を図れる電子部品および電子部品の製造方法を
提供することを目的とする。In view of the above, the present invention reduces the area required for forming lands to further reduce the size of electronic parts.
An object of the present invention is to provide an electronic component and a method of manufacturing the electronic component that can achieve high density.
【０００９】[0009]
【課題を解決するための手段】表面に第１の電極を備え
たチップと、このチップが搭載される基板の一方の面に
形成されて、このチップの電極と電気的に接続された第
２の電極と、この第２の電極から離れた位置に形成され
てこの基板の一方の面と他方の面を導通させるスルーホ
ールと、この第２の電極とこのスルーホールを接続する
リードと、この基板の他方の面のスルーホールを含むエ
リアに形成されてその表面にバンプが形成されるランド
と、少なくともチップ及び第２の電極を封止する合成樹
脂とから電子部品を構成したものである。A chip having a first electrode on its surface, and a second chip formed on one surface of a substrate on which the chip is mounted and electrically connected to an electrode of the chip. Electrode, a through hole formed at a position distant from the second electrode and electrically connecting one surface and the other surface of the substrate, a lead connecting the second electrode and the through hole, An electronic component is composed of a land formed in an area including a through hole on the other surface of a substrate and having a bump formed on the surface thereof, and a synthetic resin that seals at least a chip and a second electrode.
【００１０】[0010]
【作用】上記電子部品によれば、図７に示す従来の第３
の電極およびリードは不要となるので、ランドを形成す
るために必要な面積を小さくできる。また上記電子部品
の製造方法によれば、ランドの表面に所定寸法のバンプ
を容易に形成できる。According to the electronic component described above, the third conventional device shown in FIG.
Since the electrode and the lead are unnecessary, the area required for forming the land can be reduced. Further, according to the method of manufacturing an electronic component, bumps having a predetermined size can be easily formed on the surface of the land.
【００１１】[0011]
【実施例】次に、図面を参照しながら本発明の一実施例
を説明する。図１は本発明の一実施例の電子部品の基板
の上面図、図２は同下面図である。各図において、図６
および図７に示す従来例と同じものには同一符号を付し
ている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the drawings. FIG. 1 is a top view of a substrate of an electronic component of one embodiment of the present invention, and FIG. 2 is a bottom view of the same. In each figure,
The same parts as those in the conventional example shown in FIG. 7 are designated by the same reference numerals.
【００１２】図１において、基板１の上面（第１の面）
中央はチップが搭載されるアイランド２になっており、
このアイランド２の周囲に合計８個の第２の電極３が形
成されている。第２の電極３から離れた位置には基板の
上面から下面（第２の面）へ貫通するスルーホール４が
形成されており、第２の電極３とスルーホール４はリー
ド５により接続されている。In FIG. 1, the upper surface (first surface) of the substrate 1
In the center is Island 2 where chips are mounted,
A total of eight second electrodes 3 are formed around the island 2. A through hole 4 penetrating from the upper surface to the lower surface (second surface) of the substrate is formed at a position apart from the second electrode 3, and the second electrode 3 and the through hole 4 are connected by a lead 5. There is.
【００１３】図２において、バンプ形成基板１の下面の
スルーホール４を含むエリアにはランド７が形成されて
いる。スルーホール４はランド７のセンターに位置して
いる。このようにスルーホール４を含むエリアにランド
７を形成することにより、図７に示す第３の電極６やリ
ード８を不要にし、ランド７を形成するのに必要な面積
Ｓ２を従来の面積Ｓ１よりも小さくでき、この面積Ｓ２
を小さくすることにより、ランド７の配置設計の自由度
を大きくするとともに、その総数をより多くすることが
できる。In FIG. 2, a land 7 is formed in the area including the through hole 4 on the lower surface of the bump forming substrate 1. The through hole 4 is located at the center of the land 7. By forming the land 7 in the area including the through hole 4 in this manner, the third electrode 6 and the lead 8 shown in FIG. 7 are unnecessary, and the area S2 required to form the land 7 is reduced to the conventional area S1. Can be made smaller than this area S2
It is possible to increase the degree of freedom in designing the layout of the lands 7 and increase the total number thereof by decreasing the value.
【００１４】次に基板１の製造方法を説明する。図３
（ａ），（ｂ），（ｃ），（ｄ）は本発明の一実施例の
電子部品の製造工程における部分断面図である。まず、
基板１の上面から下面へ貫通するスルーホール４を形成
する。その後図３（ａ）に示すように、スルーホール４
の内面を含む基板１の表面に第１メッキ部１１を薄く形
成する。次に図３（ｂ）に示すようにスルーホール４の
内部に導電ペースト１２を充填する。本実施例の導電ペ
ースト１２は、ペースト状樹脂に導電粉を混入したもの
であり、スクリーン印刷手段などにより充填される。Next, a method of manufacturing the substrate 1 will be described. FIG.
(A), (b), (c), (d) is a fragmentary sectional view in the manufacturing process of the electronic component of one Example of this invention. First,
A through hole 4 penetrating from the upper surface to the lower surface of the substrate 1 is formed. After that, as shown in FIG.
The first plated portion 11 is thinly formed on the surface of the substrate 1 including the inner surface of. Next, as shown in FIG. 3B, the conductive paste 12 is filled in the through holes 4. The conductive paste 12 of this embodiment is a paste resin mixed with conductive powder, and is filled by a screen printing means or the like.
【００１５】次にこの導電ペースト１２を硬化させた
後、基板１の表面に第２メッキ部５’，７’を薄く形成
する（図３（ｃ））。次に第２メッキ部５’，７’の不
必要部分をエッチッグ法により除去して、第２の電極
３、リード５、ランド７などの回路パターンを形成する
（図３（ｄ））。このように本方法によれば、基板１を
作業性よく簡単に製造することができる。Next, after the conductive paste 12 is hardened, second plated portions 5'and 7'are thinly formed on the surface of the substrate 1 (FIG. 3C). Then, unnecessary portions of the second plated portions 5'and 7'are removed by an etching method to form a circuit pattern such as the second electrode 3, leads 5 and lands 7 (FIG. 3 (d)). Thus, according to this method, the substrate 1 can be easily manufactured with good workability.
【００１６】次にランド７上にバンプを形成する方法に
ついて説明する。図４は本発明の一実施例のバンプ形成
方法の説明図である。図中、１４は基板１の表面の回路
パターン以外の部分にコーティングされたレジスト膜で
ある。図示するように、図３（ｂ），（ｃ）の工程にお
いて導電ペースト１２が硬化する際に硬化収縮すること
により、ランド７の中央部には凹部１５が生じている。Next, a method of forming bumps on the land 7 will be described. FIG. 4 is an explanatory diagram of a bump forming method according to an embodiment of the present invention. In the figure, 14 is a resist film coated on a portion of the surface of the substrate 1 other than the circuit pattern. As illustrated, the conductive paste 12 is cured and shrunk when the conductive paste 12 is cured in the steps of FIGS. 3B and 3C, so that a recess 15 is formed in the central portion of the land 7.
【００１７】そこで図４に示すように、ランド７上にフ
ラックス（図示せず）を塗布した後、凹部１５上に半田
ボール２０’を搭載し、次いでこのバンプ形成基板１を
加熱炉で加熱する。すると半田ボール２０’は溶融して
自身の表面張力により略半球形となり、次いで硬化する
ことによりバンプ２０が完成する。上記工程において、
ランド７の中央部には凹部１５が生じているので、半田
ボール２０’をこの凹部１５上にしっかり位置決めして
搭載し、バンプ２０を形成することができる。またこの
凹部１５により、溶融した半田ボール２０’をしっかり
接着させることができる。Therefore, as shown in FIG. 4, after applying a flux (not shown) on the land 7, a solder ball 20 'is mounted on the recess 15 and then the bump forming substrate 1 is heated in a heating furnace. . Then, the solder balls 20 ′ are melted to have a substantially hemispherical shape due to the surface tension of the solder balls 20 ′ and then hardened to complete the bumps 20. In the above process,
Since the recess 15 is formed at the center of the land 7, the solder ball 20 ′ can be firmly positioned and mounted on the recess 15 to form the bump 20. Further, the recess 15 allows the melted solder ball 20 'to be firmly adhered.
【００１８】なおバンプの形成方法は本実施例に限定さ
れないのであって、例えばスクリーン印刷手段により適
量のペースト状半田をランド７上に塗布し、塗布された
ペースト状半田を加熱炉で加熱して溶融させることによ
り、自身の表面張力で半球形のバンプを形成してもよい
ものである。この場合も、ランド７の中央部には凹部１
５が生じているので、スクリーン印刷手段によりペース
ト状半田をしっかり付着させることができる。The method of forming the bumps is not limited to this embodiment. For example, an appropriate amount of paste-like solder is applied to the land 7 by screen printing means, and the applied paste-like solder is heated in a heating furnace. By melting, a hemispherical bump may be formed by its own surface tension. Also in this case, the recess 1 is formed in the center of the land 7.
5, the paste-like solder can be firmly attached by the screen printing means.
【００１９】図５は、本発明の一実施例の電子部品の一
部切欠斜視図である。この電子部品３０は、上記のよう
にして製造された基板１を用いて製造されたものであ
る。アイランド２上にはチップ９が搭載されており、チ
ップ９の上面の第１の電極３２とバンプ形成基板１の第
２の電極３は導電性のワイヤ１０により接続されてい
る。またチップ９やワイヤ１０を保護するための合成樹
脂モールド体３１がこれらを覆うように形成されてい
る。チップ９の基板１への搭載、ワイヤ１０の接続、合
成樹脂モールド体３１によるチップ９の封止工程は、バ
ンプ形成工程の前に行なわれる。この電子部品３０は、
その下面のバンプ２０を主基板（図外）の電極に接続し
て搭載される。本発明は、上記実施例に限定されないの
であって、例えば上記チップ９に代えてフリップチップ
ＴＡＢ工法で供給されるＴＣＰ部品を搭載してもよいも
のである。フリップチップの場合、ワイヤ１０による接
続は不要であって、フリップチップのバンプは、バンプ
形成基板１の第２の電極３に直接接続される。FIG. 5 is a partially cutaway perspective view of an electronic component according to an embodiment of the present invention. The electronic component 30 is manufactured using the substrate 1 manufactured as described above. A chip 9 is mounted on the island 2, and the first electrode 32 on the upper surface of the chip 9 and the second electrode 3 of the bump forming substrate 1 are connected by a conductive wire 10. Further, a synthetic resin mold body 31 for protecting the chip 9 and the wire 10 is formed so as to cover them. The steps of mounting the chip 9 on the substrate 1, connecting the wires 10, and sealing the chip 9 with the synthetic resin molded body 31 are performed before the bump forming step. This electronic component 30
The bumps 20 on the lower surface are connected to the electrodes of the main substrate (not shown) and mounted. The present invention is not limited to the above embodiment, and for example, the chip 9 may be replaced with a TCP component supplied by the flip chip TAB method. In the case of a flip chip, the connection by the wire 10 is unnecessary, and the bump of the flip chip is directly connected to the second electrode 3 of the bump forming substrate 1.
【００２０】[0020]
【発明の効果】以上説明したように本発明のバンプ形成
基板によれば、ランドを形成するのに必要な面積を小さ
くでき、したがってランドの配置設計の自由度を大きく
し、またランドの総数により多くして、電子部品の小型
化・高密度化を向上させることができる。As described above, according to the bump forming substrate of the present invention, the area required for forming the land can be reduced, so that the degree of freedom in land layout design can be increased and the total number of lands can be changed. By increasing the number, it is possible to improve the miniaturization and high density of electronic components.
【００２１】また本発明のバンプ形成基板の製造方法に
よれば、ランド上にバンプを簡単・確実に形成すること
ができる。Further, according to the method of manufacturing a bump-formed substrate of the present invention, bumps can be easily and surely formed on the land.
【図１】本発明の一実施例の電子部品の基板の上面図FIG. 1 is a top view of a substrate of an electronic component according to an embodiment of the present invention.
【図２】本発明の一実施例の電子部品の基板の下面図FIG. 2 is a bottom view of a substrate of an electronic component according to an embodiment of the present invention.
【図３】（ａ）本発明の一実施例の電子部品の製造工程
における部分断面図 （ｂ）本発明の一実施例の電子部品の製造工程における
部分断面図 （ｃ）本発明の一実施例の電子部品の製造工程における
部分断面図 （ｄ）本発明の一実施例の電子部品の製造工程における
部分断面図3A is a partial sectional view in a manufacturing process of an electronic component according to an embodiment of the present invention. FIG. 3B is a partial sectional view in a manufacturing process of an electronic component according to an embodiment of the present invention. Partial cross-sectional view in the manufacturing process of the example electronic component (d) Partial cross-sectional view in the manufacturing process of the electronic component of one embodiment of the present invention
【図４】本発明の一実施例のバンプ形成方法の説明図FIG. 4 is an explanatory diagram of a bump forming method according to an embodiment of the present invention.
【図５】本発明の一実施例の電子部品の一部切欠斜視図FIG. 5 is a partially cutaway perspective view of an electronic component according to an embodiment of the present invention.
【図６】従来の電子部品の基板の上面図FIG. 6 is a top view of a board of a conventional electronic component.
【図７】従来の電子部品の基板の下面図FIG. 7 is a bottom view of a board of a conventional electronic component.
【図８】従来の電子部品の断面図FIG. 8 is a sectional view of a conventional electronic component.
【図９】従来の電子部品の部分断面図FIG. 9 is a partial sectional view of a conventional electronic component.
１ バンプ形成基板 ２ アイランド ３ 電極 ４ スルーホール ５ リード ７ ランド １１ 第１メッキ部 １２ 導電ペースト １５ 凹部 ２０’ 半田ボール ２０ バンプ 1 Bump Formed Substrate 2 Island 3 Electrode 4 Through Hole 5 Lead 7 Land 11 First Plated Part 12 Conductive Paste 15 Recess 20 'Solder Ball 20 Bump
Claims (2)
チップが搭載される基板の一方の面に形成されて、この
チップの電極と電気的に接続された第２の電極と、この
第２の電極から離れた位置に形成されてこの基板の一方
の面と他方の面を導通させるスルーホールと、この第２
の電極とこのスルーホールを接続するリードと、この基
板の他方の面の前記スルーホールを含むエリアに形成さ
れてその表面にバンプが形成されるランドと、少なくと
も前記チップ及び第２の電極を封止する合成樹脂を有す
ることを特徴とする電子部品。1. A chip having a first electrode on a surface thereof, and a second electrode formed on one surface of a substrate on which the chip is mounted and electrically connected to an electrode of the chip. A through hole formed at a position distant from the second electrode for electrically connecting one surface and the other surface of the substrate;
A lead connecting the electrode and the through hole, a land formed on the other surface of the substrate including the through hole and having a bump formed on the surface thereof, and at least the chip and the second electrode are sealed. An electronic component having a synthetic resin that stops.
及び第２の面上に第１メッキ部を形成する工程と、 前記スルーホールの内部に、導電ペーストを充填し、こ
の導電ペーストを硬化させる工程と、 前記第１メッキ部を選択的に除去することにより、前記
第１の面に第２の電極及びこの第２の電極と前記スルー
ホールを接続するリードと、前記第２の面に、前記スル
ーホールを覆うランドとを形成する工程と、 前記第１の面にチップを搭載してチップの第１の電極
と、前記第２の電極を電気的に接続する工程と、 少なくとも前記チップ及び第２の電極の表面を合成樹脂
で封止する工程と、 前記導電ペーストが硬化することにより生じた凹部上に
バンプを形成する工程と、 を含むことを特徴とする電子部品の製造方法。2. A step of forming a first plated portion on a first surface and a second surface of a substrate on which a through hole is formed, and a conductive paste is filled inside the through hole, and the conductive paste is formed. And a lead for connecting the second electrode and the through hole to the first surface by selectively removing the first plated portion, and the second Forming a land on the surface to cover the through hole; mounting a chip on the first surface to electrically connect the first electrode of the chip to the second electrode; Manufacturing an electronic component comprising: a step of sealing the surfaces of the chip and the second electrode with a synthetic resin; and a step of forming a bump on a recess formed by curing the conductive paste. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06135543A JP3104527B2 (en) | 1994-06-17 | 1994-06-17 | Electronic component and method of manufacturing electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06135543A JP3104527B2 (en) | 1994-06-17 | 1994-06-17 | Electronic component and method of manufacturing electronic component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH088357A true JPH088357A (en) | 1996-01-12 |
| JP3104527B2 JP3104527B2 (en) | 2000-10-30 |
Family
ID=15154245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06135543A Expired - Fee Related JP3104527B2 (en) | 1994-06-17 | 1994-06-17 | Electronic component and method of manufacturing electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3104527B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990000382A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | Lead frame, chip scale package using same and manufacturing method thereof |
-
1994
- 1994-06-17 JP JP06135543A patent/JP3104527B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990000382A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | Lead frame, chip scale package using same and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3104527B2 (en) | 2000-10-30 |
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