JPH0879062A - Phase comparator and pll circuit - Google Patents

Abstract

PURPOSE: To obtain the phase comparator immune to external disturbance with a wide phase comparison range whose phase comparison characteristic is linear by providing a phase difference detection means providing an output of a phase lag signal and a phase lead signal, a lead lag discrimination means and a signal selection means to the phase comparator. CONSTITUTION: A phase difference detection section 18 having MO storage element such as a latch and a lead lag discrimination circuit 23 having an RS flip-flop as a storage element are connected to input sections 16, 17 receiving a reference signal R and a variation signal V. The phase difference detection section 18 provides an output of a phase lag signal U(=R + the inverse of V) and a phase lead signal D(=The inverse of R+V) as a phase difference between the reference signal R and the variation signal V simultaneously. The flip-flop of the lead lag discrimination circuit 23 is set when both the reference signal R and the variation signal V are inverted and reset when the both are not inverted. The result is outputted to a control input of a switching device 19 as a discrimination signal Q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase comparator and a PLL.
(Phase Locked Loop) circuit.

[0002]

2. Description of the Related Art A conventional phase comparator detects a phase difference by comparing a fluctuation signal with a reference signal and detects the phase difference when the phase of the fluctuation signal is ahead of the phase of the reference signal. And the phase difference when the phase of the fluctuation signal is delayed with respect to the phase of the reference signal is output as a phase delay signal.

Further, a PLL circuit formed by using such a phase comparator inputs the output of the phase comparator to a voltage controlled oscillator and feeds back the output of the voltage controlled oscillator to the phase comparator. Has become. By doing so, the frequency of the output signal of the voltage controlled oscillator is synchronized with the frequency of the input signal of the phase comparator.

The phase comparator as described above is classified into a memory type having a storage element and a non-memory type having no storage element. The memory type phase comparator has a wide range in which the phase can be compared characteristically from “−2π to + 2π”. However, when the comparison operation becomes unstable due to disturbance, this unstable state is caused for a long time by the memory element. continue. On the other hand, in the non-memory type phase comparator, even if the operation becomes unstable due to the disturbance, the unstable state ends early because there is no storage element, but the range in which the phases can be compared is “−π / 2 to + π”. It is as narrow as / 2 ".

That is, the PLL circuit using the memory type phase comparator can be synchronized even in the state where the phase difference of the signal frequencies is large, but if the synchronization is lost due to the disturbance, the unstable state becomes long. Further, in a PLL circuit using a non-memory type phase comparator, it is difficult to synchronize from a state in which the phase difference of the signal frequency is large, and therefore a special control for switching and switching the detection region of the phase comparator is performed. is necessary.

A PLL circuit that solves the above problems is disclosed in Japanese Patent Laid-Open No. 2-70124. Therefore,
The PLL circuit disclosed in this publication is shown in FIG.
It will be described below based on. First, this PLL circuit 1
The reference signal input section 2 is connected to the memory type phase comparator 3 and is also connected to the non-memory type phase comparator 5 via the delay element 4. The outputs of these phase comparators 3 and 5 are the switching circuits 6 that select them.
Is input to the voltage controlled oscillator 7 via, and the output of the voltage controlled oscillator 7 is input to the output unit 8 and the phase comparators 3 and 5. The switching circuit 6 is connected to a switching signal input section 9 for instructing switching of the phase comparators 3 and 5.

With the structure as described above, the output of the memory type phase comparator 3 is selected by the switching circuit 6 in the initial state, and when the synchronization acquisition is completed by this phase comparator 3, the switching circuit 6 causes the phase comparator 5 to operate. select.

By doing so, in the initial state where the phase difference between the signal frequencies is large, the memory type phase comparator 3 having a wide phase comparison range is selected, so that the synchronization acquisition is easy, and after the completion of the synchronization acquisition. , The non-memory type phase comparator 5 that is strong against disturbance is selected, so that the operation is stable.

[0009]

The PLL circuit 1 of the above publication uses memory type and non-memory type phase comparators 3 and 5 properly.

However, since the memory type and non-memory type phase comparators 3 and 5 have different output characteristics, the operation of the PLL circuit 1 becomes unstable because the output voltage difference is high if these are simply switched. . Therefore, P disclosed in the above publication
The LL circuit 1 uses the delay element 4 and the like to match the characteristics of the non-memory type phase comparator 5 with the characteristics of the memory type phase comparator 3.

A more detailed description will be given. First, since the contents of the phase comparators 3 and 5 are not disclosed in the above-mentioned publication, supplementing the contents as general contents, as shown in FIG. Of the charge pump 11 and the LPF (Low Pass Filter)
r) 12 is connected, and the non-memory type phase comparator 5 has a structure in which the LPF 14 is connected to the non-memory type phase comparison unit 13.

When the phase comparator 13 of the non-memory type phase comparator 5 is an EX (EXCLUSIVE) -OR type, FIG.
As illustrated in FIG. 8, the output of the phase comparison unit 13 is a rectangular pulse of the difference signal between the reference signal R and the fluctuation signal V. Therefore, when this is converted into a voltage by an LPF or an integrating circuit (both not shown) as indicated by the broken line in the figure, this is the phase difference between the reference signal and the fluctuation signal, as illustrated in FIG. 19A. When the phase difference is "± π", it becomes maximum, and when the phase difference is "0", it becomes "0".

However, in this case, the operation of the phase comparator 5 becomes unstable when the phase difference is "0", so that FIG.
As illustrated in FIG. 19, the offset voltage is applied so that it becomes “0” when the phase difference is “± π / 2”.
As illustrated in (c), the phase difference is "π /
When shifted by 2 ″, the characteristics of the phase comparator 5 match the characteristics of the phase comparator 3.

That is, the PLL disclosed in the above publication.
Even if the delay element 4 of the circuit 1 matches the characteristics of the non-memory type phase comparator 5 with the characteristics of the memory type phase comparator 3 as described above and switches the phase comparators 3 and 5 by the switching circuit 6, This is for stably operating the PLL circuit 1.
Further, in order to operate the PLL circuit 1 favorably, the charge pump 11 and the LPF 12 of the memory type phase comparator 3 are used.
2 and the gain of the LPF 14 of the non-memory type phase comparator 5 need to match, and the delay time of the delay element 4 also needs to match the cycle of the reference signal.

For this reason, the PLL circuit 1 of the above publication uses the memory type phase comparator 3 having a wide phase comparison range and the non-memory type phase comparator 5 which is strong against disturbance, but the phase comparison is actually performed. It is difficult to match the output characteristics of the devices 3 and 5, and the productivity is poor. Further, as described above, since the delay time of the delay element 4 needs to match the cycle of the reference signal, it is impossible to deal with the case where the cycle of the reference signal changes.

That is, in the non-memory type phase comparator 5, the unstable state ends early because there is no storage element, but the range in which the phases can be compared is narrow as "-π / 2 to + π / 2", and the memory is Since the phase comparator 3 has different output characteristics, it is difficult to switch and use the phase comparators 3 and 5.

[0017]

According to the first aspect of the present invention,
The fluctuation signal is compared with the reference signal to detect the phase difference, and the phase difference when the phase of the fluctuation signal is ahead of the phase of the reference signal is output as a phase lead signal, which fluctuates with respect to the phase of the reference signal. In a phase comparator that outputs a phase difference when the phases of signals are delayed as a phase delay signal, a phase difference detection unit that outputs a phase delay signal and a phase advance signal is provided without a storage element, and the storage element is A lead / lag discriminating means for discriminating the lead / lag of the fluctuation signal with respect to the reference signal is provided, and when the lead / lag discriminating means judges the lead of the fluctuation signal, the phase lead signal is selected, and when the delay of the fluctuation signal is discriminated, the phase delay A signal selecting means for selecting a signal is provided.

According to a second aspect of the present invention, when the reference signal is R, the fluctuation signal is V, the phase delay signal is U, and the phase lead signal is D in the first aspect of the invention, U = R + inversion V The relationship of D = inversion R + V is satisfied.

The term "reversal" described in the above equation means
It is a code representation of the overline of the logical NOT symbol.

According to a third aspect of the present invention, in the invention according to the first aspect, the lead / lag determination means is set when both the reference signal and the fluctuation signal are inverted, and both the reference signal and the fluctuation signal are not inverted. It has an RS-flip-flop that is reset.

According to a fourth aspect of the present invention, in the first aspect of the invention, the reference signal and the fluctuation signal are logic signals having the same pulse width and a duty ratio of 50 (%).

According to a fifth aspect of the invention, a memory type phase comparator having a storage element, a non-memory type phase comparator having no storage element, and a comparator switching for selecting one of these phase comparators. Means, and this comparator switching means,
In the PLL circuit in which the memory type phase comparator is selected before the completion of the synchronization acquisition and the non-memory type phase comparator is selected after the completion of the synchronization acquisition, the non-memory type phase comparator is replaced by a storage element. Phase difference detecting means for outputting a phase lag signal and a phase lead signal without having, a lead lag discriminating means for discriminating the lead or lag of the fluctuation signal with respect to the reference signal with a storage element, and the lead lag discriminating means. The phase lead signal is selected when the advance of the fluctuation signal is discriminated, and the phase delay signal is selected when the delay of the fluctuation signal is discriminated.

According to a sixth aspect of the present invention, the output of the phase comparator is input to the motor driver, and the rotation speed of the drive motor driven by this motor driver is detected by the speed detecting means.
An output of the speed detecting means is fed back to the phase comparator as a fluctuation signal to control the rotation of the drive motor, and a phase delay signal and a phase advance signal are output without a storage element. A phase difference detecting means, a lead / lag determining means having a storage element for discriminating the lead / lag of the fluctuation signal with respect to the reference signal, and a phase lead signal is selected when the lead / lag judging means discriminates the lead of the fluctuation signal, and the fluctuation With the signal selection means for selecting the phase delay signal when the signal delay is discriminated, a non-memory type phase comparator having no storage element is formed, and the non-memory type phase comparator,
A memory type phase comparator having a storage element, and a comparator switching means for selecting the memory type phase comparator before the completion of the synchronization acquisition and selecting the non-memory type phase comparator after the completion of the synchronization acquisition. And.

[0024]

According to the invention described in claim 1, the phase difference detecting means having no memory element outputs the phase lead signal and the phase delay signal, so that the unstable state of the phase difference detection due to the disturbance is terminated early, and When the lead / lag determining means having a storage element determines the lead of the fluctuation signal with respect to the reference signal, the signal selecting means selects the phase lead signal, and the lead / lag determining means having the storage element determines the delay of the fluctuation signal with respect to the reference signal. Since the signal selecting means selects the phase delay signal, the phase comparison range is wide and the output characteristic is equivalent to that of the memory type phase comparator.

According to the second aspect of the present invention, the phase lag signal U is R + inversion V and the phase advance signal D is inversion R + V with respect to the reference signal R and the fluctuation signal V. Therefore, the phase difference detection without the storage element is performed. The logical output form of the phase delay signal and the phase lead signal output by the means is equivalent to that of the memory type phase comparator.

According to the third aspect of the present invention, the RS-flip-flop included in the lead / lag determining means is set when both the reference signal and the fluctuation signal are inverted, and is reset when both the reference signal and the fluctuation signal are not inverted. Therefore, it is possible to output a signal corresponding to the fluctuation signal delayed from the reference signal or the reference signal delayed from the fluctuation signal.

Since the reference signal and the fluctuation signal are logical signals having the same pulse width and a duty ratio of 50 (%), the phase difference between the phase delay signal and the phase advance signal is the phase difference. Is always output satisfactorily.

According to a fifth aspect of the present invention, the PLL circuit selects the memory type phase comparator before completion of the synchronization acquisition and selects the non-memory type phase comparator after completion of the synchronization acquisition.
In this non-memory type phase comparator, since the phase difference detection means having no storage element outputs the phase advance signal and the phase delay signal, the unstable state of the phase difference detection due to the disturbance ends early, and further, The signal is selected when the lead / lag determining means having a storage element determines the lead of the fluctuation signal with respect to the reference signal, the signal selecting means selects the phase lead signal, and the lead / lag determining means having the storage element determines the delay of the fluctuation signal with respect to the reference signal. Since the selection means selects the phase delay signal, the phase comparison range is wide and the output characteristic is equivalent to that of the memory type phase comparator.

According to a sixth aspect of the present invention, the output of the phase comparator is input to the motor driver, and the rotation speed of the drive motor driven by this motor driver is detected by the speed detecting means.
A PLL circuit that feeds back the output of the speed detecting means to the phase comparator as a fluctuation signal selects a memory type phase comparator before the completion of the synchronization acquisition and a non-memory type phase comparator after the completion of the synchronization acquisition. When this is selected, in this non-memory type phase comparator, the phase difference detection means having no storage element outputs the phase lead signal and the phase delay signal, so that the unstable state of the phase difference detection due to the disturbance ends early. Further, when the lead / lag discriminating means having the memory element discriminates the lead of the fluctuation signal with respect to the reference signal, the signal selecting means selects the phase lead signal, and the lead / lag discriminating means having the memory element delays the fluctuation signal with respect to the reference signal. When the determination is made, the signal selection means selects the phase delay signal, so that the phase comparison range is wide and the output characteristic is equivalent to that of the memory type phase comparator.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. First, the phase comparator 1 of the present embodiment
5 is a reference signal R and a fluctuation signal V, as illustrated in FIG.
A phase difference detection unit 18, which is a phase difference detection unit having no storage element such as a latch, is connected to the input units 16 and 17 for receiving the reference signal R and the fluctuation signal V. The phase delay signal U and the phase advance signal D, which are simultaneously output as the phase difference, are output to the output units 20 and 21 via the switching device 19 which is the signal selecting means.

A lead / lag discriminating circuit 23, which is a lead / lag discriminating means having an RS-flip-flop 22 as the memory element, is also connected to the input sections 16 and 17 for the reference signal R and the fluctuation signal V. The discrimination signal Q output from the lead / lag determination circuit 23 is output to the control terminal of the switching device 19.

Here, as illustrated in FIG. 2, the phase difference detector 18 receives the reference signal R directly and the fluctuation signal V through the inverter 24 to output the phase delay signal U. And a NAND gate 27 to which the reference signal R is input via the inverter 26 and the fluctuation signal V is directly input to output the phase advance signal D. Therefore, when the reference signal is R, the fluctuation signal is V, the phase delay signal is U, and the phase lead signal is D, the phase difference detection unit 18 satisfies the relationship of U = R + inversion V D = inversion R + V. It is like this.

Further, the lead / lag decision circuit 23 is provided with a circuit shown in FIG.
And an AND gate 28 to which both the reference signal R and the fluctuation signal V are directly input, and an AND gate 31 to which the reference signal R and the fluctuation signal V are both input via the inverters 29 and 30. , These AND gates 28, 3
RS- which receives the output of 1 and outputs the discrimination signal Q
And a flip-flop 22. Therefore, the RS flip-flop 22 is set when both the reference signal R and the fluctuation signal V are inverted, and is reset when both the reference signal R and the fluctuation signal V are not inverted.

Further, in the switching device 19, for example, an OR gate (not shown) to which the phase delay signal U and the discrimination signal Q are input, and an OR gate (to which the phase advance signal D and the discrimination signal Q are input are shown. (Not shown).

The reference signal R and the fluctuation signal V are logic signals having the same pulse width and a duty ratio of 50 (%).

In such a configuration, the phase comparator 15
When the fluctuation signal V and the reference signal R are input to the phase difference detector 18, the phase difference detection unit 18 causes the phase delay signal U ′, which is a phase difference in which the fluctuation signal V is delayed from the reference signal R, and the fluctuation signal V from the reference signal R.
And a phase lead signal D ', which is the phase difference that has advanced, are output to the input gate of the switching device 19 together as U' = R + inversion V D '= inversion R + V.

At the same time, since the fluctuation signal V and the reference signal R are input to the lead / lag determination circuit 23, the RS-flip-flop 22 of this lead / lag determination circuit 23 is operated by the reference signal R.
Is set when both the reference signal R and the fluctuation signal V are inverted, and is reset when both the reference signal R and the fluctuation signal V are not inverted.
Output to the control input of.

Therefore, the switching device 19 cuts off one of the phase delay signal U'and the phase advance signal D'output from the phase difference detector 18 in accordance with the determination signal Q output from the advance / delay determination circuit 23 and the other. As shown in FIG.
As illustrated in (a), when the fluctuation signal V is delayed from the reference signal R, the phase advance signal D ′ is cut off and the phase delay signal U ′ is output as the formal phase delay signal U,
As illustrated in FIG. 4B, when the fluctuation signal V leads the reference signal R, the phase lag signal U ′ is cut off and the phase lead signal D ′ is output as the formal phase lead signal D. .

By doing so, like the conventional phase comparators 3, 5, etc., the phase difference in which the fluctuation signal V leads the reference signal R can be output as the phase lead signal D,
The phase difference in which the fluctuation signal V is delayed from the reference signal R can be output as the phase delay signal U.

Therefore, the phase delay signal U and the phase lead signal D selectively output by the phase comparator 15 in this manner are converted into analog voltages by, for example, a charge pump (not shown) and filtered by the LPF. Then, the output characteristic becomes as illustrated in FIG. This output characteristic is
In the range of “−π to + π”, the phase is the same as that of the conventional memory type phase comparator 3 and the like, and the phases of the reference signal R and the fluctuation signal V can be compared favorably.

Since the phase difference detector 18 has no storage element, the reference signal R is used as illustrated in FIG. 6 (a).
Even if one of them drops out, the output failure of the phase lead signal D ′ or the phase delay signal U ′ does not end with one corresponding pulse and continues, and the signal that is officially output is the same. Similarly, as shown in FIG. 6B, even if one spike noise is generated in the reference signal R, only one spike noise is similarly generated in the phase delay signal U ′ and the waveform is not affected. The same applies to signals that are officially output.

That is, since the phase difference detector 18 for comparing the reference signal R and the fluctuation signal V and outputting the phase lead signal D and the phase delay signal U does not have a memory element, the conventional non-memory type phase is used. Similar to the comparator 5 and the like, the unstable state of the phase difference detection due to the disturbance can be terminated early. Moreover, since the lead / lag discriminating circuit 23 having a memory element discriminates the lead / lag of the fluctuation signal V with respect to the reference signal R, and the switching device 19 selects the phase lead signal D and the phase delay signal U, the phase comparison range is conventionally. Of the non-memory type phase comparator 5 of FIG.

Further, the phase difference detector 18 to which the reference signal R and the fluctuation signal V are input outputs the phase delay signal U and the phase lead signal D as U '= R + inversion V D' = inversion R + V. Therefore, the phase comparator 15 can be realized with an extremely simple logic structure, and the productivity is good and the miniaturization is easy.

Further, the lead / lag determining circuit 23 to which the reference signal R and the fluctuation signal V are input is set when both the reference signal R and the fluctuation signal V are inverted, and both the reference signal R and the fluctuation signal V are set. Since the RS-flip-flop 22 which is reset unless is inverted, the discrimination signal Q can be accurately output with an extremely simple structure, the productivity is good and the miniaturization is easy.

Further, since the reference signal R and the fluctuation signal V are set as logic signals having the same pulse width and a duty ratio of 50 (%), the maximum phase comparison range is "-π to +".
π ”, and no dead zone is generated within that range.

That is, as illustrated in FIG. 7, if the pulse widths of the reference signal R and the fluctuation signal V are different, the phase delay signal U and the phase advance signal D are generated even if there is a phase difference. As illustrated in FIG. 8, a dead zone occurs near the phase difference “0”. In this case, since the waveform is not inverted, the phase comparator 15 does not run away even if it passes through the dead zone near the phase difference "0", but better characteristics can be obtained when the waveform is linear. Therefore, in such a case, a one-shot multivibrator (not shown) is provided in the input units 16 and 17 for the reference signal R and the fluctuation signal V so that the reference signal R and the fluctuation signal V have the same pulse width. It is preferable to eliminate the dead zone.

As shown in FIG. 9, if the duty ratio of the reference signal R and the fluctuation signal V deviates from the vicinity of 50 (%), the discrimination signal Q cannot be output even if there is a phase difference. However, as illustrated in FIG. 10, the phase comparison range may narrow. Therefore, in such a case, a one-shot multivibrator (not shown) corresponding to the cycle of the reference signal R and the fluctuation signal V is used as the input unit 16,
It is preferable that the duty ratio of the reference signal R and the fluctuation signal V is 50 (%).

Next, a second embodiment of the present invention will be described below with reference to FIG. The same parts as those of the phase comparator 15 described as the first embodiment are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the phase comparator 32 of the present embodiment is similar to the above-described phase comparator 15 in that it has a phase difference detecting section 33 which is a phase difference detecting means having no storage element and an RS-flip-flop circuit which is a storage element. A lead / lag discriminating circuit 34 which is a lead / lag discriminating means having a group 22 and a switching device 35 which is a signal selecting means.

The phase difference detector 33 receives the NAND gate 25 to which the reference signal R is directly input and the fluctuation signal V is input via the inverter 24, and the reference signal R is input via the inverter 26. And a NAND gate 27 to which the fluctuation signal V is directly input. In addition, the lead / lag determination circuit 34 uses the reference signal R
AND gate 2 to which both the variable signal V and the fluctuation signal V are directly input
8, the reference signal R and the fluctuation signal V are both inverter 2
AND gate 31 input via 4, 26 and RS
And a flip-flop 22.

That is, in the phase comparator 32 of this embodiment,
The phase difference detection unit 33 and the lead / lag determination circuit 34 also function as the inverters 24 and 26.

The switching device 35 is formed of, for example, an OR gate 36 to which the phase delay signal U and the discrimination signal Q are input, and an OR gate 37 to which the phase advance signal D and the discrimination signal Q are input. There is.

In such a configuration, the phase comparator 32
When the fluctuation signal V and the reference signal R are input to the phase difference detector 33, the phase difference detector 33 outputs the phase lag signal U'and the phase lead signal D'to the input gate of the switching device 35, and at the same time, leads and lags. RS-flip-flop 2 of discrimination circuit 34
2 is set when both the reference signal R and the fluctuation signal V are inverted, and is reset when both the reference signal R and the fluctuation signal V are not inverted, and the result is set as the determination signal Q to the control input of the switching device 35. Output.

Therefore, the switching device 35 blocks one of the phase lag signal U'and the phase lead signal D'output from the phase difference detecting section 33 according to the discrimination signal Q output from the lead lag discriminating circuit 34, while blocking the other. Therefore, when the fluctuation signal V is delayed from the reference signal R, the phase lead signal D ′ is cut off and the phase delay signal U ′ is output as the formal phase delay signal U, and the fluctuation signal from the reference signal R. When V is advanced, the phase delay signal U'is cut off and the phase advance signal D'is output as the official phase advance signal D.

Therefore, the phase delay signal U and the phase lead signal D selectively output by the phase comparator 32 in this way are converted into analog voltages by a charge pump (not shown) and filtered by the LPF. Then, "π ~ + π"
It is possible to compare the phases of the reference signal R and the fluctuation signal V in the range.

By doing so, like the conventional phase comparators 3 and 5, the phase difference in which the fluctuation signal V leads the reference signal R can be output as the phase lead signal D,
The phase difference in which the fluctuation signal V is delayed from the reference signal R can be output as the phase delay signal U.

Then, such a phase lead signal D and a phase delay signal U are detected by the phase difference detecting section 33 having no memory element.
As described above, the unstable state of the phase difference detection due to the disturbance can be ended early as in the conventional non-memory type phase comparator 5 and the like. Moreover, the lead / lag discriminating circuit 34 having a storage element causes the fluctuation signal V with respect to the reference signal R
Since the switching device 35 selects the phase advance signal D and the phase delay signal U by discriminating the advance / delay of the above, the wide phase comparison range can be secured like the conventional memory type phase comparator 3 and the like. .

A PLL circuit 38 using the phase comparator 32 of this embodiment will be described below with reference to FIG. First, in the PLL circuit 38, the charge pump 39 and the LPF 4 are added to the phase comparator 32 to which the reference signal R is input.
0 and the voltage controlled oscillator 41 are sequentially connected, and the output of the frequency divider 42 connected to the output of the voltage controlled oscillator 41 is input to the phase comparator 32 as the fluctuation signal V.

In such a configuration, the phase comparator 32
Outputs digitally the phase lead signal D or the phase delay signal U in response to the reference signal R input from the outside and the fluctuation signal V fed back from the voltage controlled oscillator 41. Then
This digital signal is converted into an analog voltage by the charge pump 39, filtered by the LPF 40, and output from the voltage controlled oscillator 41 at a predetermined frequency. Then, this signal is output to the outside and divided by the frequency divider 42 into a fraction, and then the fluctuation signal V is fed to the phase comparator 32.
Will be returned as. In this way, the signal output from the PLL circuit 38 to the outside is synchronized with the reference signal R input from the outside to the PLL circuit 38 at a frequency that is a multiple of the frequency divider 42.

In the PLL circuit 38, since the phase comparator 32 does not have a storage element in the phase difference detecting section 33,
Even if synchronization is lost due to disturbance, the unstable state ends quickly. Moreover, since the phase comparator 32 selectively outputs the phase advance signal D and the phase delay signal U in the advance / delay determination circuit 34 having a storage element, it is possible to synchronize even in a state where the phase difference between the signal frequencies is large. .

In the above PLL circuit 38, when the reference signal R and the fluctuation signal V have different pulse widths as described above, the reference signal R and the fluctuation signal V are different from each other as illustrated in FIG. In order to eliminate the dead zone of the phase comparator 32, the one-shot multivibrator 43 is provided in the portion where is input to the phase comparator 32 to form the PLL circuit 44 so that the reference signal R and the fluctuation signal V have the same pulse width. Is preferred.

Next, a third embodiment of the present invention will be described below with reference to FIG. In addition, P illustrated in this embodiment
With regard to the LL circuit 45, the same parts as those of the PLL circuits 1 and 38 described above use the same names and reference numerals, and detailed description thereof will be omitted.

First, in the PLL circuit 45 of this embodiment, the input section 2 of the reference signal R is connected to the memory type phase comparator 46 and the non-memory type phase comparator 32, and these phase comparators are connected. 46 and 32 are connected to a switching circuit 6 which is a comparator switching means. The switching circuit 6 is connected to the voltage controlled oscillator 41 via the charge pump 39 and the LPF 40.
The output of 1 is input to the output unit 8 and the phase comparators 46 and 32. Incidentally, the memory type phase comparator 46
Is the same as the phase comparison unit 10 of the memory type phase comparator 3 of the PLL circuit 1 described above as a conventional example.

In such a configuration, in the initial state, the output of the memory type phase comparator 46 is selected by the switching circuit 6, and when the synchronization acquisition is completed by this phase comparator 46, the phase comparator 32 is switched by the switching circuit 6. To be selected.

By doing so, in the initial state where the phase difference between the signal frequencies is large, the memory type phase comparator 46 having a wide phase comparison range is selected, so that the synchronization acquisition is easy, and after the completion of the synchronization acquisition. , The non-memory type phase comparator 32 that is strong against disturbance is selected, so that the operation is stable.

Moreover, since the phase comparator 32 is a non-memory type, but has the same output characteristics as the memory type phase comparator 46, these phase comparators 32 and 46 are simply switched by the switching circuit 6. be able to. That is, it is not necessary to use the delay element 4 or the like to match the characteristics of the non-memory type phase comparator 32 with the characteristics of the memory type phase comparator 46. It is not necessary to provide a dedicated LPF 40 for each of 32 and 46 to match the gains. Therefore, P of this embodiment
The LL circuit 45 has a simple structure and does not require any complicated adjustment, and thus has good productivity.

Next, a fourth embodiment of the present invention will be described below with reference to FIG. In addition, P illustrated in this embodiment
Regarding the LL circuit 47, the same parts as those of the PLL circuit 45 and the like described above are designated by the same names and reference numerals, and detailed description thereof will be omitted.

First, in the PLL circuit 47 of this embodiment, the input section 2 of the reference signal R is connected to the memory type phase comparator 46 and the non-memory type phase comparator 32, and these phase comparators are connected. 46 and 32 are connected to the switching circuit 6. The switching circuit 6 is connected to the drive motor 50 via the charge pump 39, the LPF 48 and the motor driver 49.
The output of the rotation angle sensor 51, which is the speed detecting means for detecting the rotation speed of the phase comparators 46 and 32, is the fluctuation signal V.
Has been entered in.

The LPF of the PLL circuit 47 of this embodiment is
Since 48 is designed for motor control, it differs from the LPF 40 such as the PLL circuit 45 described above. Also,
The rotation angle sensor 51 is, for example, an FG (Frequency Gen).
erator) and a rotary encoder (both not shown).

In such a configuration, the PL of this embodiment is
The L circuit 47 rotationally drives the drive motor 50 at a rotation speed synchronized with the frequency of the reference signal R. At this time, in the initial state, the output of the memory type phase comparator 46 is selected by the switching circuit 6, and when the synchronization acquisition is completed by the phase comparator 46, the phase comparator 32 is selected by the switching circuit 6.

By doing so, in the initial state where the phase difference of the signal frequency is large, the memory type phase comparator 46 having a wide phase comparison range is selected, so that the synchronization acquisition is easy, and after the completion of the synchronization acquisition. , The non-memory type phase comparator 32 that is strong against disturbance is selected, so that the operation is stable.

Moreover, since the phase comparator 32 is a non-memory type, but has the same output characteristics as the memory type phase comparator 46, these phase comparators 32 and 46 are simply switched by the switching circuit 6. be able to. That is, it is not necessary to use the delay element 4 or the like to match the characteristics of the non-memory type phase comparator 32 with the characteristics of the memory type phase comparator 46. It is not necessary to provide a dedicated LPF 40 for each of 32 and 46 to match the gains. Therefore, P of this embodiment
The LL circuit 47 has a simple structure and does not require complicated adjustment, and thus has good productivity.

[0073]

According to the first aspect of the present invention, since the phase difference detecting means for outputting the phase delay signal and the phase lead signal is provided without the storage element, the unstable state of the phase difference detection due to the disturbance is prevented. The phase-lag signal is selected when the lead-lag discriminating means, which has a storage element and terminates early, and discriminates the lead-lag of the fluctuation signal with respect to the reference signal, is provided. By providing the signal selection means for selecting the phase delay signal when determining the delay of the fluctuation signal, a wide phase comparison range can be secured and the output characteristic of the phase comparison can be made linear, so that the disturbance It has the effect of being able to obtain a phase comparator having a strong phase comparison range and a wide phase comparison range and a linear phase comparison characteristic.

According to the second aspect of the present invention, when the reference signal is R, the fluctuation signal is V, the phase delay signal is U, and the phase lead signal is D, the relationship of U = R + inversion V D = inversion R + V is satisfied. By doing so, the logical output form of the phase delay signal and the phase lead signal output by the phase difference detecting means having no storage element can be made equal to that of the memory type phase comparator, so that it is a non-memory type. The phase comparator having the same output characteristics as the memory type can be obtained.

According to a third aspect of the present invention, the lead-lag determining means is an RS-flip-flop which is set when both the reference signal and the fluctuation signal are inverted and is reset when both the reference signal and the fluctuation signal are not inverted. With this, it is possible to output a signal corresponding to a fluctuation signal delayed from the reference signal or a reference signal delayed from the fluctuation signal, and a phase comparator having a linear phase comparison characteristic that is strong against disturbance and has a wide phase comparison range is provided. It has the effect that it can be realized with a simple structure.

According to the invention described in claim 4, since the reference signal and the fluctuation signal are logic signals having the same pulse width, the phase delay signal and the phase lead signal, which are the phase differences between them, are always output satisfactorily. Therefore, it is possible to obtain the maximum phase comparison range.

According to a fifth aspect of the present invention, in the PLL circuit in which the memory type phase comparator is selected before the completion of the synchronization acquisition and the non-memory type phase comparator is selected after the completion of the synchronization acquisition, the non-memory type comparator is selected. , A phase difference detecting means for outputting a phase lag signal and a phase lead signal without having a storage element, and a lead / lag determining means for having a storage element to discriminate the lead / lag of a fluctuation signal with respect to a reference signal. And the signal selection means for selecting the phase advance signal when the advance / delay determination means determines the advance of the fluctuation signal and the phase delay signal when the delay is determined. Since the output characteristics are similar to those of the memory type phase comparator, these phase comparators can be simply switched, and the structure is simple and no complicated adjustment is required, so that the productivity is good. That.

According to a sixth aspect of the present invention, in a PLL circuit configured to control the rotation of a drive motor, a phase difference detecting means for outputting a phase delay signal and a phase lead signal without a storage element, and a storage element. A lead / lag determination means for determining the lead / lag of the fluctuation signal with respect to the reference signal,
A non-memory type phase comparator having no storage element is formed with the signal selecting means for selecting the phase lead signal when the lead / lag discriminating means discriminates the advance of the fluctuation signal and for selecting the phase delay signal when discriminating the delay. However, this non-memory type phase comparator, the memory type phase comparator having a storage element, and the memory type phase comparator are selected before the completion of the synchronization acquisition, and the non-memory type comparator is selected after the completion of the synchronization acquisition. By providing the comparator switching means for selecting the phase comparator, the output characteristics of the non-memory type phase comparator are equivalent to those of the memory type phase comparator. Therefore, these phase comparators can be simply switched. Since it has a simple structure and does not require complicated adjustment, it has an effect such as good productivity.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a phase comparator according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a phase difference detection unit that is a phase difference detection unit.

FIG. 3 is a circuit diagram illustrating a lead-lag detection circuit that is a lead-lag detection unit.

FIG. 4 illustrates the relationship of various signals of the phase comparator, (a)
Is a time chart exemplifying a state where the fluctuation signal V is delayed from the reference signal R, and (b) is a time chart exemplifying a state where the fluctuation signal V is advanced from the reference signal R.

FIG. 5 is a characteristic diagram illustrating an output characteristic of a phase comparator.

FIG. 6 illustrates the relationship of various signals of the phase comparator, (a)
6B is a time chart illustrating a state where dropout occurs in the reference signal R, and FIG. 7B is a time chart illustrating a state where spike noise occurs in the reference signal R.

FIG. 7 illustrates the relationship between various signals of the phase comparator when the pulse width of the reference signal R is wider than the fluctuation signal V, and FIG. 7A illustrates a state in which the rising edges of the reference signal R and the fluctuation signal V are synchronized. 2B is a time chart illustrating a state in which the fluctuation signal V is delayed from the reference signal R.

FIG. 8 is a characteristic diagram illustrating output characteristics of the phase comparator in a state where the pulse widths of the reference signal R and the fluctuation signal V are different and a dead zone is generated in the vicinity of the phase difference “0”.

FIG. 9 shows that the duty ratio of the reference signal R and the fluctuation signal V is 5
The relation of various signals of the phase comparator when it deviates from the vicinity of 0 (%) is illustrated, (a) is a time chart illustrating the state where the fluctuation signal V advances from the reference signal R, and (b) is the reference signal R.
7 is a time chart illustrating a state in which the fluctuation signal V is delayed.

FIG. 10 shows the duty ratio of the reference signal R and the fluctuation signal V
It is a characteristic view which illustrates the output characteristic of the phase comparator in the state where it deviated from the vicinity of 50 (%) and the phase comparison range became small.

FIG. 11 is a block diagram illustrating a phase comparator according to a second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a PLL circuit using a phase comparator according to a second embodiment of the present invention.

FIG. 13 is a block diagram illustrating another PLL circuit using the phase comparator of the second embodiment of the present invention.

FIG. 14 is a PLL circuit P according to a third embodiment of the present invention.
It is a block diagram which illustrates an LL circuit.

FIG. 15 is a block diagram illustrating a PLL circuit according to a fourth embodiment of the present invention.

FIG. 16 is a block diagram illustrating a conventional PLL circuit.

FIG. 17 is a block diagram illustrating a state in which contents of a PLL circuit are supplemented.

FIG. 18 is a time chart illustrating the relationship of various signals of the non-memory type phase comparator.

FIG. 19 illustrates output characteristics of a non-memory type phase comparator, FIG. 19A is a characteristic diagram illustrating a state in which no special processing is performed, and FIG. 19B is a characteristic diagram illustrating a state in which an offset voltage is applied. FIG. 6C is a characteristic diagram illustrating a state in which the phase difference is shifted by “π / 2”.

[Explanation of symbols]

 6 comparator switching means 15, 32 phase comparator 18, 33 phase difference detecting means 19, 35 signal selecting means 22 RS-flip-flop 23, 34 lead / lag determining means 45, 47 PLL circuit 46 phase comparator 49 motor driver 50 drive Motor 51 Speed detection means

Claims (6)

[Claims] 1. A fluctuation signal is compared with a reference signal to detect a phase difference, and the phase difference when the phase of the fluctuation signal leads the phase of the reference signal is output as a phase advance signal, In a phase comparator that outputs a phase difference when the phase of the fluctuation signal is delayed with respect to the phase as a phase delay signal, a phase difference detection unit that outputs the phase delay signal and the phase advance signal without a storage element is provided. Provided is a lead / lag discriminating means having a storage element for discriminating the lead / lag of the fluctuation signal with respect to the reference signal. When the lead / lag discriminating means judges the lead of the fluctuation signal, the phase lead signal is selected to delay the fluctuation signal. A phase comparator characterized in that it is provided with a signal selecting means for selecting a phase lag signal when discriminating. 2. When the reference signal is R, the fluctuation signal is V, the phase delay signal is U, and the phase lead signal is D, the relationship of U = R + inversion V D = inversion R + V is satisfied. The phase comparator according to claim 1. 3. The lead / lag determination means has an RS-flip-flop that is set when both the reference signal and the fluctuation signal are inverted and is reset when both the reference signal and the fluctuation signal are not inverted. The phase comparator according to claim 1. 4. The phase comparator according to claim 1, wherein the reference signal and the fluctuation signal are logic signals having the same pulse width and a duty ratio of 50 (%). 5. A memory type phase comparator having a memory element, a non-memory type phase comparator having no memory element, and a comparator switching means for selecting one of these phase comparators. In the PLL circuit, the comparator switching means selects the memory type phase comparator before the completion of the synchronization acquisition and selects the non-memory type phase comparator after the completion of the synchronization acquisition. Comparator, a phase difference detecting means for outputting a phase delay signal and a phase advance signal without having a storage element, and a lead / lag determining means for having a storage element to determine the lead / lag of the fluctuation signal with respect to the reference signal, A PLL circuit formed by a signal selecting means for selecting a phase lead signal when the lead / lag discriminating means discriminates the advance of the fluctuation signal and for selecting a phase delay signal when discriminating the delay of the fluctuation signal. 6. The output of the phase comparator is input to a motor driver, the rotation speed of a drive motor driven by the motor driver is detected by speed detecting means, and the output of the speed detecting means is used as a fluctuation signal to the phase comparator. In a PLL circuit configured to control the rotation of the drive motor by feeding back to the drive circuit, a phase difference detecting means for outputting a phase delay signal and a phase lead signal without a storage element, and a reference signal having a storage element. A lead / lag determination means for determining the lead / lag of the fluctuation signal, and a signal selection for selecting the phase lead signal when the lead / lag judgment means determines the lead of the fluctuation signal, and for selecting the phase delay signal when discriminating the delay of the fluctuation signal. By means,
Forming a non-memory type phase comparator without a storage element,
This non-memory type phase comparator, a memory type phase comparator having a storage element, and the memory type phase comparator is selected before the completion of the synchronization acquisition and the non-memory type comparator after the completion of the synchronization acquisition. A PLL circuit comprising a comparator switching means for selecting a phase comparator.