JP3410856B2 - Phase comparison method, phase comparator, and PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase comparator and a PLL.
(Phase Locked Loop) circuit.

[0002]

2. Description of the Related Art A conventional phase comparator detects a phase difference by comparing a fluctuation signal with a reference signal and detects the phase difference when the phase of the fluctuation signal is ahead of the phase of the reference signal. And outputs the phase difference when the phase of the fluctuation signal is delayed with respect to the phase of the reference signal as a phase delay signal.

Further, a PLL circuit formed by using such a phase comparator inputs the output of the phase comparator to a VCO (Voltage Controlled Oscillator) which is a voltage controlled oscillator, and compares the output of this VCO with the phase comparison. To return to the vessel. Therefore, the frequency of the output signal of the VCO is synchronized with the frequency of the input signal of the phase comparator.

The phase comparator as described above is classified into a memory type having a storage element and a non-memory type having no storage element. For example, as shown in FIG. 11, a digital memory type phase comparator 1 includes input sections 2 and 3 for a reference signal R and a fluctuation signal V, and an output section 4 for a phase delay signal U and a phase advance signal D. , 5 and are formed by a combination of a large number of NAND gates 6 to 14. In this case, the RSs functioning as a storage element are formed by the NAND gates 7 and 8 and the NAND gates 9 and 10 connected in a loop.
Flip-flops F1, F2 are formed.

In such a structure, as shown in FIG. 12A, when the fluctuation signal V is delayed from the reference signal R, the phase advance signal D is not generated but the phase delay signal U is generated, As shown in FIG. 12B, when the fluctuation signal V leads the reference signal R, the phase advance signal D is generated without generating the phase delay signal U.

Therefore, as shown in FIG. 13, a charge pump 15 and an LPF (Low Pass Filter) 16 which is a loop filter are connected to the phase comparator 1 as described above, and the phase delay output from the phase comparator 1 is delayed. When the signal U and the phase lead signal D are converted into an analog voltage by the charge pump 15 and then filtered by the LPF 16, the characteristics of the output voltage and the phase difference are as shown in FIG. In this case, the phase comparator 1 determines that the output voltage and the phase difference are “−2π
Since it has a linear relationship in the range of up to + 2π ″, it functions as a frequency comparator.

The memory type phase comparator 1 as described above is
The range in which the phases can be compared characteristically is as wide as "-2π to + 2π", but if the comparison operation becomes unstable due to a disturbance such as noise, this unstable state causes the RS-flip-flop F1,
Continue long term for F2. On the other hand, in the non-memory type phase comparator, even if the operation becomes unstable due to the disturbance, the unstable state ends early because there is no storage element, but the range in which the phases can be compared is “−π / 2 to + π”. It is as narrow as / 2 ".

Therefore, the PLL circuit using the memory type phase comparator can be synchronized even when the phase difference of the signal frequency is large, but the PLL circuit using the non-memory type phase comparator is It is difficult to synchronize from the state where the phase difference of the signal frequency is large.

More specifically, the PLL circuit synchronization process includes a frequency pulling process and a phase pulling process. In the case of a PLL circuit using a non-memory type phase comparator, the frequency pull-in is performed by the DC component when the phase difference output largely fluctuates due to delay and advance, so that it takes time to synchronize and the reference signal It may be accidentally drawn into higher frequencies. In the case of the PLL circuit using the memory type phase comparator, the function as the frequency comparator shortens the synchronization time and prevents the higher frequency of the reference signal. However, as mentioned above, the memory type phase comparator becomes unstable when the operation becomes unstable due to disturbance.
Since this continues for a long time, the PLL circuit using such a phase comparator also remains in an unstable state for a long time.

For example, in a memory type phase comparator,
As shown in FIG. 15A, when one of the reference signals R drops out, the next reference signal R and the fluctuation signal V are compared in phase, the phase delay signal U is no longer output, and the phase advance signal D is erroneous. May be output as Similarly, FIG.
As shown in FIG. 5 (b), when one spike noise occurs in the reference signal R, the spike noise and the next fluctuation signal V are compared in phase, and the phase advance signal D is no longer output, and the phase delay signal U becomes It may be output incorrectly.

That is, a PLL circuit using a memory type phase comparator and a PL circuit using a non-memory type phase comparator
The L circuit has contradictory advantages and disadvantages. A PLL circuit that solves such a problem is disclosed in
-70124 gazette. The PLL circuit disclosed in this publication has a memory-type phase comparator and a non-memory-type phase comparison switchably, and a memory-type phase comparator having a wide phase comparison range in an initial state where a phase difference of signal frequencies is large. After the phase comparator is selected and its synchronization acquisition is completed, a non-memory type phase comparator resistant to disturbance is selected.

[0012]

The PLL circuit of the above publication uses memory type and non-memory type phase comparators separately.

However, since the memory type and non-memory type phase comparators have different output characteristics, if they are simply switched, the operation of the PLL circuit becomes unstable due to the high voltage difference between the outputs.

Therefore, the PLL disclosed in the above publication.
The circuit uses delay elements to match the characteristics of the non-memory type phase comparator with the characteristics of the memory type phase comparator, but this requires fine circuit adjustment such as gain adjustment. Is. Therefore, in the PLL circuit of the above publication, it is actually difficult to match the output characteristics of the memory type and non-memory type phase comparators, and the productivity is poor.

Further, P having a memory type phase comparator 1
In the LL circuit, even if noise does not act, FIG.
When the phase of the fluctuating signal is delayed from the reference signal as shown in FIG. 16 or when the phase of the fluctuating signal is advanced from the reference signal as shown in FIG. The correspondence relationship of may break. In these cases, as indicated by circles in the drawing, a pulse that is not used for phase difference detection occurs in the delayed signal, and a discontinuous portion is output in the phase difference detection result until the next pulse occurs. To be done. This means that, as shown in FIG. 14, when the phase difference between the reference signal and the fluctuation signal exceeds “± 2π”, the detection result of the phase difference decreases to around “0”. Such discontinuities reduce the amount of feedback, but this is not a proper treatment.

Further, the PLL circuit using the phase comparator 1 as described above also takes time to acquire synchronization, but the PLL
In the case of the circuit, not only the phase comparator but also the LPF and the like are factors that determine the time required for the synchronization acquisition. For this reason, the PLL circuit is designed in consideration of the balance between responsiveness and stability. For example, when the rotation speed of the drive motor is controlled by the PLL circuit, the responsiveness of the mechanical system is slower than that of the electrical system, Since the drive motor and the drive mechanism have inertia, the feedback control of the PLL circuit may vibrate around the stable point and may not converge. In such a case, the PLL is sacrificed in response to prevent vibration.
Since the circuit is designed, the drive motor pickup will be reduced.

In order to solve the above-mentioned problems, it has been proposed to provide another feedback loop for the rotation speed of the drive motor or to reverse the feedback control or brake it before the stable point. . However, this complicates the structure of the control system and reduces productivity and reliability.

[0018]

According to another aspect of the present invention, there is provided a memory type phase comparator having a memory element, wherein a signal output means outputs a reference signal, and a phase difference of a fluctuation signal with respect to the reference signal. Is detected by the signal comparison means, and when the phase difference exceeds "+ 2π", the phase of the reference signal is shifted by "+ π" by the reference variable means, and when the phase difference exceeds "-2π". The phase of the fluctuation signal is shifted by "+ π" by the fluctuation varying means.

According to a second aspect of the present invention, in the phase comparator of the memory type having a storage element, a signal output means for outputting a reference signal is provided, and a signal comparison means for detecting a phase difference of the fluctuation signal with respect to the reference signal. Is provided, the phase of the reference signal is set to “+” when the detected phase difference exceeds “+ 2π”.
The reference variable means for shifting by π "is provided, and the variation variable means for shifting the phase of the fluctuation signal by" + π "is provided when the detected phase difference exceeds" -2π ".

According to a third aspect of the present invention, there is provided the phase comparator of the second aspect.
In the phase comparator described above, the signal comparison means outputs the phase difference of the fluctuation signal leading with respect to the reference signal as a phase lead signal and the phase difference of the phase difference of the fluctuation signal delayed with respect to the reference signal. The signal is output as a signal, and the reference variable means receives the reference signal when the phase delay signal is "ON".
If the phase delay signal exceeds “+ 2π”,
The phase of the quasi-signal is shifted by "+ π", and the fluctuation varying means receives the fluctuation signal when the phase lead signal is "on".
Then, assuming that the phase lead signal exceeds "-2π", the phase of the fluctuation signal is shifted by "+ π".

According to a fourth aspect of the present invention, there is provided the phase comparator of the second aspect.
Alternatively, in the phase comparator described in 3, the signal output means outputs the reference signal as a logic signal having a duty ratio of 50 (%), and the reference varying means inverts the reference signal by the knot circuit to set the phase to “+ π”. Only shift.

According to a fifth aspect of the present invention, there is provided a PLL circuit according to the second aspect.
The phase comparator described in 3 or 4, a charge pump for converting the output signal of the phase comparator from digital to analog, a loop filter for filtering the output signal of the charge pump, and an output voltage of the loop filter are provided. It has a voltage controlled oscillator that generates an output signal of an oscillation frequency, and a frequency divider that divides the output signal of this voltage controlled oscillator by an even number and then outputs it as a fluctuation signal to the phase comparator.

According to a sixth aspect of the present invention, there is provided a PLL circuit according to the second aspect.
The phase comparator described in 3 or 4, a charge pump for converting the output signal of the phase comparator from digital to analog, a loop filter for filtering the output signal of the charge pump, and an output voltage of the loop filter are provided. A voltage-controlled oscillator that outputs a signal of an oscillation frequency, and a frequency divider that divides the output signal of this voltage-controlled oscillator by an odd number and then outputs it as a fluctuation signal to the phase comparator,
Signal conversion means for generating a second output signal whose phase is shifted by "π" using the output signal of the voltage controlled oscillator as a first output signal, and the phase comparator varies one phase of the reference signal and the fluctuation signal. Output selecting means for selectively outputting the second output signal only when

A PLL circuit according to claim 7 is the PLL circuit according to claim 2,
Corresponding to the phase comparator described in 3 or 4, a charge pump that converts the output signal of this phase comparator from digital to analog, a loop filter that filters the output signal of this charge pump, and the output voltage of this loop filter. Motor driver that outputs drive power by a motor, a drive motor that is driven by the drive power that this motor driver outputs, and a speed detector that detects the rotation speed of this drive motor and outputs a corresponding fluctuation signal to the phase comparator. And means.

[0025]

In the phase comparison method according to the first aspect of the present invention, the reference signal is output by the signal output means, the phase difference of the fluctuation signal with respect to the reference signal is detected by the signal comparison means, and the phase difference exceeds "+ 2π". In this case, the phase of the reference signal is shifted by "+ π" by the reference varying means so that the phase difference is "-".
When it exceeds 2π ", the fluctuation varying means shifts the phase of the fluctuation signal by" + π ", so that these fluctuations shorten the discontinuous portion of the synchronous acquisition of the reference signal and the fluctuation signal.

In the phase comparator according to the second aspect of the present invention, the reference signal is output by the signal output means, the phase difference of the fluctuation signal with respect to the reference signal is detected by the signal comparison means, and the phase difference exceeds "+ 2π". In this case, the phase of the reference signal is shifted by "+ π" by the reference varying means, and when the phase difference exceeds "-2π", the phase of the varying signal is shifted by "+ π" by the variation varying means. Of the reference signal and the fluctuating signal shortens the discontinuous portion of the synchronous acquisition.

In the phase comparator according to the present invention, the signal comparing means outputs the phase difference of the fluctuation signal leading the reference signal as a phase lead signal and the fluctuation signal delayed from the reference signal. The phase difference of is output as a phase delay signal, and the reference variable means is used when the phase delay signal is "ON".
When the reference signal is input, the phase delay signal becomes "+ 2π".
Excess reference signal of the phase "+ [pi" only shifted as variation varying means, varying when the phase lead signal is "ON"
When a motion signal is input, the phase advance signal exceeds "-2π".
Since the phase of the fluctuating signal is shifted by "+ .pi.", The variable portion shortens the discontinuous portion of the synchronous acquisition of the reference signal and the fluctuating signal.

According to another aspect of the phase comparator of the present invention, the signal output means outputs the reference signal as a logic signal having a duty ratio of 50 (%), and the reference varying means inverts the reference signal by a knot circuit to phase the signal. Is shifted by "+ π", the phase of the reference signal is shifted by "+ π" by inversion.

According to a fifth aspect of the PLL circuit, the output signal of the phase comparator of the second, third or fourth aspect is converted from digital to analog by a charge pump, this output signal is filtered by a loop filter, and this output signal is output. An output signal having an oscillation frequency corresponding to the voltage is generated by the voltage controlled oscillator. Thus, the fluctuating signal is synchronously acquired with the reference signal, but this synchronous acquisition is completed quickly due to the characteristics of the phase comparator. Moreover, since the output signal of the voltage controlled oscillator is divided into even numbers by the frequency divider and then output to the phase comparator as a fluctuation signal, even if the phase comparator changes the phase of the reference signal or the fluctuation signal, the PLL The output signal of the circuit does not change.

According to a sixth aspect of the PLL circuit, the output signal of the phase comparator of the second, third or fourth aspect is converted from digital to analog by a charge pump, and this output signal is filtered by a loop filter to output the output. An output signal having an oscillation frequency corresponding to the voltage is generated by the voltage controlled oscillator. Thus, the fluctuating signal is synchronously acquired with the reference signal, but this synchronous acquisition is completed quickly due to the characteristics of the phase comparator.

Moreover, the output signal of the voltage controlled oscillator is divided by the frequency divider by an odd number and then output to the phase comparator as a fluctuation signal. The second output signal shifted by π ″ is generated by the signal converting means, and the output selecting means is such that the phase comparator does not change the phases of both the reference signal and the fluctuation signal, and both of them change. Means to selectively output the first output signal, and selectively outputs the second output signal when the phase comparator varies one of the phases of the reference signal and the fluctuation signal. Therefore, even if the phase comparator varies the phases of the reference signal and the fluctuation signal, the output signal of the PLL circuit does not change.

According to a seventh aspect of the present invention, there is provided a PLL circuit according to the second aspect.
The output signal of the phase comparator described in 3 or 4 is converted from digital to analog by the charge pump, and this output signal is filtered by the loop filter. The drive power corresponding to this output voltage is output by the motor driver, and the drive motor is driven by the drive power. The rotation speed of the drive motor is detected by the speed detection means and a corresponding fluctuation signal is output to the phase comparator, so that the rotation speed of the drive motor is synchronously captured with the reference signal. Completed quickly due to the characteristics of.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. First, the phase comparator 1 of the present embodiment
As shown in FIG. 1, reference numeral 7 denotes input sections 18 and 19 for the reference signal R and the fluctuation signal V, a phase delay signal U and a phase advance signal D.
And output units 20 and 21 for The input section 18 of the reference signal R is divided into two and one is provided with a phase shifter 22.
Are provided, and both are connected to one signal selector 23. The input section 19 of the fluctuation signal V is also branched into two parts, one of which is provided with a phase shifter 24, and both of them are connected to one signal selector 25.

The signal selectors 23 and 25 are connected to a phase comparator 26 which is a signal comparing means, and the phase comparator 26 is connected to the output sections 20 and 21. Further, the phase comparator 26 is connected to a signal discriminator 27, and the signal discriminator 27 is connected to the signal selector 23 and the signal selector 25.

The phase shifter 22 is formed of an existing shift register, counter, delay circuit (neither shown), etc., and the reference signal R is the first reference signal R, and its phase is "+ π". To generate the second reference signal R bar. Similarly, the phase shifter 24 also
The fluctuation signal V is the first fluctuation signal V, and its phase is "+".
The second fluctuation signal V bar is generated by shifting by π ″.
In this embodiment, since the reference signal R and the fluctuation signal V are logic signals having a duty ratio of 50 (%), the phase shifters 22 and 24 use the knot circuit (not shown) to output the signals R and V. Is inverted to output the signals R bar and V bar.

The signal selector 23 is formed by an existing digital switching device (not shown) such as a switching circuit or a multiplexer, and corresponds to the selection signal Sr of the signal discriminator 27, and the first and second signals are selected. One of the reference signals R and R bar is selectively output as the reference signal R '. Similarly, the signal selector 25 also selects the selection signal S of the signal discriminator 27.
Corresponding to r, one of the first and second fluctuation signals V and V bar is selectively output as a fluctuation signal V '.

The phase comparator 26 is formed as a memory type having a storage element, like the phase comparator described above as a conventional example, and detects the phase difference of the fluctuation signal V'with respect to the reference signal R '. . More specifically, as shown in FIG. 2A, when the fluctuation signal V is delayed with respect to the reference signal R, the phase difference is output as a phase delay signal U,
As shown in FIG. 2B, when the fluctuation signal V leads the reference signal R, the phase difference is output as the phase lead signal D.

When the reference signal R is input while the phase delay signal U is "on", the signal discriminator 27 determines that the phase delay signal U exceeds "+ 2π" and selects the selection signal Sr as the signal selector. To 23. Further, when the fluctuation signal V is input when the phase lead signal D is "ON", it is determined that the phase lead signal D exceeds "-2π" and the selection signal Sv is output to the signal selector 25.

The phase comparator 17 of this embodiment uses the reference signal R
When the phase difference between the variable signal V and the fluctuation signal V exceeds "+ 2π", the phase of the reference signal R is shifted by "+ π".
When the phase difference between the fluctuation signal V and the fluctuation signal V exceeds “−2π”, the phase of the fluctuation signal is shifted by “+ π”.
The variation varying means is realized here.

A reference clock (not shown) which is a signal output means for outputting the reference signal R is connected to the input section 18 for the reference signal R. “On” between the phase delay signal U and the phase advance signal D is an active state in which a phase difference is detected, and is represented as “L” in the drawing.

In such a configuration, the phase comparator 17
In the phase comparison method of 1), when the reference signal R and the fluctuation signal V are input to the input units 18 and 19, the phase shifters 22 and 24 are input.
Thus, the second reference signal R bar and the second fluctuation signal V bar whose phases are shifted by “+ π” are generated. Therefore,
The signal selector 2 includes the first and second reference signals R and R bars and the first and second fluctuation signals V and V bar which are different in phase by "π".
The signal selectors 23, 2
Normally, 5 selectively outputs the first reference signal R and the first fluctuation signal V to the phase comparator 26. This phase comparator 26
Detects the phase difference between the first reference signal R and the first fluctuation signal V, and detects the phase difference of the fluctuation signal V delayed with respect to the reference signal R as shown in FIG. 2B, the phase difference of the fluctuation signal V that is ahead of the reference signal R is output as the phase advance signal D, as shown in FIG.

At this time, if the phase difference of the fluctuation signal V with respect to the reference signal R exceeds "+ 2π", as described with reference to FIG. 16 in the conventional example, the first reference signal R and the first fluctuation signal V are separated from each other. The one-to-one correspondence is broken. However, in the phase comparison method of the phase comparator 17 of this embodiment,
In the above case, the phase of one of the first reference signal R and the first fluctuation signal V is shifted by "+ π", so that the discontinuous portion of the phase difference detection result can be shortened.

More specifically, as shown in FIG.
When the phase lag signal U is detected due to the phase difference between the first reference signal R and the first fluctuation signal V, the first fluctuation signal V advances from the first reference signal R at the position of the white circle in the figure, so that it remains as it is. The detection results are discontinuous. However, in the above-mentioned case, since the first reference signal R is input when the phase delay signal U is "ON", the selection signal Sr is output to the signal selector 23. Then, the signal selector 23 switches the output signal from the first reference signal R to the second reference signal R bar, so that the second reference signal R bar and the second reference signal R bar whose phase is shifted by “+ π” are indicated by black circles in the figure. With the one fluctuation signal V, the phase delay signal U is detected substantially continuously. Furthermore, when the phase delay signal U is detected by the phase difference between the second reference signal R bar and the first fluctuation signal V as described above, when the first fluctuation signal V precedes the second reference signal R bar, Since the selector 23 switches the output signal from the second reference signal R bar to the first reference signal R, the phase delay signal U is detected substantially continuously by the first reference signal R and the first fluctuation signal V. .

Similarly, when the phase lead signal D is detected due to the phase difference between the first reference signal R and the first fluctuation signal V, as shown in FIG. When the one fluctuation signal V is delayed, the first fluctuation signal V is input when the phase lead signal D is "ON", so that the selection signal Sv is output from the signal discriminator 27 to the signal selector 23 to cause the first fluctuation. The signal V is switched to the second fluctuation signal V bar, and the phase advance signal D is detected substantially continuously by the second fluctuation signal V bar and the first reference signal R.

That is, when the phase difference between the reference signal R and the fluctuation signal V exceeds "± 2π", the phase comparator 17 of the present embodiment corresponds to the phase of the reference signal R or the fluctuation signal V. Is shifted by "+ π", the discontinuity of detection of the phase delay signal U and the phase advance signal D is alleviated. For this reason,
As will be described later in detail, when a PLL circuit (not shown) is formed by the phase comparator 17 of the present embodiment, even if the one-to-one correspondence between the reference signal R and the fluctuation signal V is broken, the synchronization thereof is Capture can be completed quickly.

Further, in the phase comparator 17 of this embodiment,
Even when the frequencies of the reference signal R and the fluctuation signal V are different and the phase difference is sequentially displaced in one direction, one of the phase advance signal D and the phase delay signal U is output substantially continuously, and these signals D , U are not output alternately, the PLL
When the circuit is formed, the synchronization acquisition is not pulled to higher frequencies.

Moreover, the phase comparator 17 of the present embodiment has the same input / output mode of the reference signal R, the fluctuation signal V, the phase delay signal U, and the phase lead signal D as the conventional one, and the dedicated control signal is used. Since no input is required, it is easy to replace it with a conventional phase comparator as it is.

Further, in the phase comparator 17 of the present embodiment, the reference signal R and the fluctuation signal V are logical signals which are square waves having a duty ratio of 50 (%), and the phase shifters 22 and 24 are provided with the signal R. , V are inverted by the knot circuit, the signals R bar and V bar whose phases are shifted by “+ π” are easily generated with a simple structure. The fluctuation signal V composed of a square wave with a duty ratio of 50 (%) is, for example, an output signal of an encoder connected to a drive motor.

Further, the phase comparator 17 of the present embodiment judges that the phase delay signal U exceeds "+ 2π" when the reference signal R is input when the phase delay signal U is "on",
When the fluctuation signal V is input when the phase lead signal D is "on", it is determined that the phase lead signal D exceeds "-2π", and therefore these determinations are reliably performed with a simple structure.

In the phase comparator 17 of this embodiment, when the phase difference signals D and U exceed "± 2π" as described above, the phases of the signals R and V are changed by "+ π". , The outputs of the signals D and U can be maintained substantially continuously. Normally, the above control alone is sufficient, but P
Depending on the target of the LL control, the phases of the signals R and V can be sequentially switched.

When a PLL circuit (not shown) is formed by connecting a charge pump, LPF or the like to the phase comparator 17 of the present embodiment, this PLL circuit, as shown in FIG. Can be completed.

That is, in the ideal state, the first reference signal R and the first fluctuation signal V are used to detect the phase difference, and as shown in the figure, the phase difference characteristic passes through the zero point. At this time, when the phase delay of the first fluctuation signal V exceeds “+ 2π”, the first reference signal R is switched to the second reference signal R bar, so that the detected phase difference is “0” as shown in the figure. ”
It is maintained near "+ π" without falling to the neighborhood.
Similarly, when the phase advance of the first fluctuation signal V exceeds “−2π”, the first fluctuation signal V switches to the second fluctuation signal V bar, so that the detected phase difference is “as shown in the figure. It is maintained near "-π" without dropping to around 0 ".

Therefore, even if the one-to-one correspondence relationship between the reference signal R and the fluctuation signal V is broken, this correspondence relationship is quickly recovered by the phase comparator 17, so that the PLL circuit also quickly completes the synchronization acquisition. can do.

As shown in the figure, when the phase delay signal U exceeds "+ 2π" and the first reference signal R is switched to the second reference signal R bar, the phase advance signal D is "-".
When it exceeds 2π ″, the second reference signal R bar may be returned to the first reference signal R, but the first fluctuation signal V is actually switched to the second fluctuation signal V bar. However, even in this case , The phase difference is detected by the second reference signal R bar and the second fluctuation signal V bar, so that the phase difference is detected by the first reference signal R and the first fluctuation signal V as shown in the figure. It becomes the same as the state of doing.

Next, a second embodiment of the present invention will be described below with reference to FIGS. With regard to the second embodiment, the same parts as those in the first embodiment described above are designated by the same names and reference numerals, and detailed description thereof will be omitted.

The phase comparator 28 of this embodiment is formed by a TTL (Transistor-Transistor Logic) circuit, as shown in FIG. First, the input sections 18 and 19 for the reference signal R and the fluctuation signal V are respectively branched into two, and one side is provided with inverters 29 and 30 which are knot circuits, and both are provided in the selector circuits 31 and 32. It is connected. A phase comparator 26, which is a signal comparing means, is connected to the selector circuits 31 and 32. The phase comparator 26 has two input terminals of each of the selector circuits 31 and 32 and an inverter 33, It is connected via 34. A D-FF 35 is connected to the output terminals of the signal R bar and U'of the selector circuit 31.
The output terminal of the selection signal Sr of F35 is the selector circuit 3
1 is connected to the control terminal. Similarly, the D-FF 36 is connected to the output terminals of the signals V bar and D ′ of the selector circuit 32.
Are connected, and the output terminal of the selection signal Sv of the D-FF 36 is connected to the control terminal of the selector circuit 32.

In the present embodiment, the reference signal R and the fluctuation signal V are logic signals having a duty ratio of 50 (%).
The inverters 29 and 30 invert the signals R and V to generate signals R bar and V bar whose phases are shifted by "+ π".

The selector circuit 31 includes the D-FF3.
Corresponding to the selection signal Sr of 5, the first and second reference signals R, R
One of the bars is selectively output as the reference signal R '. Similarly, the selector circuit 32 also corresponds to the selection signal Sv of the D-FF 36 and selectively outputs one of the first and second fluctuation signals V and V bar as the fluctuation signal V '.

As shown in FIG. 5, when the fluctuation signal V is delayed with respect to the reference signal R, the phase comparator 26 outputs the phase difference as a phase delay signal U and with respect to the reference signal R. When the fluctuation signal V is advanced, the phase difference is output as a phase advance signal D.

When the reference signal R is input when the phase delay signal U is "ON", the D-FF 35 determines that the phase delay signal U exceeds "+ 2π" and outputs the selection signal Sr to the selector circuit 31. Output. Also, the D-FF3
When the fluctuation signal V is input when the phase lead signal D is "ON", the output signal 6 outputs the selection signal Sv to the selector circuit 32 because the phase lead signal D exceeds "-2π". More specifically, the D-FFs 35 and 36 sample the signals U and D by using the inverted signals R and V as clocks, and output the selection signals Sr and Sv as a result.

The phase comparator 28 of this embodiment uses the reference signal R
When the phase difference between the variable signal V and the fluctuation signal V exceeds "+ 2π", the phase of the reference signal R is shifted by "+ π".
When the phase difference between the fluctuation signal V and the fluctuation signal V exceeds “−2π”, the phase of the fluctuation signal is shifted by “+ π”.
The variation varying means is realized here.

In such a configuration, the phase comparison method of the phase comparator 28 of the second embodiment functions similarly to the phase comparator 17 of the first embodiment described above. That is, as shown in FIG. 5, the phase difference between the first reference signal R and the first fluctuation signal V is usually detected by the phase comparator 26, and the phase difference between the fluctuation signal V and the reference signal R is delayed. Is output as a phase delay signal U, and the phase difference of the fluctuation signal V that is ahead of the reference signal R is output as a phase advance signal D.

Then, as indicated by a white circle in the figure, when the first fluctuation signal V advances from the first reference signal R when the phase delay signal U is detected, the D-FF 35 causes the phase delay signal U to be detected.
Since the first reference signal R is input when is ON, the selection signal Sr is output to the selector circuit 31. Then, the selector circuit 31 switches the output signal from the first reference signal R to the second reference signal R bar. Therefore, as shown by the black circle in the figure, the second reference signal R bar and the first reference signal R bar whose phase is shifted by “+ π” The phase delay signal U is detected substantially continuously by the fluctuation signal V. Similarly, if the first fluctuation signal V lags behind the first reference signal R when the phase lead signal D is detected, the first fluctuation signal V is switched to the second fluctuation signal V bar, and the phase lead signal D becomes It is detected almost continuously.

That is, the phase comparator 2 of the second embodiment
Similarly to the phase comparator 17 of the first embodiment, 8 also reduces the detection discontinuity of the phase delay signal U or the phase advance signal D by shifting the phase of the reference signal R or the fluctuation signal V. Even if the frequencies of the reference signal R and the fluctuation signal V are different and the phase difference is sequentially displaced in one direction, the signals D and U of the phase difference are generated.
One of them is output substantially continuously and is not output alternately, and when the PLL circuit is formed, the synchronous acquisition is not pulled to higher frequencies.

Further, in the phase comparator 28 of the present embodiment, the reference signal R and the fluctuation signal V are logic signals having a duty ratio of 50 (%), and these signals R and V are inverters 29 which are knot circuits. , 30 so that the phase is "+"
The signals R bar and V bar shifted by π ″ are easily generated with a simple structure.

Further, the D-FF 35 has a phase delay signal U
When the reference signal R is input when is ON, it is determined that the phase delay signal U exceeds "+ 2π", and the D-FF 36
Determines that the phase lead signal D exceeds “−2π” when the fluctuation signal V is input when the phase lead signal D is “ON”, these determinations are surely executed with a simple structure. It In this embodiment, the inverted signals R bar and V bar are input to the D-FFs 35 and 36. This is because the phase comparator 26 detects the falling edge, whereas the D-FF 35 and 36 receives the inverted signals.
This corresponds to the detection of rising edges 35 and 36.

Incidentally, the phase comparator 28 of the second embodiment.
Corresponds to the above-described phase comparator 17 of the first embodiment specifically disclosed by a TTL circuit. However, the present invention is not limited to the above embodiment, and can be realized by various circuits as long as they are logically equivalent.

Next, a third embodiment of the present invention will be described below with reference to FIG. First, the PLL circuit 3 of this embodiment
7 has the phase comparator 28 described above as the second embodiment of the present invention. The output section 20 of the phase comparator 28,
A charge pump 38 is connected to the charge pump 21, and the charge pump 38 has a loop filter LPF3.
9 is connected. A motor driver 40 is connected to the LPF 39, and a drive motor 41 is connected to the motor driver 40. This drive motor 41
A rotation angle sensor 42, which is a speed detecting means for detecting the rotation speed, is connected to the rotation angle sensor 42.
Is the input portion 19 of the fluctuation signal V of the phase comparator 28.
It is connected to the. The rotation angle sensor 42 is, for example, an FG (Frequency Generator) or a rotary encoder (both not shown).

In such a configuration, the PL of this embodiment is
The L circuit 37 rotationally drives the drive motor 41 at a rotation speed synchronized with the frequency of the reference signal R.

More specifically, when the charge pump 38 converts the output signals U and D of the phase comparator 28 from digital to analog, the LPF 39 filters this output signal. Next, since the motor driver 40 outputs drive power corresponding to this output voltage, the drive motor 41 is rotationally driven by this drive power. At this time, since the rotation angle sensor 42 feeds back the fluctuation signal corresponding to the rotation speed of the drive motor 41 to the phase comparator 28 as the fluctuation signal V, the phase comparator 28 outputs the fluctuation signal V and the reference signal R. To the charge pump 38 as the phase delay signal U or the phase advance signal D.

As described above, the PLL circuit 37 feedback-controls the drive motor 41 to the number of revolutions synchronized with the frequency of the reference signal R to drive the rotation, but the phase comparator 28
Can stably output the phase delay signal U and the phase advance signal D substantially continuously as described above, and this correspondence can be achieved even if the one-to-one correspondence relationship between the reference signal R and the fluctuation signal V is broken. The relationship can be quickly restored. Therefore, the PLL
Even with the circuit 37, the drive motor 41 can be stably and substantially continuously driven, and the synchronous acquisition of the rotation speed of the drive motor 41 can be quickly completed.

Since the change in the rotation speed of the drive motor 41 causes vibration and noise and also shortens the life of the mechanical system, it is extremely difficult to quickly stabilize the rotation speed of the drive motor 41 as described above. preferable. The PL of this embodiment is
When the phase difference between the reference signal R and the fluctuation signal V falls within the range of "± 2π", the L circuit 37 will thereafter function like a conventional PLL circuit.

Next, a fourth embodiment of the present invention will be described below with reference to FIGS. 7 and 8. With respect to the PLL circuit 43 shown in this embodiment, the same parts as those of the PLL circuit 37 described above are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the PLL circuit 43 of the present embodiment is shown in FIG.
As shown in, the LPF 39 has a voltage controlled oscillator VC
The O44 is connected, and the frequency divider 45 connected to the VCO 44 is connected to the input portion 19 of the fluctuation signal V of the phase comparator 28. Therefore, the motor driver 40
The drive motor 41 and the rotation angle sensor 42 are not provided. The VCO 44 generates an output signal O having an oscillation frequency corresponding to the output voltage of the LPF 39, and the frequency divider 45 divides the output signal O of the VCO 44 by an even number and then outputs it to the phase comparator 28. It is set to output as a fluctuation signal.

In such a configuration, the PL of this embodiment is
In the L circuit 43, the charge pump 38 converts the output signals U and D of the phase comparator 28 from digital to analog, and LP
When F39 filters, the VCO 44 generates an output signal O having an oscillation frequency corresponding to this output voltage and outputs it to the outside. Then, the frequency divider 45 divides the output signal O of the VCO 44 by an even number and feeds it back to the phase comparator 28 as the fluctuation signal V. Therefore, the phase comparator 28 outputs the fluctuation signal V and the reference signal R. The phase difference is output as a phase delay signal U and a phase advance signal D.

The PLL circuit 43 of the present embodiment outputs the frequency signal synchronized with the reference signal R as described above, but the phase comparator 28 quickly completes the synchronization acquisition as described above, and therefore the PLL circuit. Even at 43, the synchronization acquisition can be completed quickly.

In the PLL circuit 43 of this embodiment, V
Since the frequency divider 45 divides the output signal O of the CO 44 by an even number to obtain the fluctuation signal V of the phase comparator 28, as shown in FIG. 8, the phase comparator 28 causes the phase comparator 28 to output the first reference signal R and the second reference signal R. Signal R
Whichever of the bars produces the output signals U and D, the output signal O is the same. Similarly, the output signal O is the same regardless of whether the signals U and D are generated by the first fluctuation signal V or the first fluctuation signal V bar. That is, the phase comparator 28
Since the switching operation of 1 does not affect the output signal O of the PLL circuit 43, the operation of the PLL circuit 43 is stable and it is not necessary to correct the output signal O.

Next, a fifth embodiment of the present invention will be described below with reference to FIGS. 9 and 10. Regarding the PLL circuit 46 and the phase comparator 47 shown in the present embodiment, the same parts as those of the PLL circuit 54 and the phase comparator 28 described above will be denoted by the same names and reference numerals and detailed description thereof will be omitted.

First, in the PLL circuit 46 of this embodiment, as shown in FIG. 9, the frequency divider 48 divides the output signal O of the VCO 44 by an odd number and then outputs it to the phase comparator 47 as a fluctuation signal. . The output part of the VCO 44 is divided into two parts, and one side is provided with an inverter 49 which is a signal converting means. Therefore, the inverter 49 shifts the phase of the output signal O of the VCO 44 by “π” as the first output signal O. The second output signal O bar is generated.

A switching circuit 50 which is an output selecting means for selectively outputting one of these output signals O and O-bar.
Are provided in the switching circuit 50, and the output section 5 of the selection signals Sr and Sv provided in the phase comparator 47 is provided in the switching circuit 50.
1 is connected. Therefore, in the switching circuit 50, the phase comparator 47 is selected depending on the combination of the first reference signal R and the first fluctuation signal V or the combination of the second reference signal R bar and the second fluctuation signal V bar. When the phase difference is output, the first output signal O is selectively output. Further, the switching circuit 50 includes the phase comparator 4
If 7 outputs the phase difference by the combination of the first reference signal R and the second fluctuation signal V or the combination of the second reference signal R bar and the first fluctuation signal V, the second output signal O bar is selectively output.

In such a configuration, the PL of this embodiment is
In the L circuit 46, the charge pump 38 converts the output signals U and D of the phase comparator 47 from digital to analog and outputs L
When the PF 39 filters, the VCO 44 generates the output signal O having the oscillation frequency corresponding to this output voltage.
Then, the frequency divider 48 divides the output signal O of the VCO 44 by an odd number and feeds it back to the phase comparator 47 as the fluctuation signal V. Therefore, the phase comparator 47 compares the fluctuation signal V with the reference signal R. The phase difference is output as a phase delay signal U and a phase advance signal D.

However, the PLL circuit 46 of this embodiment is
Since the frequency divider 48 divides the output signal O of the CO 44 by an odd number to obtain the fluctuation signal V of the phase comparator 47, when the phase comparator 47 uses the first reference signal R as shown in FIG. And the case where the second reference signal R bar is used, the phase of the output signal O is different by “π”. This also applies to the fluctuation signals V, V bar, and these signals R, R bar,
The output signal O changes depending on the combination of V and V bar.
Therefore, in the PLL circuit 46 of this embodiment, the output signal O is used as the first reference signal O and the second reference signal O bar having a phase difference of "π" is generated by the inverter 49, and these reference signals O and O bar are generated. The output signal O is always made to be the same by selectively outputting one of them according to the operation of the phase comparator 47.

More specifically, since the phase comparator 47 selects one of the first reference signal R and the second reference signal R bar for signal output and outputs the selection signals Sr and Sv, the switching circuit 50 analyzes the contents of the selection signals Sr, Sv,
The first output signal O is output when the phases of the reference signal R and the fluctuation signal V are both not changed or both are changed, and one of the reference signal R and the fluctuation signal V is changed. If so, the second output signal O bar is output.

In addition, the phase comparators 17, 28, 4 described above
Since the output characteristic 7 is the same as that of a general memory type phase comparator, it can be treated as a memory type phase comparator. For example, the phase comparator of the present embodiment is combined with the phase comparator (not shown) filed by the applicant as Japanese Patent Application No. 6-209724, and in the initial state, the phase comparator of the present embodiment performs synchronization acquisition. It is possible to complete quickly, and thereafter, maintain good synchronization acquisition by the phase comparator of the above application.

[0085]

In the phase comparison method according to the first aspect of the present invention, the reference signal is output by the signal output means, the phase difference of the fluctuation signal with respect to the reference signal is detected by the signal comparison means, and the phase difference is "+ 2π". When it exceeds, the reference variable means shifts the phase of the reference signal by "+ π", and when the phase difference exceeds "-2π", the fluctuation variable means shifts the phase of the fluctuation signal by "+ π". By doing so, even if the one-to-one correspondence between the reference signal and the fluctuation signal is broken, this correspondence can be quickly recovered, and the detection of the phase delay and the phase lead can be made stable and substantially continuous. You can

A phase comparator according to a second aspect is provided with signal output means for outputting a reference signal, and with signal comparison means for detecting the phase difference of the fluctuation signal with respect to the reference signal, and the detected phase difference is "+ 2π". If the reference variable means for shifting the phase of the reference signal by "+ π" is exceeded, the fluctuation variable shifts the phase of the fluctuation signal by "+ π" when the detected phase difference exceeds "-2π". By providing the means, even if the one-to-one correspondence between the reference signal and the fluctuation signal is broken, this correspondence can be quickly recovered, and the detection of the phase delay and the phase lead can be stably performed substantially continuously. Can be made.

In the phase comparator according to the present invention, the signal comparison means outputs the phase difference of the fluctuation signal leading with respect to the reference signal as a phase lead signal and the fluctuation signal delayed with respect to the reference signal. The phase difference of is output as a phase delay signal, and the reference variable means is used when the phase delay signal is "ON".
When the reference signal is input, the phase delay signal becomes "+ 2π".
Excess reference signal of the phase "+ [pi" only shifted as variation varying means, varying when the phase lead signal is "ON"
When a motion signal is input, the phase advance signal exceeds "-2π".
By shifting the phase of the fluctuating signal by "+ π", the phase difference between the reference signal and the fluctuating signal is "± 2".
Since it is possible to easily detect that the value exceeds π ″, the operations of the reference varying unit and the variation varying unit can be reliably executed at appropriate timings.

In the phase comparator according to the fourth aspect, the signal output means outputs the reference signal as a logic signal having a duty ratio of 50 (%), and the reference varying means inverts the reference signal by a knot circuit to phase Is shifted by "+ π", the phase of the reference signal can be shifted with a simple structure. Therefore, the structure of the phase comparator can be simplified and the productivity can be improved.

A PLL circuit according to a fifth aspect is the PLL circuit according to the second aspect.
The phase comparator described in 3 or 4, a charge pump for converting the output signal of the phase comparator from digital to analog, a loop filter for filtering the output signal of the charge pump, and an output voltage of the loop filter are provided. By having a voltage controlled oscillator that generates an output signal of the oscillation frequency and a frequency divider that divides the output signal of this voltage controlled oscillator by an even number and then outputs it as a fluctuation signal to the phase comparator, synchronization acquisition is achieved. It can be completed promptly due to the characteristics of the phase comparator, and the variable phase of the phase comparator does not affect the output signal, so that a PLL circuit with a stable output signal can be obtained without requiring special correction means.

According to a sixth aspect of the PLL circuit, a charge pump for converting the output signal of the phase comparator from digital to analog, a loop filter for filtering the output signal of the charge pump, and an output voltage of the loop filter are provided. A voltage-controlled oscillator that outputs a signal of the corresponding oscillation frequency, a frequency divider that divides the output signal of this voltage-controlled oscillator by an odd number, and then outputs it as a fluctuation signal to the phase comparator, and an output signal of the voltage-controlled oscillator. The signal converting means for generating the second output signal whose phase is shifted by "π" as the first output signal, and the second output signal only when the phase comparator varies one phase of the reference signal and the fluctuation signal. And the output selection means for selectively outputting the signal, the synchronous acquisition can be completed more quickly by the characteristics of the phase comparator, and The output signal of the voltage controlled oscillator by a variable is changed but the output signal of the output selection means does not change, the output signal can be obtained a stable PLL circuit.

A PLL circuit according to a seventh aspect is the PLL circuit according to the second aspect.
Corresponding to the phase comparator described in 3 or 4, a charge pump that converts the output signal of this phase comparator from digital to analog, a loop filter that filters the output signal of this charge pump, and the output voltage of this loop filter. Motor driver that outputs drive power by a motor, a drive motor that is driven by the drive power that the motor driver outputs, and a speed detection unit that detects the rotation speed of the drive motor and outputs a corresponding fluctuation signal to the phase comparator. Since the synchronous acquisition can be completed quickly by the characteristics of the phase comparator, the rotational speed of the drive motor can be stabilized quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase comparator according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the correlation between various signals of the phase comparator.

FIG. 3 is a characteristic diagram showing an output characteristic of a phase comparator.

FIG. 4 is a block diagram showing a phase comparator according to a second embodiment of the present invention.

FIG. 5 is a time chart showing the correlation of various signals of the phase comparator.

FIG. 6 is a block diagram showing a PLL circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a PLL circuit according to a fourth embodiment of the present invention.

FIG. 8 is a time chart showing the relationship between the reference signal and the output signal of the PLL circuit.

FIG. 9 is a block diagram showing a PLL circuit according to a fifth embodiment of the present invention.

FIG. 10 is a time chart showing the relationship between the reference signal and the output signal of the PLL circuit.

FIG. 11 is a circuit diagram showing a phase comparator of a conventional example.

FIG. 12 is a time chart showing the relationship of various signals of the phase comparator.

FIG. 13 is a block diagram showing a state in which a charge pump and an LPF which is a loop filter are connected to the phase comparator.

FIG. 14 is a characteristic diagram showing an output characteristic of a phase comparator.

FIG. 15 is a time chart showing the relationship of various signals of the phase comparator.

FIG. 16 is a time chart showing the relationship of various signals of the phase comparator.

[Explanation of symbols]

17, 28, 47 Phase comparator 26 Signal comparison means 29,30 knot circuit 37, 43, 46 PLL circuit 38 Charge pump 39 loop filter 40 motor driver 41 Drive motor 42 Speed detection means 44 Voltage controlled oscillator 45,48 frequency divider 49 Signal conversion means 50 Output selection means

Claims (7)

(57) [Claims] 1. A memory-type phase comparator having a memory element, wherein a reference signal is output by a signal output means, and a phase difference of a fluctuation signal with respect to the reference signal is detected by a signal comparison means, and this phase difference is "+ 2π". When the phase difference exceeds "-2π", the phase of the reference signal is shifted by "+ π" by the reference variable means when the phase difference exceeds "-2π". A phase comparison method characterized by the above. 2. A memory type phase comparator having a memory element, wherein signal output means for outputting a reference signal is provided, signal comparison means for detecting a phase difference of a fluctuation signal with respect to the reference signal is provided, and the detected phase difference is provided. Is provided with reference variable means for shifting the phase of the reference signal by "+ π" when exceeds "+ 2π", and the phase of the fluctuation signal is only "+ π" when the detected phase difference exceeds "-2π". A phase comparator characterized in that a variation varying means for shifting is provided. 3. The signal comparing means outputs the phase difference of the fluctuation signal leading with respect to the reference signal as a phase lead signal and the phase difference of the fluctuation signal delayed with respect to the reference signal as the phase delay signal. The reference variable means outputs the phase when the reference signal is input when the phase delay signal is "ON".
If the delay signal exceeds "+ 2π", the phase of the reference signal is shifted by "+ π", and the fluctuation changing means receives the fluctuation signal when the phase advance signal is "ON".
3. The phase comparator according to claim 2, wherein the phase of the fluctuating signal is shifted by "+ .pi." If the only signal exceeds "-2.pi." . 4. The signal output means outputs the reference signal as a logic signal having a duty ratio of 50 (%), and the reference changing means inverts the reference signal by a knot circuit to set the phase to "+".
4. The method according to claim 2, wherein the shift is performed by π ″.
The described phase comparator. 5. The phase comparator according to claim 2, 3 or 4, a charge pump for converting an output signal of the phase comparator from digital to analog, and a loop filter for filtering an output signal of the charge pump. A voltage-controlled oscillator that generates an output signal with an oscillation frequency corresponding to the output voltage of this loop filter, and a frequency divider that divides the output signal of this voltage-controlled oscillator by an even number and then outputs it as a fluctuation signal to the phase comparator. And a PLL circuit. 6. The phase comparator according to claim 2, 3 or 4, a charge pump for converting the output signal of the phase comparator from digital to analog, and a loop filter for filtering the output signal of the charge pump. A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the output voltage of the loop filter; and a frequency divider that divides the output signal of the voltage-controlled oscillator by an odd number and then outputs it as a fluctuation signal to the phase comparator. , A signal conversion means for generating a second output signal whose phase is shifted by “π” by using the output signal of the voltage controlled oscillator as a first output signal, and the phase comparator for determining one phase of the reference signal and the fluctuation signal. Output selecting means for selectively outputting the second output signal only when variable,
A PLL circuit having: 7. The phase comparator according to claim 2, 3 or 4, a charge pump for converting an output signal of the phase comparator from digital to analog, and a loop filter for filtering the output signal of the charge pump. A motor driver that outputs drive power corresponding to the output voltage of this loop filter, a drive motor that is driven by the drive power that this motor driver outputs, and the rotation speed of this drive motor are detected to generate a corresponding fluctuation signal. A PLL circuit, comprising: a speed detecting means for outputting to the phase comparator.