JPH09284128A - Phase comparison method, phase comparator, pll circuit and motor controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the control method extending a frequency lock width with less noise component by obtaining the difference between a variation signal and plural reference signals with difference phase differences, comparing difference signals in outputs and selecting a difference signal providing a minimum phase difference at all times. SOLUTION: A 2nd reference signal R2 with a phase difference of πfrom the phase of a reference signal R is obtained from a phase variable circuit 10 inputting the reference signal R. The reference signal R and a variation signal V are given to a 1st phase comparator circuit 11, from which signals U1 , D1 are outputted. The 2nd reference signal R2 and the variation signal V are given to a 2nd phase comparator circuit 12, from which signals U2 , D2 are outputted. A selection circuit 13 that selects finally a 1st difference signal or a 2nd difference signal whose phase difference with respect to the reference signal R is within ±2$π gives a switching signal to a changeover circuit 14. The changeover circuit 14 acts like an output means that selects the 1st difference signal or the 2nd difference signal finally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison method, a phase comparator, a PLL circuit and a motor control device used in a synchronous circuit, a copying machine, a facsimile, a printer, etc., and particularly, a synchronization acquisition time in the motor control is shortened. The present invention relates to a phase comparison method, a phase comparator, a PLL circuit, and a motor control device.

[0002]

2. Description of the Related Art Conventionally, PLL circuits have been used in a wide variety of fields from wired / wireless communication to motor control. For the PLL circuit, a memory type phase comparator having a storage element inside or a non-memory type phase comparator having no storage element inside is usually used.

FIG. 15 shows an example of the configuration of a conventional digital memory type phase comparator. The memory type phase comparator 150 has an input unit 15 for inputting a reference signal R and a fluctuation signal V.
1, 152 and output units 153 and 154 for the phase delay signal U and the phase advance signal D, and are composed of a combination of a large number of NAND gates 155 to 163. In the phase comparator 150, the NAND gates 156 and 157 and the NAND gate 15 connected in a loop form.
RS-flip-flops F1 and F2 functioning as storage elements are formed by the elements 8 and 159.

The memory type phase comparator 15 having such a configuration
At 0, when the fluctuation signal V lags the reference signal R as shown in FIG. 16 (a), the phase delay signal D is generated. On the other hand, when the fluctuation signal V leads the reference signal R as shown in FIG. 16B, the phase lead signal D is generated.

Then, as shown in FIG. 17, a charge pump 170 and a low pass filter (LPF) 171 are connected to the phase comparator 150 of FIG.
The phase lag signal U and the phase lead signal D output by 0 are converted into an analog voltage by the charge pump 170 and the LPF
By filtering with 171, it can be understood that the output voltage and the phase difference characteristic have a wide phase comparison range as shown in FIG. As is apparent from FIG. 18, the output voltage of the phase comparator 150 and the phase difference are −2π−
There is a linear relationship in the range of + 2π. Therefore,
It can be seen that the phase comparator 150 functions as a frequency comparator.

Here, the synchronization process of the PLL circuit includes a frequency pulling process and a phase pulling process. The pulling of the frequency of the PLL circuit using the non-memory type phase comparator is performed based on the DC component when the phase difference output vibrates largely in the lag and advance. Therefore, it takes a long time for synchronization, and the high-order frequency of the reference signal may be accidentally pulled in and locked.

On the other hand, a PLL using a memory type phase comparator
In the circuit, by functioning as a frequency comparator, it is possible to shorten the synchronization time and prevent the frequency from being pulled to a higher frequency.

However, the memory type phase comparator is based on the premise of the phase comparison that the reference signal and the fluctuation signal have a one-to-one correspondence. Therefore, if this correspondence is broken, For example, there arises a problem that the output becomes unstable due to noise for a long period of time. A PLL circuit for solving this problem is disclosed in JP-A-2-7012.
No. 4 discloses this. This PLL circuit is provided with a memory type phase comparator and a non-memory type phase comparator that can be switched, and uses a memory type phase comparator with a wide phase comparison range in the initial state where the phase difference of signal frequencies is large. After the synchronization acquisition of the memory type phase comparator is completed, the non-memory type phase comparator that is strong against disturbance is selected.

However, in the circuit configuration, the output characteristics of the memory type and non-memory type phase comparators are different. Therefore, if these are simply switched, the operation of the PLL circuit becomes unstable due to the size of the output voltage difference. It was easy and required fine adjustment of the circuit such as gain.

Therefore, in order to solve these problems, the inventor of the present invention proposes as Japanese Patent Application No. 6-209724.
We proposed a non-memory type phase comparator and a PLL circuit using it. However, since this phase comparator and the PLL circuit use the conventional memory type phase comparator in the synchronization acquisition process, the synchronization acquisition time is the same as the conventional one.

In the synchronization acquisition process, the one-to-one correspondence between the reference signal R and the fluctuation signal V often breaks. FIG. 19 shows the input / output state of the digital memory type phase comparator viewed from the time waveform when the one-to-one correspondence is broken. FIG.
19A shows the case where the phase of the fluctuation signal V is behind the reference signal R, and FIG. 19B shows the case where the phase of the fluctuation signal V is ahead of the reference signal R. FIG.
9 (a) and FIG. 19 (b), the pulse marked with a circle is ignored in the phase difference output, and the one-to-one correspondence between the reference signal R and the fluctuation signal V is broken at the pulse. . Therefore, a discontinuous portion occurs in the phase delayed output U and the phase advanced output D until the next pulse arrives.
The occurrence of a discontinuous portion in the phase difference output means that the phase difference once decreases to around 0 in FIG. 18 when the phase difference of the fluctuation signal exceeds 2π with respect to the reference signal.

In order to solve the above-mentioned problems, the inventor of the present invention was further instructed by Japanese Patent Application No. 6-278703 and Japanese Patent Application No. 7-1.
No. 18107 proposed a phase comparator and a PLL circuit.

According to the phase comparator and the PLL circuit disclosed in Japanese Patent Application No. 6-278703, two or more stable points of the PLL circuit (PLL motor control circuit) are formed, and synchronization is achieved by pulling in to whichever is closer. The capture time (pull-in time) can be shortened.

Further, according to the phase comparator and the PLL circuit disclosed in Japanese Patent Application No. 7-118107, the wide phase comparison range remains unchanged as in the conventional memory type phase comparator.
The processing after the one-to-one correspondence has been lost can be changed to shorten the synchronization acquisition time (pull-in time).

[0015]

However, the phase comparator and the PLL circuit disclosed in the above-mentioned Japanese Patent Application No. 6-278703 are effective in the phase pull-in process, but the frequency pull-in is narrow because the phase comparison range is narrow. The problem is that the process is ineffective. That is, this phase comparator and P
The LL circuit is not suitable for the synchronization process of signals having a large frequency difference.

Further, the phase comparator and the PLL circuit disclosed in Japanese Patent Application No. 7-118107 have a great effect on the frequency pulling process, but they are complicated because they must be phase-shifted with respect to both the reference signal and the fluctuation signal. However, it is necessary to limit the reference signal and the fluctuation signal. That is, the input signal is duty 5
If it is 0%, the phase shift can be performed by the NOT circuit, but if it is different, a complicated circuit is required for the phase shift.

Therefore, in order to solve the above-mentioned problems, an object of the present invention is to shorten the synchronization acquisition time, particularly the synchronization acquisition time in motor control (make the synchronization pull-in faster).
A phase comparison method, a phase comparator, and a PLL circuit are provided.

[0018]

In order to achieve the above object, the phase comparison method according to claim 1 of the present invention compares the phase of the reference signal with the phase of the fluctuation signal to determine the fluctuation signal with respect to the phase of the reference signal. In a phase comparison method for obtaining a phase difference signal, the phase of the reference signal and the phase of the fluctuation signal are compared to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal as a first difference signal, Comparing the phase of the second reference signal obtained by shifting the phase of the reference signal by + π and the phase of the fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the second reference signal as a second difference signal; Of the first difference signal and the second difference signal, a signal having a phase difference of ± 2π with the reference signal or the second reference signal is output as a final difference signal.

The phase comparison method according to claim 2 of the present invention is a phase comparison method for comparing a phase of a reference signal and a phase of a fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, By comparing the phase of the reference signal and the phase of the fluctuation signal, a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is obtained as a first difference signal, and the phase of the reference signal and the phase of the fluctuation signal are calculated. Comparing the phases of the second fluctuation signal shifted by + π, the difference signal of the phase of the second fluctuation signal with respect to the phase of the reference signal is obtained as a second difference signal, and the difference signal of the first difference signal and the second difference signal is calculated. home,
A signal having a phase difference of ± 2π with respect to the reference signal is output as a final difference signal.

The phase comparison method according to claim 3 of the present invention is a phase comparison method for comparing a phase of a reference signal and a phase of a fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, When a plurality of fluctuation signals having different phases are input, a difference signal between the phases of the plurality of fluctuation signals and the reference signal is obtained, and when the phase difference of the difference signal currently being output exceeds a predetermined range, Among the plurality of difference signals, the difference signal having the smallest phase difference from the reference signal is selected and output.

The phase comparison method according to claim 4 of the present invention is a phase comparison method for comparing a phase of a reference signal and a phase of a fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, When a plurality of reference signals having different phases are input, the difference signals of the phases of the plurality of reference signals and the fluctuation signal are respectively obtained, and when the phase difference of the difference signals currently being output exceeds a predetermined range, Among the plurality of difference signals, the difference signal having the smallest phase difference from the fluctuation signal is selected and output.

The phase comparator according to claim 5 of the present invention is
In a phase comparator that compares the phase of the reference signal and the phase of the fluctuation signal and outputs a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, shifts the phase of the reference signal by + π to generate the second reference signal. The phase varying means for outputting is compared with the phase of the reference signal and the phase of the fluctuation signal, and a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is first calculated.
A first phase comparison means for outputting a difference signal and a phase of the second reference signal and a phase of the fluctuation signal are compared with each other, and a difference signal of the phase of the fluctuation signal with respect to the phase of the second reference signal is calculated as a second difference. The second phase comparison means for outputting as a signal and one of the first difference signal and the second difference signal having a phase difference of ± 2π with the reference signal or the second reference signal as a final difference signal. And a selective output means for selecting and outputting.

The phase comparator according to claim 6 of the present invention is
In a phase comparator that compares the phase of the reference signal and the phase of the fluctuation signal and outputs a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, shifts the phase of the fluctuation signal by + π to generate the second fluctuation signal. The phase varying means for outputting is compared with the phase of the reference signal and the phase of the fluctuation signal, and a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is first calculated.
A first phase comparison means for outputting a difference signal and a phase of the reference signal and a phase of the second fluctuation signal are compared with each other, and a difference signal of the phase of the second fluctuation signal with respect to the phase of the reference signal is a second difference. The second phase comparing means for outputting as a signal and the first difference signal and the second difference signal having a phase difference of ± 2π or less with respect to the reference signal are selected and output as a final difference signal. And a selective output means.

The phase comparator according to claim 7 of the present invention is
7. The phase comparator according to claim 5, wherein the first difference signal output from the first phase comparison means is a first phase lead signal indicating a phase lead of a fluctuation signal with respect to the reference signal, and the reference signal. A second phase difference signal output from the second phase comparison means is a phase advance of the fluctuation signal with respect to the second reference signal or the reference signal. A second phase lead signal indicating the phase advance of the second fluctuation signal with respect to the second fluctuation signal, and a second phase delay signal indicating the phase delay of the fluctuation signal with respect to the second reference signal or the phase delay of the second fluctuation signal with respect to the reference signal. In the state in which the first phase advance signal of the first difference signal or the second phase advance signal of the second difference signal selected as the final difference signal is ON, When the fluctuation signal or the second fluctuation signal input to the first phase comparison means or the second phase comparison means selected as the final difference signal becomes active, the first difference signal or the second difference signal It is determined that the phase difference of the difference signal exceeds + 2π, and the first phase delay signal of the first difference signal or the second phase delay signal of the second difference signal selected as the final difference signal is turned on. In the state where the first reference signal or the second reference signal input to the first phase comparison means or the second phase comparison means selected as the final difference signal is activated, It is determined that the phase difference between the difference signal or the second difference signal exceeds -2π.

The phase comparator according to claim 8 of the present invention is
In a phase comparator that compares the phase of a reference signal with the phase of a fluctuation signal and outputs a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, the reference signal, the first fluctuation signal, and the first fluctuation signal as input signals. A first fluctuation signal having a phase different from that of the first fluctuation signal and shifting the phase of the first fluctuation signal by + π to output a third fluctuation signal; Second phase varying means for shifting the phase by + π and outputting a fourth fluctuation signal, and the phase of the reference signal and the phase of the first fluctuation signal are compared, and the first fluctuation signal with respect to the phase of the reference signal. Of the second fluctuation signal with respect to the phase of the reference signal by comparing the phase of the reference signal and the phase of the second fluctuation signal with the first phase comparison means that outputs the difference signal of the phase as the first difference signal. The phase difference signal is output as the second difference signal. Comparing the phase of the reference signal with the phase of the third fluctuation signal and outputting the difference signal of the phase of the third fluctuation signal with respect to the phase of the reference signal as a third difference signal. Third phase comparing means for
Fourth phase comparison means for comparing the phase of the reference signal with the phase of the fourth fluctuation signal and outputting a difference signal of the phase of the fourth fluctuation signal with respect to the phase of the reference signal as a fourth difference signal; When the phase difference of the difference signal being output exceeds a predetermined range, the phase difference with the reference signal is the smallest among the first difference signal, the second difference signal, the third difference signal, and the fourth difference signal. Selection output means for selecting and outputting the difference signal.

The PLL circuit according to claim 9 of the present invention is
A PLL circuit for performing phase synchronization control, a phase comparator according to claim 5, 6 or 7, a charge pump for converting an output signal of the phase comparator from an analog signal to a digital signal, and an output of the charge pump. A loop filter for filtering a signal, a voltage-controlled oscillator for generating an output signal having an oscillation frequency corresponding to the output voltage of the loop filter, and an output signal of the voltage-controlled oscillator divided by an even number to obtain the variable signal. And a frequency divider for outputting to the phase comparator.

According to a tenth aspect of the present invention, there is provided a motor control device for performing phase synchronization control of a motor, wherein the phase comparator according to the fifth, sixth or seventh aspect and the output signal of the phase comparator. Of the digital signal from a digital signal to an analog signal, a loop filter for filtering the output signal of the charge pump, a motor driver for driving the motor with a drive voltage corresponding to the output voltage of the loop filter, and a motor for the motor. And a speed detecting means for detecting a rotation speed and outputting a signal corresponding to the rotation speed as the fluctuation signal to the phase comparator.

According to an eleventh aspect of the present invention, in a motor control device for performing phase synchronization control of a motor, the phase comparator according to the eighth aspect and an output signal of the phase comparator are digital signals. A charge pump for converting into an analog signal, a loop filter for filtering an output signal of the charge pump, a motor driver for driving the motor with a drive voltage according to the output voltage of the loop filter, and a rotation speed of the motor And a speed detecting means for outputting the first fluctuation signal and the second fluctuation signal corresponding to the rotation speed to the phase comparator.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram of a phase comparator according to a first embodiment of the present invention. This phase comparator shifts the phase of the reference signal R by + π
The phase variable circuit 10 as the phase varying means of the present invention that outputs the reference signal R ₂ is compared with the phase of the reference signal R and the phase of the fluctuation signal V, and the difference signal between the phase of the fluctuation signal and the phase of the reference signal R is compared. Is output as a first difference signal.
A first phase comparator circuit 11 as a phase comparison means compares the phase of the second reference signal R ₂ in phase with the variation signal, a phase difference signal of the variation signal V to the second reference signal R ₂ phase first The second phase comparison circuit 12 as the second phase comparison means of the present invention that outputs the two difference signals, and the phase of the reference signal R or the second reference signal R _{2 of} the first difference signal and the second difference signal Based on the selection result of the selection circuit 13 as the selection output means of the present invention that selects a difference within ± 2π as the final difference signal, the final difference signal is first
It comprises a switching circuit 14 as a selective output means of the present invention for switching to either the difference signal or the second difference signal.

The memory type phase comparator shown in FIG. 15 can be used for the first and second phase comparison circuits 11 and 12 of the phase comparator. When the output of the memory type phase comparator of FIG. 15 is converted into a voltage through the charge pump and LPF, the relationship of output voltage-phase difference shown in FIG. 18 can be obtained.

The input of the phase comparator shown in FIG. 1 is the reference signal R and the fluctuation signal V, and the outputs are the phase delay signal U and the phase lead signal D. The output formats are the same. Therefore, it can be replaced and combined with the conventional one very easily. Further, since the inside of the phase comparator is also a logical operation, as will be described later, TTL (Transistor-Transistor Lo)
gic) circuit and the like.

The operation of the phase comparator of FIG. 1 will be described at the same time as the phase comparator of the second embodiment described below.

[Second Embodiment] FIG. 2 is a block diagram of a phase comparator according to a second embodiment. This phase comparator shifts the phase of the fluctuation signal V by + π to generate the second fluctuation signal V ₂
And the phase of the reference signal R and the phase of the fluctuation signal V are compared, and the difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal R is the first difference. The first phase comparison circuit 21 as the first phase comparison means of the present invention which outputs as a signal is compared with the phase of the reference signal R and the phase of the second fluctuation signal V ₂ , and the second fluctuation with respect to the phase of the reference signal R is compared. The second phase comparison means of the present invention outputs the difference signal of the phase of the signal V ₂ as the second difference signal.
Selection as the selection output means of the present invention for selecting, as the final difference signal, the phase comparison circuit 22 and one of the first difference signal and the second difference signal having a phase difference of ± 2π with respect to the reference signal R. It comprises a circuit 23 and a switching circuit 24 as selection output means of the present invention for switching the final difference signal to either the first difference signal or the second difference signal based on the selection result of the selection circuit 13.

The phase comparator of the second embodiment has the phase variable circuit 20 provided on the variable signal V side, and the other structure is the same as that of the phase comparator of the first embodiment described above. .

When the phase variable circuits 10 and 20 in the phase comparators of the first and second embodiments are constructed of NOT circuits, there is a constraint that either the reference signal R or the input signal of the fluctuation signal V has a duty of 50%. Will be needed. However, since the input signal (reference signal R or fluctuation signal V) that is easily restricted differs depending on the circuit to which the phase comparator is connected, as shown in other embodiments described later, the first embodiment
Alternatively, the two phase comparators may be used properly.

Next, the first embodiment having the above-mentioned configuration
The operation of the phase comparators 2 and 2 will be described. For convenience of explanation, the operation will be described using the phase comparator of the first embodiment shown in FIG.

FIG. 3 shows the phase comparator of the first embodiment shown in FIG.
9 shows the output result when the reference signal R and the fluctuation signal V similar to those of No. 9 are input. In the phase comparator of the first embodiment, the second reference signal R ₂ having the phase difference π is generated based on the reference signal R input by the phase variable circuit 10. Then, the reference signal R and the second reference signal R ₂ are compared in phase with the fluctuation signal V by the first phase comparison circuit 11 and the second phase comparison circuit 12, respectively.

FIG. 3A shows the output when the phase of the fluctuation signal V is delayed with respect to the reference signal R. FIG.
In (a), the switching circuit 14 first selects the difference signal of the first phase comparison circuit 11 as the final difference signal of the phase comparator. That is, the phase delay signal U = U ₁ of the phase comparator. The switching circuit 14 uses the reference signal R
When the selection circuit 13 detects that the phase difference between the fluctuation signal V and the fluctuation signal V exceeds 2π, that is, when it is detected that the one-to-one correspondence between the pulses of the reference signal R and the fluctuation signal V is broken. The final difference signal of the comparator is switched to the difference signal of the second phase comparison circuit 12. The switching of the phase difference output by the switching circuit 14 will be described below.

First, it is assumed that the difference signal of the first phase comparison circuit 11 is selected as the final difference signal of the phase comparison circuit, that is, the phase delay signal U. In FIG. 3A, when the pulse of the reference signal R marked with ◯ is input, the phase lag signal U is active (Low), so the pulse of ◯ is 1: 1 with the fluctuation signal V. It will be out of correspondence. That is, this pulse is ignored in the phase delay signal U. Therefore, the selection circuit 13 detects this and outputs the selection signal S to the switching circuit 14.
Then, the switching circuit 14 switches the final difference signal of the phase comparator from the first phase comparison circuit 11 to the difference signal of the second phase comparison circuit 12 based on the selection signal S. As a result, the phase delay signal U becomes U ₂ which is the difference signal of the fluctuation signal V with respect to the second reference signal R ₂ .

Similarly, when the difference signal of the second phase comparison circuit 12 is selected as the final difference signal of the phase comparator, the □ mark is added while the phase delay signal U is active (Low). When the second reference signal R ₂ is input, this pulse deviates from the one-to-one correspondence with the fluctuation signal V. Therefore, the selection circuit 13 detects this and outputs the selection signal S to the switching circuit 14. And
The switching circuit 14 switches the final difference signal of the phase comparator from the second phase comparison circuit 12 to the difference signal of the first phase comparison circuit 11 based on the selection signal S. As a result, the phase delay signal U becomes U ₁ which is the difference signal between the reference signal R and the fluctuation signal V.

By the operation of the phase comparator described above, the reference signal R and the fluctuation signal V as shown in FIG.
It is possible to mitigate the discontinuous portion of the phase delay signal U immediately after the one-to-one correspondence is broken.

Further, FIG. 3B shows the output when the phase of the fluctuation signal V leads the reference signal R.
In FIG. 3B, it is assumed that the difference signal of the first phase comparison circuit 11 is first selected as the phase advance signal D of the phase comparison circuit. That is, the phase lead signal D = D ₁ .

It is assumed that a pulse of the fluctuation signal V marked with a circle is input as the reference signal R. Since the phase lead signal D at that time is active (Low), the selection circuit 1
3 judges that the one-to-one correspondence between the reference signal R and the fluctuation signal V is broken, and outputs the selection signal S to the switching circuit 14. The switching circuit 14 outputs the final difference signal of the phase comparator from the first phase comparison circuit 11 to the second phase comparison circuit 12 based on the selection signal S.
Switch to the difference signal of. That is, the phase lead signal D = D
It becomes ₂ .

Similarly, when the difference signal of the second phase comparison circuit 12 is selected as the final difference signal of the phase comparator, it is assumed that the fluctuation signal V marked with □ is input. The phase lead signal D at that time is active (Lo
Therefore, the selection circuit 13 determines that the one-to-one correspondence between the second reference signal R ₂ and the fluctuation signal V is broken, and outputs the selection signal S to the switching circuit 14. The switching circuit 14 uses the selection signal S
Based on the above, the final difference signal of the phase comparator is switched from the second phase comparison circuit 12 to the difference signal of the first phase comparison circuit 11. That is, the phase lead signal D = D ₁ .

By the operation of the phase comparator described above, the discontinuous portion of the phase lead signal D immediately after the one-to-one correspondence between the reference signal R and the fluctuation signal V as shown in FIG. 19B is broken. Can be relaxed.

In FIG. 19B, the fluctuation signal V
The pulse marked with a black square indicates that the second reference signal R ₂ and the fluctuation signal V are out of one-to-one correspondence. However, when the pulse of the fluctuation signal V is input, since the difference signal of the first phase comparison circuit 11 is selected as the final difference signal of the phase comparator, the phase advance signal D is not affected and the switching is performed. The circuit 14 does not switch the difference signals of the phase comparison circuits 11 and 12.

In FIG. 4, for comparison with the output voltage-phase difference characteristic of the conventional phase comparator, a charge pump and a low pass filter (LPF) are connected to the phase comparator of the first embodiment (FIG. 17). The output voltage-phase difference characteristic obtained by converting the phase difference output of the phase comparator into a voltage is shown.

In FIG. 4, is the first phase comparison circuit 11
Is a phase difference characteristic when is selected. Reference signal R
When the phase delay of the fluctuation signal V with respect to the output signal exceeds 2π, the output of the second phase comparison circuit 12 is selected by the selection circuit 13 and the switching circuit 14 instead of the output of the first phase comparison circuit 11 as described above. The phase difference characteristic switches from to. In the conventional phase comparator, when the phase delay exceeds 2π, the phase difference drops to near 0 (see FIG. 18), but in the case of the phase comparator of the first embodiment, as shown in FIG. The phase difference is converted to near π.

When the phase lead of the fluctuation signal V with respect to the reference signal V exceeds 2π while the first phase comparison circuit 11 is selected, the output of the first phase comparison circuit 11 is replaced by the second phase. The output of the phase comparison circuit 12 is selected by the selection circuit 13 and the switching circuit 14, and the phase difference characteristic is switched to. The phase difference at this time is converted to around -π as shown in FIG. The phase difference characteristic is
Since the phase difference is separated by 2π or more, both are substantially the same.

On the other hand, when the phase delay or the phase advance exceeds 2π when the difference signal of the second phase comparison circuit 12 is selected, the first phase comparison circuit 12 is replaced with the output of the second phase comparison circuit 12. The difference signal 11 is the selection circuit 13 and the switching circuit 1.
4 is selected. That is, the phase difference characteristic switches from or to.

Based on FIG. 5, it will be described that the phase comparator of the first embodiment has an effect that the synchronization time can be shortened and stable pull-in can be achieved not only in the phase pull-in process but also in the frequency pull-in process. In Figure 5,
An output example when the frequency of the fluctuation signal V is slightly lower than the reference signal R is shown. FIG. 5A shows a conventional memory type phase comparator, and FIG. 5B shows the first embodiment. This is the output of the phase comparator.

The phase corresponds to the integral of frequency. Therefore, when there is a frequency difference, the phase difference gradually increases with time and the output of the phase comparator increases. However, when the phase difference exceeds 2π, the reference signal R and the fluctuation signal V are in a one-to-one relationship.
Since the correspondence is broken, the output of the phase comparator drops. That is,
The output voltage based on the phase difference between the reference signal R and the fluctuation signal V becomes a sawtooth wave as shown in FIG.

In the phase comparators of the first embodiment and the conventional example, only one of the phase lead signal and the phase delay signal is output, and the phase difference leads to lead or lag like a non-memory type phase comparator. It does not swing and is not pulled into higher frequencies.

When the PLL circuit is constructed by using the phase comparator, the direct current component (feedback amount) contained in the output of the phase comparator acts on the frequency pull-in, and the noise component due to the one-to-one misalignment causes the frequency pull-in. It becomes an obstacle. Finally, the frequency can be synchronized by the action of a loop filter such as an LPF, but in order to suppress noise, the LPF
Since the frequency band must be narrowed and stable frequency pull-in cannot be performed, frequency synchronization takes time.

Comparing the characteristics of the conventional phase comparator shown in FIG. 5A with the characteristics of the phase comparator of the first embodiment shown in FIG. 5B, the phase comparison of the first embodiment is performed. The DC output (feedback amount) is obviously larger in the output of the device, and the noise component causing the one-to-one mismatch is smaller. That is, when a similar PLL circuit is configured, the phase comparator of the first embodiment has a larger component that acts on the frequency pull-in, the frequency pull-in is performed more strongly, and the noise component makes the operation unstable. Few. Therefore, more stable and faster frequency synchronization can be achieved, and since the noise component is originally small, the LPF band can be widened.

[Third Embodiment] FIG. 6 shows a circuit example in the case where the phase comparator of the first embodiment is specifically configured by a TTL circuit. In this circuit, 60 and 63 are N
NOT circuit composed of AND gates, 61 is a first phase comparison circuit, 62 is a second phase comparison circuit, 64, 65 and 66
Is a D-flip flop, 67 is a NAND gate, 68
Is a selector circuit.

When each circuit configuration shown in FIG. 6 is made to correspond to each block of the phase comparator shown in FIG. 1, the NOT circuit 60 is the phase variable circuit 10 and the first phase comparison circuit 61 is the first phase comparison circuit 11. In addition, the second phase comparison circuit 62 includes the second phase comparison circuit 12, the NOT circuit 63, and the D-flip-flop 6
4, 65 and 66, the NAND gate 67, and the portion of the TTL selector 68 from the input terminals 3A and 3B to the output terminal 3Y are the selection circuit 13, and the selector circuit 68 is the switching circuit 1.
It corresponds to 4 respectively.

The phase variable circuit 60 limits the reference signal R to a square wave with a duty of 50% and restricts the NAN.
It is configured by one NOT circuit 60 including a D gate. Therefore, the circuit configuration can be greatly simplified. Here, the reference signal R is limited to 50% duty in order to configure the phase variable circuit 10 with the NOT circuit 60.
Since it is possible to use a delay circuit or the like as the phase variable circuit 10, the input constraint is not always necessary.
In addition, the first and second phase comparison circuits 61 and 62 include the circuit shown in FIG.
A phase comparator similar to that shown in FIG.

Next, the operation of the phase comparator of the third embodiment will be described. FIG. 7 shows a signal waveform when the phase of the fluctuation signal V is delayed with respect to the reference signal R in the phase comparator of the third embodiment.

In this phase comparator, as shown in FIG. 7, the reference signal R'is used to switch the outputs of the first and second phase comparison circuits 61 and 62. Reference signal R '
The reference signal R and the second reference signal R ₂ whose phase is shifted by + π by the NOT circuit 60 (phase variable circuit) are input to the selector circuit 68, and either the reference signal R or the second reference signal R ₂ is input. Is selected and output by the selector 68. Specifically, the selector circuit 68
The discrimination signal S for switching the output of the
When the difference signal of the phase comparison circuit 61 is selected as the final difference signal, the second reference signal R _{2 is} set as the reference signal R ′.
Is selected, the discrimination signal S is Low, and the second phase comparison circuit 6
When the difference signal of 2 is selected as the final difference signal, the reference signal R is selected as the reference signal R ′. Then, the phase delay signal U is sampled using the rising edge of the reference signal R'as a clock.

In FIG. 7, the output levels of the first or second phase comparison circuits 61 and 62 and the reference signal R'are interchanged because the D-flip-flop used in this phase comparator rises. Detection, and the first and second phase comparison circuits 61 and 62 are falling detection,
This is because the detection directions of both pulses are opposite.
As the sampling timing, the pulse timings of the first and second phase comparison circuits 61 and 62 and the reference signal R or R ₂ input thereto are matched.

In FIG. 7, when the pulse of the reference signal V marked with a circle is input, the reference signal R'is output even though the phase delay signal U is active (Low). , The one-to-one correspondence between the reference signal R and the fluctuation signal V is broken, and the phase difference between the two exceeds + 2π. In such a case, the output S _U of the D-flip-flop 66 becomes Low, which makes it possible to detect that the one-to-one correspondence is broken.

Although not shown, even when the phase of the fluctuation signal V is advanced with respect to the reference signal R, the phase advance signal D is similarly sampled at the falling timing of the fluctuation signal V. . As a result of sampling, when the output SD of the D-flip-flop 64 becomes Low, it can be detected that the phase difference between the reference signal R and the fluctuation signal V exceeds -2π.

When the output S _U or S _{D of the} D-flip-flop 66 or 64 becomes Low, that is, the reference signal R
If the phase difference between the phase of the variation signal V to the phase of exceeds ± 2 [pi, rising output S _K of the NAND gate 67, Hig selection signal S inputted to the selector circuit 68
Swap h and Low. The selector circuit 68 switches the outputs of the first phase comparison circuit 61 and the second phase comparison circuit 62 based on the selection signal S. In this way, the switching timing of the first and second phase comparison circuits 61 and 62 can be easily obtained by using the phase difference output.

If the fall detection is unified, the NOT circuit and the reference signal need not be replaced.

By the phase comparator shown in FIG. 6 described above, switching of the input depending on the phase difference can be realized and the desired phase difference characteristic shown in FIG. 4 can be obtained. However, Figure 6
The circuit configuration of the phase comparator of is an example. That is,
Since logical operations are performed inside the phase comparator, different circuit configurations may be used as long as they are logically equal.

[Fourth Embodiment] FIG. 8 is a block diagram of a motor control device using the phase comparator of the third embodiment. This motor control device is connected to a reference signal generation circuit (not shown) that generates a reference signal R, receives the reference signal R and the fluctuation signal V, and outputs the phase difference between the reference signal R and the fluctuation signal V. The phase comparator 80 which detects the difference signal and outputs the difference signal, the charge pump 81 which converts the difference signal from the digital signal to the analog signal, the loop filter 82 which filters the analog signal, and the output voltage from the loop filter. A motor driver 83 that drives the motor 84 accordingly, and a speed detection circuit 85 that detects the rotation speed of the motor 84 and outputs a fluctuation signal V corresponding to the rotation speed. The fluctuation signal output from the speed detection circuit 85 V
Is fed back to the phase comparator 80. That is, this PLL motor control circuit outputs the FG to the reference signal R.
(Frequency Generator) or an output of a speed detection circuit 85 such as an encoder is synchronized to perform motor control with stable rotation accuracy.

This motor control device has a structure in which the output of the phase comparator 80 is converted into a voltage by the charge pump 81 and the loop filter 82, and the motor 84 is controlled by the output voltage. Therefore, there is no difference from the configuration of the motor control circuit using the conventional memory type phase comparator. Further, since the output format of the phase comparator 80 is the same, it can be handled in the same manner as the conventional memory type phase comparator, and further, the loop filter 82 can be designed in the same manner as the conventional one. is there.

Further, Japanese Patent Laid-Open No. 7-
In the phase comparator of No. 118107, since not only the reference signal R but also the fluctuation signal V is a signal with a duty of 50%, it is necessary to use an encoder with an output of 50% as a speed detection circuit.

However, according to the phase comparator of the present invention, it is only necessary to place a constraint of 50% duty on one side of the input signal. Therefore, in the fourth embodiment, only the reference signal R that can be easily realized is used. It was set to 50%. Therefore,
In the fourth embodiment, the duty 50 is changed to the conventional one.
Since it is not necessary to stick to%, various circuits can be selected as the speed detection circuit 85.

A motor controller was constructed using the phase comparator of the present invention and the conventional phase comparator, respectively, and an experiment of starting the motor from a stationary state was conducted. As a result, the circuit using the phase comparator of the present invention takes a shorter time until synchronization on average, and good results can be obtained. In the phase comparator of the present invention, the reason for the result is that the feedback amount for frequency pull-in is large and the noise component that is out of one-to-one correspondence is small as described in FIG. Further, in the phase comparator of the present invention, since the amount of feedback becomes extremely discontinuous, it is effective not only for pulling in the frequency but also for one-to-one correspondence deviation due to disturbance. Therefore, in the control of a motor having a large inertia, it is important to use the phase comparator of the present invention in the PLL motor control circuit because the frequency pull-in is important in the synchronization process.

After the fluctuation of the phase difference is within -2π to + 2π, the phase difference output is not switched in the phase comparator 80. Therefore, the phase comparator 80 is similar to the conventional memory type phase comparator. To work. That is, since the phase comparison range is wide, synchronization in a wide frequency range is possible.

In the motor control by the PLL circuit, the fluctuation of the number of revolutions of the motor until the synchronization is problematic in terms of noise. However, by using the circuit of the fourth embodiment, the synchronization time can be shortened and the noise can be reduced. There is also an effect that the problem can be alleviated.

[Fifth Embodiment] FIG. 9 shows a circuit example in the case where the phase comparator of the second embodiment is concretely configured by a TTL circuit. In this circuit, 90 and 93 are N
NOT circuit constituted by AND gate, 91 is a first phase comparison circuit, 92 is a second phase comparison circuit, 94, 95 and 96
Is a D-flip flop, 97 is a NAND gate, 98
Is a selector circuit.

When each circuit configuration shown in FIG. 9 is made to correspond to each block of the phase comparator shown in FIG. 2, the NOT circuit 90 becomes the phase variable circuit 20 and the first phase comparison circuit 91 becomes the first phase comparison circuit 21. , The second phase comparison circuit 92 includes a second phase comparison circuit 22, a NOT circuit 93, a D-flip-flop 9
4, 95 and 96, the NAND gate 97, and the selector circuit 98 from the input terminals 3A and 3B to the output terminal 3Y are the selection circuit 23, and the selector circuit 98 is the switching circuit 24.
It corresponds to each.

In the phase comparator of the fifth embodiment,
The variation signal V is constrained to have a duty of 50%, and the variation signal side is configured by the NOT circuit 90, and the variation signal V generates the second variation signal V ₂ . This phase comparator discriminates that the output is within ± 2π, similarly to the phase comparator of the third embodiment shown in FIG. 6, and when the output exceeds this range, the first and second phase comparator circuits The operation of switching the outputs of 91 and 92 is performed. Regarding the phase difference output of the phase comparator of the fifth embodiment, the characteristic shown in FIG. 4 can be obtained as in the phase comparator of the third embodiment.

[Sixth Embodiment] FIG. 10 shows a fifth embodiment.
FIG. 3 is a block diagram when the phase comparator of is used in a PLL phase lock circuit. The PLL phase locked loop circuit is connected to a reference signal generation circuit (not shown) that generates a reference signal R, and the reference signal R and the fluctuation signal V are input.
The phase comparator 100 described above that detects the phase difference between the phase of the fluctuation signal V and the phase of the reference signal R and outputs the difference signal.
, A charge pump 101 for converting the difference signal from a digital signal to an analog signal, a loop filter 102 for filtering the analog signal, and a voltage control oscillator (VCO) for outputting a signal having an oscillation frequency according to the output voltage of the loop filter. ) 103 and the output signal of the VCO 103, and divides this signal by an even number and then outputs it as a fluctuation signal V to the phase comparator 100.

The output form of the phase comparator 100 of the sixth embodiment is the same as that of the conventional memory type phase comparator. Therefore, the charge pump 101, the loop filter 102,
Phase comparator 10 through VCO 103 and frequency divider 104
The loop that feeds back to 0 can have the same configuration as a normal PLL circuit. Further, as described in the fifth embodiment, since the input signal (reference signal) R does not have the duty of 50%, the output O can be synchronized with the pulse-shaped reference signal R.

Further, the PLL phase locked loop circuit of the sixth embodiment uses the frequency divider 104 having a frequency division ratio of 2N. FIG. 11 shows an output example when the frequency division ratio is 2. FIG.
11A shows the case where the fluctuation signal V is synchronized with the input signal R, and FIG. 11B shows the case where the second fluctuation signal V ₂ is synchronized with the input signal R (the fluctuation signal V with the input signal R). Is synchronized with the phase shifted by π).

As is apparent from FIG. 11, when the fluctuation signal V is synchronized with the input signal R (FIG. 11A) and when the second fluctuation signal V ₂ is synchronized (FIG. 11B). In both cases, the output O does not change when the frequency division ratio is a multiple of 2. Therefore, when the frequency division ratio is 2N, the output terminal can have a simple structure. Also in the sixth embodiment, the effect of the phase comparator according to the present invention described with reference to FIG. 5 and the like is that the frequency can be pulled in quickly and the synchronization time is stable and short.

Further, in the case of a PLL circuit using a frequency divider, particularly in the case of a PLL circuit using a frequency divider having a frequency division ratio of 2N, the fluctuation signal V with a duty of 50% can be easily generated. it can. Therefore, the fifth embodiment shown in FIG.
The phase variable circuit 90 can be configured with a NOT circuit on the side of the fluctuation signal V like the phase comparator of FIG. 1 and there is an effect that the circuit can be simplified.

Further, when the frequency division ratio is odd, the input signal R is synchronized with either the fluctuation signal V or the second fluctuation signal V ₂ as shown in Japanese Patent Application Laid-Open No. 7-118107. It is sufficient to provide an output switching circuit capable of determining whether or not the output is switched and switching the output based on this. That is, it is possible to easily determine which output of the first or second phase comparison circuits 91 and 92 is selected by the selector circuit 98 based on the output S of the D-flip-flop 95 shown in FIG. The output may be switched based on the output S.

As described above, the outputs U and D of the phase comparator of the present invention have the same output format as that of the conventional memory type phase comparator, and also have the same output format as that of JP-A-6-209724. Therefore, by combining these two, the phase comparator of the present invention is selected at the time of synchronization acquisition to realize fast synchronization acquisition, and after completion of the synchronization acquisition, the non-memory type phase comparator of JP-A-6-209724 resistant to noise is used. The PLL circuit to be selected can be easily realized.

[Seventh Embodiment] FIG. 12 is a block diagram showing a configuration of a phase comparator according to a seventh embodiment of the present invention.
The phase comparator according to the seventh embodiment is different from the reference signal R in phase difference π /
Two variable signals V _A and V _B are input, the phase variable circuit 120 that shifts the phase of the variable signal V _A by + π and outputs the variable signal V _A2, and the phase of the variable signal V _B Is shifted by + π to output a fluctuation signal V _B2 , and a first phase comparison circuit 123 for obtaining the phase difference between the phase of the fluctuation signal V _{A and} the phase of the reference signal R.
And a second phase comparison circuit 124 for obtaining the phase difference of the phase of the fluctuation signal V _A2 with respect to the phase of the reference signal R, and the third phase comparison circuit 124 for obtaining the phase difference of the phase of the fluctuation signal V _B with respect to the phase of the reference signal R.
The phase comparison circuit 125 and the fourth phase comparison circuit 12 for obtaining the phase difference between the phase of the fluctuation signal V _{B2 and} the phase of the reference signal R.
6 and the reference signal R currently selected as the phase difference output
And fluctuation signal V _A , reference signal R and fluctuation signal V _A2 , reference signal R and fluctuation signal V _B or reference signal R and fluctuation signal V
_Based on the selection circuit 127 that determines that the phase difference of _B2 exceeds ± 2π and selects the final difference signal, and the selection result of the selection circuit 127, the difference signal with the smallest phase difference
It is composed of a switching circuit 128 which is selected from the fourth phase comparison circuits to obtain a final difference signal.

That is, the phase comparator of the seventh embodiment is
The difference signal between the phase of the reference signal R and the phase of the plurality of fluctuation signals having different phases is obtained by each of the plurality of phase comparison circuits, and the output of the phase comparison circuit currently selected as the difference signal exceeds the predetermined phase difference range. In this case, the difference signal of the other phase comparison circuit having the smallest phase difference within the predetermined phase difference range is output as the final difference signal.

The phase shift of the reference signal R or the fluctuation signal V is not limited to the above-mentioned phase difference π. That is, a plurality of signals having different phase differences are generated by the phase variable circuit, and the output from the phase comparison circuit is sequentially switched to further increase the feedback amount of frequency pull-in and reduce the noise that is out of one-to-one correspondence. be able to. Therefore, when the PLL circuit is configured, the synchronization time can be shortened by the above effect.

FIG. 13 shows the characteristics when signals with phase differences π / 2, π and 3π / 2 are produced in the phase comparator of the seventh embodiment. As is apparent from FIG. 13, it can be understood that the phase comparator according to the seventh embodiment further widens the difference between the feedback amount and the noise as compared with FIG. 5B.

In the phase comparator shown in FIG. 13,
It is also possible to input a plurality of reference signals and obtain a difference signal of the phases of the plurality of reference signals with respect to the phase of the fluctuation signal. That is, a plurality of reference signals having different phases are input, the difference signals of the phases of the plurality of reference signals and the fluctuation signal are respectively obtained, and when the phase difference of the difference signal currently being output exceeds a predetermined range, Of the difference signals, the difference signal having the smallest phase difference from the fluctuation signal is selected and output.

[Embodiment 8] FIG. 14 shows Embodiment 7.
2 shows an example in which a fluctuation signal having a plurality of phase differences is generated from the fluctuation signal V by using the phase comparator of FIG. This motor control device is connected to a reference signal generation circuit that generates a reference signal R (not shown), receives the reference signal R and the two-phase fluctuation signals V _A and V _B, and outputs two signals with respect to the phase of the reference signal R. The phase comparator 140 of the seventh embodiment that detects the phase difference between the phase fluctuation signals V _A and V _B and outputs the difference signal, and the charge pump 141 that converts the phase difference signal from a digital signal to an analog signal.
, A loop filter 142 that filters an analog signal, a motor driver 143 that drives a motor 144 according to the output voltage of the loop filter 142, and a rotation speed of the motor 144 is detected, and a two-phase fluctuation signal corresponding to the rotation speed is detected. And a speed detection circuit 145 that outputs V. The two-phase fluctuation signal V output from the speed detection circuit 145 is fed back to the phase comparator 140.

An encoder can be used as the speed detecting circuit 145. Many encoders output two-phase signals of A phase and B phase with a phase difference of π / 2. Therefore, the phase variable circuits 120 and 121 of the phase comparator 140
According to (FIG. 12), if the phase A and phase B outputs from the encoder are respectively phase-shifted by π, 0, π / 2, π
And a fluctuation signal V having a phase difference of 3π / 2 can be easily generated. By selecting an encoder of A phase and B phase with a duty of 50% as the speed detection circuit 145, the phase variable circuit 120 that constitutes the phase comparator 140,
Since 121 (FIG. 12) can be configured with two NOT circuits, the circuit configuration can be simplified.

As a result of performing a test using the motor control device of the eighth embodiment, it was possible to stably reduce the synchronization time as compared with the case of using the conventional phase comparator.

Incidentally, in each of the above-mentioned embodiments, the selection circuit constituting the phase comparator is constituted by the logic circuit.
In some cases, the phase difference may be determined using the analog output voltage that has passed through the filter. In addition, although the selector circuit was used for the switching circuit that constitutes the phase comparator,
A switching circuit such as a switching circuit may be used.

[0094]

As described above, according to the phase comparison method (claims 1 and 2) of the present invention, one of the input signals (reference signal and fluctuation signal) is phase-shifted to perform phase comparison. , The phase comparison result is switched when the one-to-one correspondence is deviated, so that the signals can be quickly associated with each other while keeping the wide phase comparison range, and the discontinuity of the phase difference output can be mitigated. . Further, when there is a frequency difference, the feedback component of the frequency pull-in can be increased and the noise component can be reduced. Therefore, when the PLL circuit is configured using this method, it is effective in the frequency pull-in process and stable. As a result, quick synchronization can be acquired. Further, since the phase shift need only be performed on one of the input signals, the application field can be expanded.

According to the phase comparison method (claim 3) of the present invention, a plurality of fluctuation signals having different phases are input,
The phase difference of the reference signal and the phase difference of the multiple fluctuation signals are calculated, and if the phase difference of the difference signal currently being output exceeds the specified range, the difference signal Since the difference signal with the smallest phase difference is selected and output, it is possible to increase the feedback component of the frequency pull-in when there is a frequency difference and reduce the noise component. Therefore, when a PLL circuit is constructed by using this phase comparison method, it is effective for frequency pull-in as well, and stable and fast synchronization acquisition is possible.

Further, according to the phase comparison method (claim 4) of the present invention, a plurality of reference signals having different phases are input,
The phase difference of the fluctuation signal and the phase difference of the multiple reference signals with different phase differences are calculated respectively, and if the phase difference of the difference signal currently being output exceeds the specified range, Since the difference signal with the smallest phase difference is selected and output, it is possible to increase the feedback component of the frequency pull-in when there is a frequency difference and reduce the noise component. Therefore, when a PLL circuit is constructed by using this phase comparison method, it is effective for frequency pull-in as well, and stable and fast synchronization acquisition is possible.

Further, according to the phase comparator of the present invention (claim 5), the reference signal R is phase-shifted and the phase comparison is performed with the fluctuation signal V respectively, and when the one-to-one correspondence is deviated, the phase comparison is performed. Since the result is switched, it is possible to quickly associate the signals while maintaining the wide phase comparison range, and to mitigate the discontinuity of the phase difference output. Further, when there is a frequency difference, the feedback component of the frequency pull-in can be increased and the noise component can be reduced. Therefore, when the PLL circuit is configured by using this phase comparator, it is also effective for the frequency pull-in, Stable and fast synchronization acquisition is possible. Further, since the output format is the same logic output format as the conventional memory type phase comparator, it can be easily replaced or combined with the conventional one. Further, since the variable signal V is not phase-shifted, the circuit configuration can be simplified and the application field can be expanded. Furthermore, since it suffices to limit the duty of 50% to only one of the reference signals R, the phase varying means can be realized by one NOT circuit, and a phase comparator with a simple structure and low cost can be obtained.

Further, according to the phase comparator of the present invention (claim 6), the fluctuation signal V is phase-shifted and the phase comparison is performed with the reference signal R respectively. When the one-to-one correspondence is deviated, the phase comparison is performed. Since the result is switched, it is possible to quickly associate the signals while maintaining the wide phase comparison range, and to mitigate the discontinuity of the phase difference output. Further, when there is a frequency difference, the feedback component of the frequency pull-in can be increased and the noise component can be reduced. Therefore, when the PLL circuit is configured by using this phase comparator, it is also effective for the frequency pull-in, Stable and fast synchronization acquisition is possible. Further, since the output format is the same logic output format as the conventional memory type phase comparator, it can be easily replaced or combined with the conventional one. Furthermore, since the reference signal R is not phase-shifted, the circuit configuration can be simplified and the application field can be expanded. Furthermore, since it suffices to limit the duty of 50% to only one of the fluctuation signals V, the phase varying means can be realized by one NOT circuit, and a phase comparator with a simple structure and low cost can be obtained.

According to the phase comparator of the present invention (claim 7), the output of the phase comparator itself is used to determine the one-to-one correspondence between the reference signal R and the fluctuation signal V in the logic circuit. Therefore, an inexpensive phase comparator can be constructed with a simple configuration.

Further, according to the phase comparator of the present invention (claim 8), the phase difference between a plurality of signals having different phase differences and other input signals is sequentially switched. It is possible to increase the frequency pull-in feedback component and reduce the noise component. Therefore, when a PLL circuit is constructed by using this phase comparison method, it is effective for frequency pull-in as well, and stable and fast synchronization acquisition is possible.

Further, according to the PLL circuit of the present invention (claim 9), since the frequency pull-in component is large and the noise component is small, it is possible to obtain the effect that the frequency synchronization process is stable and fast. Also, the division ratio of the frequency divider is 2
The output is the same regardless of which of the first and second phase comparison means inside the phase comparator is selected, and no special circuit (output switching means) is required. Furthermore, since a signal with a duty of 50% can be easily created, the phase varying means of the phase comparator can be simplified.

Further, according to the motor control circuit of the present invention (claim 10), the phase comparator has the same logical form as that of the conventional memory type phase comparator, so that there is no difference from the conventional PLL motor control circuit. It can be configured without problems. Further, since the frequency pull-in component and the noise component in the output are large, the frequency synchronization process is stable and fast, and the motor can be started up quickly. Further, since the synchronization time is shortened, it is possible to obtain an effect that the time during which noise caused by the fluctuation of the rotation speed of the motor until the synchronization is generated is shortened.

Further, according to the motor control circuit of the present invention (claim 11), the fluctuation signal V having a phase difference of every π / 2 can be easily produced from the speed detecting means (encoder) of the two-phase output. Therefore, the phase comparator configured to sequentially switch the output of the phase comparison means can be configured with a simple circuit. By using this phase comparator, the feedback component of the frequency pull-in can be increased and the noise component can be reduced, so that the synchronization can be fast and the motor can be started quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase comparator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a phase comparator according to a second embodiment of the present invention.

FIG. 3A and FIG. 3B are timing charts showing the output of the phase comparator according to the first embodiment of the present invention.

FIG. 4 is a graph showing an output voltage-phase difference characteristic of the phase comparator according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram for comparing the phase difference characteristics of the phase comparator according to the first embodiment of the present invention and the conventional phase comparator, and FIG. Phase difference characteristic, FIG. 5B is a phase difference characteristic of the phase comparator according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a phase comparator according to a third embodiment of the present invention.

FIG. 7 is a timing chart showing an output of the phase comparator according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a PLL circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a phase comparator according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a PLL circuit according to a sixth embodiment of the present invention.

FIG. 11 is a timing chart showing an output of the PLL circuit according to the sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a phase comparator according to a seventh embodiment of the present invention.

FIG. 13 is an explanatory diagram showing a phase difference characteristic of the phase comparator according to the seventh embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a PLL circuit according to an eighth embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a conventional phase comparator.

16 is a timing chart showing the output of the conventional phase comparator, FIG. 16 (a) shows the case where the phase of the fluctuation signal V is delayed with respect to the reference signal R, and FIG. The case where the phase of the fluctuation signal V leads the signal R is shown.

FIG. 17 is a block diagram showing a configuration for converting a phase difference output of a conventional phase comparator into a voltage.

FIG. 18 is a graph showing an output voltage-phase difference characteristic of a conventional phase comparator.

19 is a timing chart showing the output of the conventional phase comparator, FIG. 19 (a) shows the case where the phase of the fluctuation signal V is delayed with respect to the reference signal R, and FIG. The case where the phase of the fluctuation signal V leads the signal R is shown.

[Explanation of symbols]

10, 20, 120, 121 Phase variable circuit 11, 21, 123 First phase comparison circuit 12, 22, 124 Second phase comparison circuit 13, 23, 127 Discrimination circuit 14, 24, 128 Selection circuit 60, 63, 90, 93 NOT circuit 61,91 First phase comparison circuit 62,92 Second phase comparison circuit 64,65,66,94,95,96 D-flip-flop 67,97 NAND gate 68,98 Selector circuit 80,100,140, 150 Phase Comparator 81,101 Charge Pump 82,102,141 Loop Filter 83,143 Motor Driver 84,144 Motor 85,145 Speed Detection Circuit 103 Voltage Controlled Oscillator 104 Frequency Divider 120 Phase 125 Third Phase Comparison Circuit 126 Fourth Phase comparator circuit 151,152 Input section 153,154 Output section 55~163 NAND gate

Claims (11)

[Claims] 1. A phase comparison method for comparing the phase of a reference signal and the phase of a fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, wherein the phase of the reference signal and the phase of the fluctuation signal are By comparing, the difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is obtained as a first difference signal, and the phase of the second reference signal obtained by shifting the phase of the reference signal by + π is compared with the phase of the fluctuation signal. Then, a difference signal of the phase of the fluctuation signal with respect to the phase of the second reference signal is obtained as a second difference signal, and the difference signal between the reference signal and the second reference signal of the first difference signal and the second difference signal is obtained. A phase comparison method characterized in that a phase difference within ± 2π is output as a final difference signal. 2. A phase comparing method for comparing a phase of a reference signal and a phase of a fluctuation signal to obtain a difference signal of a phase of the fluctuation signal with respect to a phase of the reference signal, wherein the phase of the reference signal and the phase of the fluctuation signal are By comparison, a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is obtained as a first difference signal, and the phase of the reference signal and the phase of the fluctuation signal are + π.
By comparing the phases of the second fluctuation signals that have been shifted only by the difference between the phases of the second fluctuation signal with respect to the phase of the reference signal, as a second difference signal, among the first difference signal and the second difference signal. A phase comparison method characterized in that a signal having a phase difference of ± 2π with respect to the reference signal is output as a final difference signal. 3. A phase comparison method for comparing a phase of a reference signal and a phase of a fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, wherein a plurality of fluctuation signals having different phases are input, Difference signals between the phases of the plurality of fluctuation signals and the reference signal are respectively obtained, and when the phase difference of the difference signal currently being output exceeds a predetermined range, the difference signal with the reference signal among the plurality of difference signals is calculated. A phase comparison method characterized by selecting and outputting a difference signal having the smallest phase difference. 4. A phase comparison method for comparing a phase of a reference signal and a phase of a fluctuation signal to obtain a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, wherein a plurality of reference signals having different phases are input, Difference signals between the phases of the plurality of reference signals and the fluctuation signal are respectively obtained, and when the phase difference of the difference signal currently being output exceeds a predetermined range, the difference signal from the fluctuation signal among the plurality of difference signals is calculated. A phase comparison method characterized by selecting and outputting a difference signal having the smallest phase difference. 5. A phase comparator that compares the phase of a reference signal with the phase of a fluctuation signal and outputs a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, by shifting the phase of the reference signal by + π. A phase varying unit that outputs a second reference signal is compared with the phase of the reference signal and the phase of the fluctuation signal, and a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is output as a first difference signal. A first phase comparing means, comparing the phase of the second reference signal and the phase of the fluctuation signal, and outputting a difference signal of the phase of the fluctuation signal with respect to the phase of the second reference signal as a second difference signal. Of the two-phase comparison means and the first difference signal and the second difference signal, the phase difference between the reference signal and the second reference signal within ± 2π is selected and output as the final difference signal. And a selective output means, Phase comparator characterized by. 6. A phase comparator which compares the phase of a reference signal with the phase of a fluctuation signal and outputs a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, by shifting the phase of the fluctuation signal by + π. A phase varying unit that outputs a second fluctuation signal is compared with the phase of the reference signal and the phase of the fluctuation signal, and a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal is output as a first difference signal. A first phase comparing means, comparing the phase of the reference signal with the phase of the second fluctuation signal, and outputting a difference signal of the phase of the second fluctuation signal with respect to the phase of the reference signal as a second difference signal. Two-phase comparison means, and a selection output means for selecting and outputting, as the final difference signal, one of the first difference signal and the second difference signal having a phase difference of ± 2π from the reference signal, The phase characterized by having Comparator. 7. The phase comparator according to claim 5, wherein the first difference signal output from the first phase comparison means is a first phase advance signal indicating a phase advance of the fluctuation signal with respect to the reference signal. And a first phase delay signal indicating a phase delay of the fluctuation signal with respect to the reference signal, and the second difference signal output from the second phase comparison means is the second phase difference signal.
A second phase lead signal indicating a phase advance of the fluctuation signal with respect to the reference signal or a phase advance of the second fluctuation signal with respect to the reference signal; and a phase delay of the fluctuation signal with respect to the second reference signal or a second phase advance with respect to the reference signal. A second phase delay signal indicating a phase delay of the fluctuation signal, wherein the selection output means is a first phase advance signal or a second difference signal of the first difference signal selected as the final difference signal. In the state in which the second phase advance signal is ON, the fluctuation signal or the second fluctuation signal input to the first phase comparison means or the second phase comparison means selected as the final difference signal is active. When it becomes, it is judged that the phase difference of the first difference signal or the second difference signal exceeds + 2π, and the first difference signal of the first difference signal selected as the final difference signal.
The reference signal input to the first phase comparison means or the second phase comparison means selected as the final difference signal in a state where the phase delay signal or the second phase delay signal of the second difference signal is ON. Alternatively, it is determined that the phase difference between the first difference signal and the second difference signal exceeds -2π when the second reference signal becomes active. 8. A phase comparator which compares the phase of a reference signal and the phase of a fluctuation signal and outputs a difference signal of the phase of the fluctuation signal with respect to the phase of the reference signal, wherein the reference signal and the first fluctuation are used as input signals. A first phase varying unit that has a signal and a second variation signal having a phase different from that of the first variation signal, and shifts the phase of the first variation signal by + π to output a third variation signal; Comparing the phase of the reference signal and the phase of the first fluctuation signal with a second phase varying means for shifting the phase of the second fluctuation signal by + π to output a fourth fluctuation signal,
Comparing the phase of the reference signal with the phase of the second fluctuation signal, and comparing the phase of the reference signal with the phase of the second fluctuation signal to output a difference signal of the phase of the first fluctuation signal with respect to the phase of the reference signal as a first difference signal. Second phase comparing means for outputting a difference signal of the phase of the second fluctuation signal with respect to the phase of the reference signal as a second difference signal, and comparing the phase of the reference signal with the phase of the third fluctuation signal to obtain the reference A third difference signal that outputs a difference signal of the phase of the third fluctuation signal with respect to the phase of the signal, as a third difference signal.
A fourth phase comparing means compares the phase of the reference signal with the phase of the fourth fluctuation signal and outputs a difference signal of the phase of the fourth fluctuation signal with respect to the phase of the reference signal as a fourth difference signal. When the phase difference of the difference signal currently being output exceeds a predetermined range, the comparing means compares the reference signal with the first difference signal, the second difference signal, the third difference signal and the fourth difference signal. A phase comparator comprising: selection output means for selecting and outputting a difference signal having the smallest phase difference. 9. A PLL circuit for performing phase synchronization control, the phase comparator according to claim 5, 6 or 7, and a charge pump for converting an output signal of the phase comparator from an analog signal to a digital signal. A loop filter for filtering the output signal of the charge pump, a voltage controlled oscillator generating an output signal having an oscillation frequency corresponding to the output voltage of the loop filter, and an output signal of the voltage controlled oscillator divided by an even number. , A frequency divider that outputs the fluctuation signal to the phase comparator, the PLL circuit. 10. A motor control device for performing phase synchronization control of a motor, comprising: the phase comparator according to claim 5, 6 or 7; and a charge pump for converting an output signal of the phase comparator from a digital signal to an analog signal. A loop filter for filtering the output signal of the charge pump, a motor driver for driving the motor with a drive voltage corresponding to the output voltage of the loop filter, and a rotation speed of the motor, A motor control device comprising: a speed detection unit that outputs a signal to the phase comparator as the fluctuation signal. 11. A motor control device for performing phase synchronization control of a motor, the phase comparator according to claim 8, a charge pump for converting an output signal of the phase comparator from a digital signal to an analog signal, and the charge pump. Filter for filtering the output signal of the motor, a motor driver for driving the motor with a drive voltage corresponding to the output voltage of the loop filter, a rotation speed of the motor, and the first fluctuation according to the rotation speed. A motor control device comprising: a speed detection unit that outputs a signal and a second fluctuation signal to the phase comparator.