JP2776328B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
AS, especially for gate arrays and standard cells
In an IC, the present invention relates to a PLL circuit that simultaneously performs clock multiplication and inter-chip phase matching.

[0002]

2. Description of the Related Art A conventional PLL circuit for multiplication is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-162132. Referring to FIG. 7, the conventional PLL circuit includes a phase comparator 31 and
Loop filter 33, voltage controlled oscillator 34 and frequency divider 3
And 2.

The operation of this conventional PLL circuit will be described. The phase of an external signal and that of a feedback signal are compared by a phase comparator 31, and this phase difference is converted into a voltage difference by a loop filter 33. The oscillation frequency and phase of the control oscillator 34 change, and the frequency divider 3
2 is fed back to the phase comparator 31. This feedback operation is performed in such a direction that the frequency difference and the phase difference between the input signal and the feedback signal are reduced. Since the phase and frequency of the input signal and the feedback signal coincide with each other in the phase comparator 31, after all, if the frequency divider is, for example, (1/2), the signal entering the frequency divider is twice as large as the input signal. Having a frequency.

[0004]

However, since the phases match at the input of the phase comparator, the signal that enters the frequency divider eventually has a phase difference from the input signal of the phase comparator by the delay of the frequency divider. become.

One of the fields of application of this conventional PLL circuit is to reduce clock skew between chips when one system is composed of multiple chips. However, the above-mentioned PLL circuit is used to skew multiplication. Is performed at the same time, the delay of the frequency divider depends on the process of the chip and the junction temperature power supply voltage, and the difference in the process and the junction temperature of each chip always appears. This causes a problem that the frequency of the entire system is reduced.

[0006]

The PLL circuit of the present invention comprises:
A phase comparator that compares the phase difference between the two signals, an oscillator that receives an output of the phase comparator and outputs an output signal of a predetermined frequency, and a frequency divider that divides the output signal of the predetermined frequency. A PLL circuit that detects a phase difference between an input signal and an output signal of the frequency divider with the phase comparator, wherein a first delay unit provided between the input signal and the phase comparator; have a second delay means having a delay time equal to the first delay means between said phase comparator and the divider, the divider of the frequency of the input signal (1 /
2 ^N ) (N is a natural number)
The phase of which is opposite to the edge of the waveform of the input signal to be adjusted.
In this configuration, the frequency division operation is performed at the edge .

Further, the first and second delay means of the PLL circuit of the present invention may be AND circuits having the same configuration.

Further, the frequency divider of the PLL circuit of the present invention may be configured to output a frequency of (1 / ^2N ) (N is a natural number) of the frequency of the input signal.

[0009]

Next, an embodiment of the present invention will be described.

FIG. 1 is a configuration diagram of a PLL circuit according to an embodiment of the present invention.

Referring to FIG. 1, the PL of this embodiment
The L circuit has two inputs AND5 and 2 receiving the input signal VIN.
A phase comparator 4 receiving an output of an input AND5, a voltage controlled oscillator (hereinafter referred to as a VCO) 1 for outputting an output signal having a predetermined frequency based on an output of the phase comparison 4, and multiplying the output signal to the outside of the PLL circuit A clock driver 2 that outputs a signal, an output signal 10 of the clock driver 2 is received at a clock terminal C, and a flip-flop 3 that divides the frequency by (１ ／), a frequency-divided signal 13 and an output signal 10 are received, and two inputs are received. This is a configuration having a frequency divider 7 including a two-input AND5 having the same configuration as the AND5 and a two-input AND6 having the same configuration.

Next, the operation of the PLL circuit according to this embodiment will be described with reference to FIG.

This PLL circuit outputs a signal 11 delayed by a predetermined time by AND5 when an input signal VIN is input. This signal 11 is input to the phase comparator 4 and input from the VCO 1 via the clock driver 2 as an output signal 10 to the clock terminal of the flip-flop 3. Next, the flip-flop outputs an output signal 13 of (１ ／) frequency division, and outputs the output signal 10 and the output signal 13.
Is input to the phase comparator 4 via the AND 6 that performs the AND logic of.

The input signal VIN is delayed by a delay time of AND5.
The output signal is output to output signal 11. This rising edge
The edge signal is detected by the phase comparator 4 and output from the VCO 1.
Is forced. The output signal 10 is twice the input signal VIN.
Is a multiplied signal having the frequency of Furthermore, this
The multiplied signal 10 is frequency-divided by the frequency divider 7, and this frequency divider
Through an AND circuit 6 having the same delay time as the D circuit 5
You. The phase of signal 11 and the phase of signal 12 from the operation of the PLL
Are the same, and the delays of the AND circuit 5 and the AND circuit 6
Since the delay times are equal, the input signal VIN multiplied signal 10 is the same.
It will have one phase.

As a result, the signal 11 and the signal 12 have substantially the same phase difference.

The output of the flip-flop 3 in the frequency divider 7
Output the force signal 13 to the signal 12 via the AND circuit 6
And has the same delay time as AND circuit 6
By using the AND circuit 5, the input signal VIN
And the signal 10 can be eliminated.

Further, the frequency divider 3 is constituted by a frequency divider of 1/4 or 1/8, it can also be in correspondence with divided frequency divider to configure. The detailed description is the same as that of the 1/2 frequency divider, and therefore, the description thereof is omitted.

[0018]

As described above, the PLL circuit of the present invention
The path is such that the phase difference between the multiplied output signal and the input signal is zero.
The circuit configuration is as follows.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining an operation of the PLL circuit shown in FIG. 1;

FIG. 3 is a configuration diagram of a conventional PLL circuit.

[Explanation of symbols]

 1,34 VCO 2 clock driver 3 flip-flop 4,31 phase comparator 5,6 AND circuit 7,32 frequency divider 10,11,12,13 output signal FIN, VIN input signal FOUT, VOUT output signal

Claims (2)

(57) [Claims] 1. A phase comparator for comparing a phase difference between two signals, an oscillator receiving an output of the phase comparator and outputting an output signal of a predetermined frequency, and dividing the output signal of the predetermined frequency. A PLL circuit for detecting a phase difference between an input signal and an output signal of the frequency divider by the phase comparator, wherein a first circuit is provided between the input signal and the phase comparator. the delay means, have a second delay means having a delay time equal to the first delay means between said phase comparator and the divider, the divider of the input signal
Output frequency of (1/2 ^N ) (N is a natural number)
And the waveform of the input signal whose phase is to be matched
A PLL circuit which performs a frequency dividing operation at an edge having a phase opposite to that of an edge . 2. The PLL circuit according to claim 1, wherein said first and second delay means are AND circuits having the same configuration.