JP2814028B2 - Phase control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase
The present invention relates to a phase control circuit used for a Locked Loop (Looped Loop) circuit or the like.

2. Description of the Related Art FIGS. 4, 5 and 6 show a conventional example. FIG. 4 is a block diagram showing a PLL circuit, and FIG. 5 is an electric circuit showing details of a phase comparison circuit shown in FIG. FIG. 6 and FIG. 6 are time charts for explaining the operation of FIG. FIG.
, 31 is a phase comparison circuit, 32 is a reference oscillation circuit,
33 is a 1 / R divider circuit, 34 is a VCO (voltage controlled oscillator), 35 is a 1 / N divider circuit, 36 is a charge pump,
Reference numeral 37 denotes an LPF (low-pass filter). The phase comparison circuit 31 shown in FIG. 4 and FIG.
3 and an input pulse "FV" from the 1 / N frequency dividing circuit 35 (see FIG. 6). Then, the input pulse “FR” and the input pulse “F”
The phase difference with V is compared, and a phase difference pulse “U” (VCO frequency raising signal) and a phase difference pulse “D” (VCO frequency lowering signal) are output according to the phase difference. The basic function of the phase comparison circuit 31 is to output “U = 1, D = 0” when the phase of the input pulse “FR” is ahead of the phase of the input pulse “FV”, and to output the input pulse “FR”. Is output later than the phase of the input pulse "FV", "U = 0, D = 1" is output, and the phase of the input pulse "FR" matches the phase of the input pulse "FV". Sometimes "U = 0, D = 0" is output,
That is.

However, actually, as shown in FIG. 6, hazardous pulses "Hu" and "Hd" (hereinafter simply referred to as "hazard") are generated, so that the phase difference pulse "U" is generated. The hazard "Hu" overlaps the phase difference pulse "D" and the hazard "Hd". As described above, since the phase difference pulse and the period in which the hazard occurs overlap, for example, the CMO in the charge pump 36 shown in FIG.
Both channels of the S transistor are simultaneously turned on,
There is a problem that the charge pump 36, the VCO 34 and the like malfunction. SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit capable of removing an overlapping portion between a phase difference pulse and a hazard and performing an accurate operation.

SUMMARY OF THE INVENTION A phase control circuit according to the present invention comprises:
The output is set to 1
A first flip-flop circuit having a logic level of
The falling (or rising) of the other of the two input pulses
To set the output to the first logic level
A second flip-flop circuit and the first and second flip-flop circuits;
Both flip-flop circuits output the first logic level.
The first and second flip-flops
The roads are reset together to set the first and second flip-flops.
Control to set both outputs of the flip-flop circuit to the second logic level
Control circuit, and the first and second flip-flop circuits
Path corresponding to each of the above two input pulses.
Was there a two outputs, the first, second flip
The phase of the above two input pulses in the flop circuit
The side receiving the advanced input pulse is set first, and the phase
The side that received the delayed input pulse is subsequently set, followed by
The first and second flip-flop circuits are both reset.
The above input of the one whose phase is advanced
One of the output units corresponding to the pulse responds to the phase difference
And outputs the first pulse from the other output section.
Is a hazard having an overlap with the first pulse.
To output the second pulse in the shape of an arrow when the first pulse disappears
The outputs of the phase comparison circuit and the two output units are output first.
The logic level of the force is changed from the second logic level to the first logic level.
The first pulse is output from the output unit on the side that changed to
A discrimination circuit for discriminating that the discrimination has been performed;
The output on the side that outputs the first pulse based on the discrimination information
The output on the side that outputs the second pulse from the output of the power unit
By relatively delaying the output of the
Output of the section to an output without the above overlap section
And a delay control circuit .

FIG. 1, FIG. 2 and FIG. 3 show an embodiment. FIG. 1 is a block diagram showing a phase control circuit.
1 is an electric circuit diagram showing details of FIG. 1, and FIG. 3 is a time chart showing operations of FIGS. 1 and 2. The phase control circuit shown in FIGS. 1 and 2 is replaced with the phase comparison circuit 3 shown in FIG.
A PLL circuit can be configured by using the PLL circuit in place of 1. 1 and 2 are as follows. The phase comparison circuit 11 compares the phase of the input pulse “FR” from the 1 / R frequency dividing circuit (not shown) with the phase of the input pulse “FV” from the 1 / N frequency dividing circuit (not shown). Then, according to the phase difference, a phase difference pulse “U” (first pulse, a signal for raising the frequency of a VCO (not shown)) and a phase difference pulse “D” (first pulse, a frequency lowering signal of the VCO) Signal). This phase comparison circuit 1
The configuration of 1 is the same as the configuration of the phase comparison circuit 31 shown in FIG. 5 except that the output inverter is not included (the output inverter is included in delay circuits 13 and 14 described later). Therefore, as shown in FIG. 3, the basic function of the phase comparison circuit 11 is that "U = 0, D = 1 when the phase of the input pulse" FR "is ahead of the phase of the input pulse" FV ". Is output, and when the phase of the input pulse “FR” is behind the phase of the input pulse “FV”, “U = 1, D = 0” is output, and the phase of the input pulse “FR” and the input pulse “FV” are output. When the phase of FV "matches," U = 1, D = 1 "is output. However, actually, the hazard “Hu” (second pulse)
And “Hd” (second pulse), the phase difference pulse “U” and the hazard “Hu” overlap, and the phase difference pulse “D” and the hazard “Hd” overlap. The determination circuit 12 determines which of the phase difference pulse “U” and the phase difference pulse “D” was output first, and outputs a determination signal “S” (“logical value“ 1 ”or“ 0 ”). That is, the delay circuit 13 determines which phase of the input pulse “FR” or “FV” is advanced.
The signal "U1" (the phase difference pulse "U" and the hazard "Hd") from one of the output sections is delayed for a predetermined time, and a delayed pulse "U2" is output. Delay circuit 14
Is a signal “D” from the other output unit of the phase comparison circuit 11.
1 "(the phase difference pulse" D "and the hazard" Hu ") are delayed by a predetermined time, and the delay pulse" D2 "is output.The delay circuits 13 and 14 have substantially the same delay time. The re-delay circuit 15 delays the signal "U2" from the delay circuit 13 for a predetermined time and outputs a re-delay pulse "U3".
Numeral 6 is for delaying the signal "D2" from the delay circuit 14 by a predetermined time and outputting a re-delay pulse "D3". The delay time of the re-delay circuit 15 and the delay time of the delay circuit 16 are configured to be substantially the same. The selection circuit 17 receives the determination signal “S” (a signal indicating which of the phase difference pulse “U” and the phase difference pulse “D” was output first) from the determination circuit, and receives the delay pulse “U2” or One of the re-delay pulses “U3” is selected, and the inverted output pulse “U3” is selected.
In response to the determination signal "S" from the determination circuit, the selection circuit 18 selects either the delay pulse "D2" or the re-delay pulse "D3", and outputs the inverted output pulse. It outputs “D4.” Note that the delay time in the delay circuits 13 and 14 is determined by the selection circuit 17
18 is set to be equal to or longer than the time until completely standby (a time until which of the delay pulse and the re-delay pulse is output is completely determined). Next,
The operation of the phase control circuit shown in FIGS. 1 and 2 will be described with reference to the time chart of FIG. Phase comparison circuit 11
Receives input pulses “FR” and “FV”,
These phases are compared. When the phase of the input pulse “FR” is ahead of the phase of the input pulse “FV”, a phase difference pulse “U” is output from one output unit, and the phase of the input pulse “FR” is the same as that of the input pulse “FV”. When the phase is behind the phase, the other output section outputs a phase difference pulse “D”. When the phase difference pulse “U” disappears, a hazard “Hu” overlapping with the phase difference pulse “U” is output from the other output unit. When the phase difference pulse “D” disappears, the phase difference pulse “D” is output. Overlapping hazards "Hd" are output from one output. Upon receiving the phase difference pulse “U” and the phase difference pulse “D”, the discrimination circuit 12 outputs a discrimination signal “S”.
(“Logic value“ 1 ”or“ 0 ”) The signal“ U1 ”from one output of the phase comparator 11 is sequentially delayed by the delay circuit 13 and the re-delay circuit 15, Outputs a delay pulse "U2" from the re-delay circuit 15 and a re-delay pulse "U3" from the re-delay circuit 15. Similarly, the signal "D1" from the other output of the phase comparison circuit 11 is delayed. The delay pulse "D2" is sequentially delayed by the circuit 14 and the re-delay circuit 16,
The re-delay circuit 16 outputs a re-delay pulse “D3”. The discrimination signal "S" from the discrimination circuit 12 is input to the selection circuits 17 and 18, and the output portions of the selection circuits 17 and 18 (each constituted by a pair of tri-state inverters) enter a standby state. When the phase difference pulse is “U = 0, D = 1”, the selection circuit 17 selects the delay pulse “U2”, and the selection circuit 18 selects the re-delay pulse “D3”. vice versa,
When the phase difference pulse is “U = 1, D = 0”, the selection circuit 17 selects the re-delay pulse “U3”, and the selection circuit 18 selects the delay pulse “D2”. That is, the phase difference pulses "U" and "D" are simply delayed, whereas the hazards "Hu" and "Hd" are re-delayed. As a result, the inverted output pulse “U4” from the selection circuit 17 and the inverted output pulse “D4” from the selection circuit 18 do not overlap each other. Therefore, for example, when the outputs of the selection circuits 17 and 18 are connected to a charge pump, it is possible to prevent both channels of the CMOS transistors in the charge pump from being turned on at the same time, and to prevent malfunctions of the charge pump and the VCO.

According to the present invention, since the second pulse is relatively delayed from the first pulse to remove the overlapped portion between the two pulses, the circuit can operate accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing details of FIG. 1;

FIG. 3 is a time chart for explaining the operation of FIGS. 1 and 2;

FIG. 4 shows a conventional example, and is a block diagram showing a PLL circuit.

FIG. 5 is an electric circuit diagram showing details of a phase comparison circuit of FIG. 4;

FIG. 6 is a time chart for explaining the operation of FIG. 5;

[Explanation of symbols]

 11 ... Phase comparison circuit 12 ... Discrimination circuit 13, 14 ... Delay circuit 15,16 ... Re-delay circuit 17, 18 ... Selection circuit

Claims (3)

(57) [Claims] [Claim 1] one of the two input pulses having a phase difference
Output when set by falling (or rising) of
Flip-flop circuit having a first logic level
And the other falling (or falling) of the two input pulses
Rising) and set the output to the first logic level.
A second flip-flop circuit, and the first and second
Both flip-flop circuits set the first logic level.
Receiving the output, the first and second flip-flops
Resetting the flip-flop circuit together, the first and second flip
Set both outputs of the flop circuit to the second logic level
And the first and second flip-flops
Loop circuit for each of the above two input pulses.
Corresponding to the first and second free paths.
Of the above two input pulses in the flip-flop circuit
The side that receives the advanced input pulse is set first,
The side that receives the delayed input pulse is set subsequently,
Subsequently, the first and second flip-flop circuits are both
By being reset, a first pulse corresponding to the phase difference is output from one of the output units corresponding to the input pulse whose phase is advanced, and the first pulse is output from the other output unit. A phase comparison circuit for outputting a second hazard-shaped pulse having an overlap portion when the first pulse disappears, receiving the outputs of the two output portions, and first outputting the logical level of the output
A discriminating circuit for discriminating that the first pulse has been output from the output section on the side where the signal has changed from the second logic level to the first logic level, and the first circuit based on discrimination information from the discriminating circuit. By relatively delaying the output of the output unit on the side that outputs the second pulse from the output of the output unit on the side that outputs the pulse, the output of each output unit does not have the overlap unit. A delay control circuit for converting the output into an output. 2. The delay control circuit comprises: two delay circuits for respectively delaying signals from the two output units; two re-delay circuits for respectively delaying signals from the two delay circuits; In response to the discrimination information from the discrimination circuit, of the signal from the delay circuit or the signal from the re-delay circuit, the one corresponding to the one output unit outputs the signal from the delay circuit to the other output. 2. The phase control circuit according to claim 1, further comprising a selection circuit for selecting a signal from the re-delay circuit. 3. The determination circuit according to claim 2, The output of the first flip-flop circuit and the second flip-flop circuit
The inverted outputs of the flip-flop circuits are both at the first logic level.
The second flip-flop.
Output of the flip-flop circuit and inversion of the first flip-flop circuit
When both outputs go to the first logic level,
A third flip-flop circuit to be activated.
The state of the flip-flop circuit of the first
Output level first in the flip-flop circuit
Has changed from the second logic level to the first logic level.
And the reset state indicates the second
Output level first in the flip-flop circuit
Has changed from the second logic level to the first logic level.
2. The method according to claim 1, wherein the identification information represents
On-board phase control circuit.