JP3228414B2 - Phase comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention delays input waveform edge signals on the side to be compared with each other which are input to a reset circuit for generating two independent reset signals, and generates an error on the leading and lagging sides of the phase. The present invention relates to a phase comparator in which a detection zone is overlapped so that a dead zone hardly occurs in error detection characteristics.

[0002]

2. Description of the Related Art Conventionally, as a means for preventing a dead zone of an error detection characteristic in a phase comparator, a method of delaying the timing of a reset signal to lengthen a pulse width of an error signal output has been used. For example, Japanese Patent Application Laid-Open No. 9-1627
No. 28 discloses a technique of connecting a plurality of logic gates to form a reset circuit in order to optimize the delay of the reset circuit. The configuration is shown in FIG.

In FIG. 15, the connection of the NAND circuit is replaced with an RS flip-flop for easy understanding. The correspondence of the circuit in this case is shown in FIG. 17, and a truth table of the RS flip-flop is shown in the following [Table 1].

[0004]

[Table 1]

FIG. 16 is a diagram which is completely equivalent to FIG. 15. Hereinafter, the operation of the conventional phase comparator shown in FIG. 16 will be described with reference to the timing chart of FIG. In the following description, the flip-flop is referred to as F
It is abbreviated as F. When the comparison signal IN, which is a phase delay signal, falls as shown in FIG. 18B, the reset signal is input to the RSFF (hereinafter, RSFF is simply referred to as FFF).
F) The error output DWB of the RS 22a is shown in FIG.
It becomes a low level as shown in FIG. 8 (H) (indicated by the letter b in FIG. 18). At the same time, the output signal net22 of the FFRS 21 to which the comparison signal IN is input as the set signal is
FIG. 18 (I) shows the state shown in FIG.
It goes to high level over (I) as shown by the symbol c.

The output signal ne of the FFRS 11 of the REF terminal side error detection circuit to which the reference signal REF of the phase lead signal is inputted.
As shown in FIG. 18D, t12 is already at the high level. Also, the output signal net2 of the FFRS23
3 {FIG. 18 (J)}, output signal net13 of FFRS13
18 (E), the comparison signal IN and FIG.
When the reference signal REF shown in FIG. Therefore, when the output signal net22 of the FFRS 21 becomes high level, the input of the reset circuit 4 becomes all high level.

At this time, the output signal net23 of the FFRS21 and the output signal net13 of the FFRS13 are input to the reset circuit 4 because the combinational circuit 4a is inserted in the configuration of FIG.
11, the output signal net13 and the output signal net23 operate in response to the rise of the reference signal REF and the comparison signal IN as described above. Because they are far apart, there is no effect if there is some delay. As a result, the output signal net14 of the reset circuit 4 immediately changes from the high level to the low level, as indicated by the symbol d in FIG.

When the output signal net14 of the reset circuit 4 becomes low level, the input REF terminal side and the input IN
The reset is simultaneously applied to both error detection circuits RS22b and RS12b on the terminal side, and the error detection circuit RS22b shown in FIG.
The output signal net25 shown in (L) falls as shown by the symbol e. The output signal net15 of the error detection circuit RS12b shown in FIG. 18 (G) also falls as shown by the symbol g in FIG.

[0009] In response to this, FIG.
(H) output signal net21 (DWB), FFRS12
The output signal net11 (UPB) shown in FIG. 18C rises at the same time (indicated by reference numerals f and h in FIG. 18). Finally, in the input phase relationship as shown in FIG.
The output pulse of the output signal net21 (DWB) of the output signal 22a has a minimum fixed width.

On the other hand, the output signal net11 of the FFRS 12a
The output pulse width of (UPB) changes according to the phase advance amount of the reference signal REF with respect to the comparison signal IN, and this decreases to the minimum fixed width because the phase of the reference signal REF is delayed from the comparison signal IN by the delay of the reset circuit 14. That is to say, it is delayed by an amount. Conversely, the reference signal REF is the comparison signal I
Regarding the phase relationship delayed from N, the error detection circuit RS12b on the reference signal REF side and the error detection circuit RS on the input IN side
Since 22b is completely symmetric, the above description may be read symmetrically.

FIG. 19 to FIG. 23 show a summary of this for each input phase. FIG. 19A to FIG.
(A) shows the reference signal REF in the case of the phase (1) to the phase (4), respectively, and FIGS. 19 (b) to 23 (b) show the comparison signal in the case of the phase (1) to the phase (4), respectively. IN is shown. FIGS. 19C to 23C show the error signal UPB of the FFRS 12a in the case of the phase (1) to the phase (4), respectively, and FIGS. 19C to 23C show the phase ( FIGS. 19 (d) to 23 (d) show error signals UPB of the FFRS 22a in the cases of phase (1) to phase (4). ing.

Phase (2) in FIG. 20 is the same as phase (3) in FIG. 21 when the reference signal REF is ahead of the comparison signal IN.
In the case of the same phase, the phase (4) in FIG. 22 and the phase (5) in FIG. 23 are the case where the reference signal REF is later than the comparison signal IN. When there is a phase difference between the comparison signal and the reference signal {phases (1), (2), (4), and (5) in FIGS.
｝), The error signal output pulse width on the side where the delayed waveform is input is the minimum value, and the error signal output pulse width on the side where the advanced waveform is input is It is obtained by adding the phase difference of the waveform. When the input waveforms have the same phase, both error signal output pulse widths are minimized.

FIGS. 24 to 26 are graphs showing the relationship between the phase error and the error signal output pulse width. FIG.
26 are the same variation conditions, and the left side is the error signal UP which is the output of the FFRS 12a.
B, the pulse width of each error signal DWB output from the FFRS 22a is made to correspond to the upper and lower sides of the vertical axis for convenience, and the right side of each of FIGS. 24 to 26 shows the difference of the pulse width on the vertical axis. .

FFRS1 in the left graphs of FIGS.
The characteristic of the error signal UPB of FIG. 2a is proportional to the amount of charge discharged on the power supply side of the charge pump 200 in the phase comparator 100 in FIG. 12, and similarly, the characteristic of the output DWB of the FFRS 22a in the left graph of FIGS. It can be said that it is proportional to the side suction charge amount. The graphs on the right side of FIGS. 24 to 26 are proportional to the charge / discharge charge amount of the capacitor 201 connected to the output side of the charge pump 200 in FIG. 12, and are also proportional to the terminal voltage of the capacitor 201.

The characteristic shown in FIG. 24 is an ideal characteristic when there is no manufacturing variation. The error output range with respect to the phase error is smaller than the error signal UPB side of the FFRS 12a and the FFRS 22.
It is in a state of being in contact with the error signal DWB side of "a" without overlapping. FIG. 25 shows the characteristics in the case where there is an element variation in the direction in which the overlap increases, and FIG. 26 shows the case where the detection ranges do not overlap or come into contact with each other.

[0016]

However, this prior art has the following problems. That is, the dead zone shown in the variation (2) of FIG. 26 due to the unbalance of the device performance due to the manufacturing variation cannot be avoided. The reason for this is that the error output range in the ideal state does not overlap between the error signal UPB side of the FFRS 21a and the error signal DWB side of the FFRS 22a, and is in a state of being in direct contact. This is because the reason that the dead band is generated in the error detection characteristic is that only the minute pulse is lost due to the rounding of the pulse generated by the load capacitance of the error signal output.

In the above-mentioned Japanese Patent Application Laid-Open No. 09-162728, "The reset circuit in the phase comparator according to the present invention is not limited to the configuration shown in the figure, and the circuits have the same logic and the number of inputs is three or less. Any structure may be used as long as it is constituted by a plurality of stages of logic gates. "It is clear that imbalance in the error detection range is not assumed. .

Japanese Patent Application Laid-Open No. 04-35522 discloses that even when there is no phase difference in a signal with respect to a reference signal, a pulse signal obtained by comparing the phase differences has a predetermined pulse width so that the phase difference is reduced. A phase comparator including a pulse width changing means for providing a pulse width in which a pulse width corresponding to a phase difference and a predetermined pulse width are added, if any, is disclosed. Japanese Patent Application Laid-Open No. 05-276027 discloses a phase comparator that generates a phase delay signal and a phase advance signal to such an extent that a circuit at the next stage can react even in a steady state to obtain a phase comparison characteristic without a dead zone. It has been disclosed. However, even in these publications, there is no suggestion about a technique for eliminating the above-mentioned dead zone caused by an imbalance in element performance due to manufacturing variations or the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. Even if the error detection range is relatively changed due to manufacturing variations or the like, it is possible to make it difficult to generate a dead zone in the error detection characteristics. Even if the variation is at a maximum,
An object of the present invention is to provide a phase comparator that can prevent interruption of an error detection region.

[0020]

In order to achieve the above object, a phase comparator according to the present invention comprises: a first flip-flop circuit for outputting a first error signal in response to a level change of a reference signal; A second flip-flop circuit for outputting a second error signal in response to a change, and a first flip-flop circuit for holding a level before the level change of the reference signal when the level of the reference signal changes, and detecting an error due to a delay in the reference signal. An error detection circuit, a second error detection circuit that holds the level of the comparison signal before the level change when the level of the comparison signal changes, and detects an error due to a delay of the comparison signal; When the phase of the comparison signal is delayed, the edge of the comparison signal when the level changes is propagated with a delay by the delay amount of the first delay circuit, and the error detection range of the first error signal is compared with the comparison signal. Base The resetting the first error detection circuit with the direction in which the signal is delayed to expand by the time delay of the first delay circuit hardly occurs a dead zone in the error detection characteristics 1
And when the phase of the reference signal lags behind the phase of the comparison signal, the edge of the reference signal when the level changes is propagated with a delay amount of the second delay circuit, and the second error The error detection range of the signal is expanded by a delay amount of the second delay circuit in a direction in which the comparison signal lags behind the reference signal, so that a dead zone is hardly generated in the error detection characteristics, and the second error detection circuit is reset. A second reset circuit independent of the first reset circuit.

According to the present invention, the reference signal is input to the first flip-flop circuit, and the first flip-flop circuit changes the level of the first flip-flop circuit.
And the first error detection circuit holds the level before the level change of the reference signal when the level of the reference signal changes, and detects an error due to the delay of the reference signal. Also,
Are compared signal input to the second flip-flop circuit, and outputs a second error signal a change in the level of its <br/>, level change of the comparison signal when the level change of the comparison signal by a second error detection circuit The previous level is maintained, and an error due to the delay of the comparison signal is detected. When the phase of the comparison signal lags behind the phase of the reference signal, the edge of the comparison signal when the level changes is delayed by the delay amount of the first delay circuit and propagated to the first reset circuit. The first reset circuit expands the error detection range of the first error signal by the delay amount of the first delay circuit in a direction in which the reference signal lags behind the comparison signal, thereby deteriorating the error detection characteristics.
In addition to making the sensation zone less likely to occur , the first error detection circuit is reset. Similarly, when the phase of the reference signal lags behind the phase of the comparison signal, the edge at the time when the level of the reference signal changes is delayed by the delay amount of the second delay circuit and the second edge independent of the first reset circuit. To the reset circuit. The second reset circuit expands the error detection range of the second error signal by the delay amount of the second delay circuit in a direction in which the comparison signal lags behind the reference signal , thereby generating a dead zone in the error detection characteristic.
And resetting the second error detection circuit.

Therefore, according to the present invention, even if the error detection range is relatively changed due to manufacturing variations, etc., it is possible to make it difficult to generate a dead zone in the error detection characteristics. Disruption can be prevented.

[0023]

Next, an embodiment of a phase comparator according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment according to the present invention. Referring to FIG. 1, the phase comparator according to the present invention includes a first RS
An FF, a second FF 13 serving as a first error detection circuit,
A third FF including NAND circuits 21 and 22;
A fourth FF 23 serving as a second error detection circuit, and a NAND
A first reset circuit composed of a circuit 14, a second reset circuit composed of a NAND circuit 24, and delay circuits 15 and 2
5 is provided.

The NAND circuit 11 has a reference signal REF which is a phase advance signal with respect to the comparison signal IN and the NAND circuit 1
2 is input to the NAND circuit 21. Similarly, the comparison signal IN and the NAND circuit 22 are input to the NAND circuit 21.
And an error signal DWB output from the controller. The output signal of the NAND circuit 11, the output signals of the second and fourth FFs 13 and 24, and the output signal of the NAND circuit 21 through the delay circuit 15 are input to the NAND circuit 14 as the first reset circuit. The output signal of the NAND circuit 21, the output signals of the second and fourth FFs 23, and the output signal of the NAND circuit 11 through the delay circuit 25 are input to the NAND circuit 24 as the second reset circuit.

The output signal of the NAND circuit 11, the output signal of the second FF 13, and the output of the NND circuit 14 are input to the NAND circuit 12, and similarly, the output signal of the NAND 21 and the fourth signal are input to the NAND circuit 22. The output signal of the FF 23 and the output signal of the NAND circuit 24 are input.
When the terminal function of the second FF 13 is made to correspond to FIG.
The output terminal of the NAND circuit 11 is connected to the terminal SB, and the output terminal of the NAND circuit 14 is connected to the terminal RB.

Similarly, the terminal SB of the fourth FF 23 has N
The output terminal of the AND 21 is connected, and the output terminal of the NAND circuit 24 as a second reset circuit is connected to the terminal RB. The outputs of the first and second reset circuits are independent and the first and second reset circuits are reset by the NAND circuit 14.
Error detection circuit, and a NAND which is a second reset circuit
The error detection range is expanded independently of the second error detection circuit reset by the circuit 24.

Next, the operation of the first embodiment configured as described above will be described. First, FIG. 1 shows the configuration of the first embodiment. For this purpose, the NAND circuit is replaced with RSFF. FIG. 17 shows the correspondence of the circuit in this case, and Table 1 shows a truth table of the RSFF. FIG. 2 is a block diagram showing a circuit configuration completely replaced with FIG. 1 in this manner.

The operation of the first embodiment will be described below with reference to the timing chart of FIG. 3 based on FIG.
The comparison signal IN, which is the phase delay signal shown in FIG.
When the comparison signal IN is input to the terminal RB of the FRS 22a and the terminal SB of the FFRS 21 and the comparison signal IN falls, the output signal of the FFRS 22a to which the reset signal is input as shown by reference numeral a2 in FIG. The error signal DWB shown in (H) is at a low level.

At the same time, the F
The output signal net22 of the FRS 21 shown in FIG. 3 (I) is at a high level as shown by the symbol a3 in FIG. FIG. 3 (A)
The reference signal REF, which is a phase lead signal as shown in FIG.
The signal is input to a terminal SB of the FRS 11 and a terminal RB of the FFRS 12a. When the reference signal REF is input to the terminal RB of the FFRS 12a, the output signal of the FFRS 12a, that is, the error signal UPB is output as shown in FIG. Also, the output signal net12 of the FFRS11, which is the REF terminal side error detection circuit, to which the reference signal REF has been input, has already become the same as shown in FIG. To a high level.

The FFRS 13 receives the rising edge of the reference signal REF, and the output signal net 13 of FIG.
As shown in the figure, it is already at the high level. Similarly,
The FFRS 23 also receives the rise of the comparison signal IN, and the output signal net23 is already at the high level as shown in FIG. The output signal net22 of the FFRS21
And the output signal net13 of the FFRS 13 becomes high level, so that the levels of the signals applied to the input terminals of the NAND circuits 14 and 24 all become high level.

At this time, the output signal net22 of the FFRS 21
Are directly input to the NAND circuit 24 and the NAND circuit 1
4 is input through a delay circuit 15. As described above, the high-level output signal net23 of the FFRS 23 is input to both the NAND circuits 14 and 24, and the FFRS1
The third output signal net13 is also input. In addition, NAND
The output signal net12 of the FFRS11 is directly input to the circuit 14, and the output signal net12 of the FFRS11 is input to the NAND circuit 24 through the delay circuit 25.

As described above, the output signal net2 of the FFRS 21
2 is input to the NAND circuits 14 and 24 as described above, so that the output signal net2 of the NAND circuit 24 is immediately output.
4 changes from a high level to a low level as shown in FIG. 3 (K) (in FIG. 3, denoted by reference numeral a5). NAND
When the output signal net24 of the circuit 24 goes low, the output signal net25 of the AND circuit RS22b becomes
As shown in (L), the level of the FFRS 22 becomes low.
The voltage is applied to the terminal SB of a and the terminal RB of FFRS21.

On the other hand, the output signal net22 of the FFRS 21 is N
Since the delay circuit 15 exists in the path input to the AND circuit 14, the timing at which the output signal net14 of the NAND circuit 14 changes from high level to low level as shown in FIG. 24 output signals
This is delayed from the net 24 by the delay amount of the delay circuit 15 (indicated by reference numeral a4 in FIG. 3). NAND circuit 14
Low level output signal net14 is at terminal R of FFRS13.
B and applied to the AND circuit RS12b. AND circuit RS1
2b, the low-level output signal ne of the NAND circuit 14
By applying t14, the output signal net15 of the AMD circuit RS12b becomes low level as shown in FIG. Subsequent operations are the same as those of the conventional example, and a detailed description thereof will be omitted.

Finally, in the input phase relationship as shown in FIG. 3, the pulse of the error signal DWB has the minimum fixed width. On the other hand, the pulse width of the error signal UPB is
Changes according to the amount of phase advance of the reference signal REF with respect to
This decreases to the minimum fixed width when the phase of the reference signal REF lags behind the comparison signal IN by the delay amount of the delay circuit 15.

Conversely, regarding the phase relationship in which the reference signal REF lags behind the comparison signal IN, the above description may be read symmetrically because the error detection circuits on the reference signal REF side and the comparison signal IN side are completely symmetric. . This is summarized for each input phase and is shown in FIGS. FIG.
FIGS. 8A to 8A show phases (1) to (4), respectively.
8 shows the reference signal REF in the case of FIG.
(B) shows the comparison signal IN in each of the phases (1) to (4).

FIGS. 4 (c) to 8 (c) show the error signal UPB of the FFRS 12a in the case of the phases (1) to (4), respectively. FIGS. 4 (c) to 8 (c) FIGS. 4D to 8D show the error signals UPB of the FFRS 12a in the case of the phases (1) to (4), respectively.
The error signal UWB of the FFRS 22a in the case of the phase (4) is shown. Phase (1) in FIG. 4 and phase (2) in FIG. 5 show the case where the reference signal REF is ahead of the comparison signal IN. Phase (3) in FIG. 6 shows a case where the reference signal REF and the comparison signal IN are in phase. Phase (4) in FIG. 7 and phase (5) in FIG. It is when it is late.

When the phase difference between the reference signal REF and the comparison signal IN is large {corresponding to the phases (1), (2), (4) and (5)}, the reference signal REF or the comparison signal having a delayed phase Error signal DWB or UP on the side to which IN is input
The pulse width of B becomes the minimum value. On the contrary, the pulse width of the error signal DWB or UPB on the side to which the reference signal REF or the comparison signal IN of the waveform advanced in phase is input is different from the above-mentioned minimum value by the input waveform. The phase difference and the delay of the delay circuit are added.

If the input waveforms of the reference signal REF and the comparison signal IN are in phase, neither error signal output pulse width is at a minimum. The broken line in FIGS.
And the pulse width in the absence of the delay circuit 25, which is equal to the pulse width indicated by the broken line in the timing charts shown in FIGS. It can be seen that the delays of the delay circuits 15 and 25 increase the pulse width of the error signal output.

FIGS. 9 to 11 show the phase error and the error signal DWB.
Alternatively, the graph shows the relationship with the pulse width of UPB. 9 to 11, adjacent graphs are under the same variation condition, and the left side is the error signal UPB,
The pulse width of each DWB corresponds to the upper and lower sides of the vertical axis for convenience, and the right side shows the pulse width difference on the vertical axis.

FIG. 12 briefly shows a peripheral circuit of the phase comparator. Generally, the phase comparator 100 according to the present invention is used.
A charge pump circuit 200 is connected to the subsequent stage, and controls output charges by error signals UPB and DWB output from the phase comparator 100. Charge pump circuit 200
Is connected to a capacitor 201 for integrating the output charge and outputting it as a voltage.

Referring back to FIGS. 9 to 11, the characteristics of the error signal UPB in the graphs on the left side in FIGS. 9 to 11 are related to the amount of charge discharged on the power supply side of the charge pump 200 in FIG. Similarly, it can be said that the characteristic of the error signal DWB is proportional to the amount of charge absorbed on the GND (ground) side. 9 to 11, the graph on the right side shows the charge pump 200 shown in FIG.
Is proportional to the charge / discharge charge amount of the capacitor 201, and is also proportional to the terminal voltage of the capacitor 201.

9 to 11, the characteristics shown in the graph on the left side of FIG. 9 are ideal characteristics in the case where there is no manufacturing variation of the element, and the error output range with respect to the phase error is different from the error signal UPB side. It overlaps with the error signal DWB. Further, the characteristics shown in FIG. 10 show a case where there is a device variation in a direction in which the error output range with respect to the phase error becomes larger on the error signal UPB side and the error signal DWB side on the error signal UPB side. Further, the characteristic shown in FIG. 11 shows that, contrary to FIG. 10, the element variation in the direction in which the error output range with respect to the phase error is minimized between the error signal UPB side and the error signal DWB side. Indicates that the number is small.

As described above, in the first embodiment, the error signals UPB and DWB in the circuit shown in FIG.
Is the corresponding one of the input signals (ie, the error signal UP
B corresponds to the reference signal REF, and the error signal DWB corresponds to the comparison signal IN), and changes the output level of the error signal from a high level to a low level in response to the fall of the error signal DWB. The NAND circuits 14 and 24, which are reset circuits, generate a reset signal in accordance with the falling edge of one of the input waveforms of the reference signal REF and the comparison signal IN whose phase is delayed.

The error signals UPB and DWB output high level and are held by this reset signal. In other words, a fixed width negative logic pulse is output as the error signal DWB or UPB corresponding to the side where the phase of the comparison signal IN or the reference signal REF is delayed. Further, the error signal D corresponding to the side where the phase of the comparison signal IN or the reference signal REF is advanced.
As WB or UPB, a negative logic pulse is output during a period obtained by adding the fixed width to the falling phase difference of the comparison signal IN or the reference signal REF.

Here, the comparison signal I is larger than the reference signal REF.
Taking the case where the fall of N is delayed as an example, the propagation of the falling edge of the comparison signal IN to the NAND circuit 14 as the reset circuit is delayed from the NAND circuit 24 by the delay amount of the delay circuit 15. That is, the error signal UP
The error detection range of B is smaller than the comparison signal IN by the reference signal REF.
Is expanded by the delay amount of the delay circuit 15 in the direction of delay.

Similarly, the error detection range of the error signal DWB is expanded by the delay amount of the delay circuit 25 in a direction in which the comparison signal IN is delayed from the reference signal REF. Thus, even if the error detection range of each of the error signals UPB and DWB fluctuates due to manufacturing variations of the elements, the delay circuits 15 and 2
If the delay amount is within the delay amount of 5, no dead zone occurs in the error detection characteristics.

Next, a second embodiment of the present invention will be described. Although the basic configuration of the second embodiment is the same as that of the first embodiment, the configurations of the reset circuit and the delay circuit are further improved. FIG. 13 is a block diagram showing the configuration of the second embodiment according to the present invention. In FIG. 13, the reset circuit includes a three-input NAND circuit 14 and a two-input AND circuit 16.

This is because the output signal net13 of the FFRS 13 shown in FIG. 3E and the output signal net23 of the FFRS 23 shown in FIG. This is because the one-stage AND circuits 16 and 26 can be inserted into the output paths of the FFRS 13 and FFRS 23, respectively, by utilizing the fact that there is no problem even if there is a slight delay due to the difference from the timing. As a result, compared with the case where a 4-input NAND circuit has been required for the reset circuit,
There is an effect that the operation speed at a low power supply voltage can be given a margin.

FIG. 14 shows a third embodiment according to the present invention. FIG. 14 is also shown as a block diagram. In FIG. 14, the output signal net13 of the FFRS13 and the output signal net23 of the FFRS23 also pass through the delay circuit. , Two-input NAND, and three inverters. That is, on the side corresponding to the reference signal REF, the two-input NAND circuit 15a
And an inverter 15b, a delay circuit is configured, and a NAND circuit 14 as a reset circuit is connected to the delay circuit.

The NAND circuit 15a includes the NAND circuit 2
1 and the output signal of the FFRS 23 are input and N
The output of the AND circuit 15a is input to the NAND circuit 14 through the inverter 15b. NAND
The circuit 14 further includes an output signal of the NAND circuit 11 and F
The output signal of the FRS 13 is input and these three inputs N
An AND logic is taken and the output signal is output to the NAND circuit 12 and the FF.
It is supplied to RS13.

The same configuration is applied to the side corresponding to the comparison signal IN, and the two-input NAND circuit 25
a and an inverter 25b constitute a delay circuit, and the output of the delay circuit is input to the NAND circuit 24 of the reset circuit. The NAND circuit 25a has an NA
The output signal of the ND circuit 11 and the output signal of the FFRS 13 are input, and the output of the NAND circuit 25b is
To the NAND circuit 24. NAND circuit 2
4 is output to the NAND circuit 22 and the FFRS 23. By doing so, FIG.
In addition to the effect of the second embodiment shown in FIG. 3, a new effect that the gate scale can be reduced is obtained.

[0052]

As described above, according to the present invention, the input signal edge signal of the comparison signal and the reference signal of the reference signal, which are input to the reset circuit for generating two independent reset signals, are delayed. The error detection areas on the leading side and the lagging side of the phase are overlapped, so that even if the error detection range due to the unbalance of the element performance due to manufacturing variations of the element relatively changes, the error detection area It is possible to prevent a sharp cut, and it is possible to prevent a dead zone from being generated in the error detection characteristics.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a phase comparator according to the present invention.

FIG. 2 shows a NAND circuit in the phase comparator of FIG.
It is a block diagram of a phase comparator shown by replacing with a flip-flop.

FIG. 3 is a timing chart for explaining an operation of the phase comparator shown in FIG. 2;

FIG. 4 is a timing chart showing the phase relationship between error signals UPB and DWB when reference signal REF is advanced by more than the phase of comparison signal IN for explaining the operation of the phase comparator shown in FIG. 2;

FIG. 5 shows error signals UPB and D when reference signal REF for explaining the operation of the phase comparator shown in FIG. 2 is advanced in a smaller way than in FIG. 4 with respect to the phase of comparison signal IN;
FIG. 4 is a timing chart showing a phase relationship of WB.

6 is a timing chart for explaining the operation of the phase comparator shown in FIG. 2 and showing the phase relationship between the error signals UPB and DWB when the phases of the reference signal REF and the comparison signal IN are the same.

FIG. 7 is a timing chart illustrating the phase relationship between error signals UPB and DWB when reference signal REF lags behind the phase of comparison signal IN for explaining the operation of the phase comparator shown in FIG. 2;

8 is an error signal UPB when the reference signal REF for explaining the operation of the phase comparator shown in FIG. 2 is delayed by a smaller amount than the phase of the comparison signal IN in FIG.
FIG. 4 is a timing chart showing a phase relationship between DWB and DWB.

FIG. 9 is a diagram illustrating the operation of the phase comparator shown in FIG. 2 without variation in element characteristics, and the output range of the error signal for the phase error overlaps between the error signal UPB and the DWB. FIG. 6 is a characteristic diagram showing a relationship between pulse widths in a state in a graph.

10 is a diagram showing the characteristics of elements for explaining the operation of the phase comparator shown in FIG. 2; the output range of the error signal largely overlaps between the error signal UPB and the DWB with respect to the phase error; FIG. 4 is a characteristic diagram showing a graph of a relationship between pulse widths in a state where the pulse width is in a state of being in a state.

11 is a diagram for explaining the operation of the phase comparator shown in FIG. 2; there is a variation in element characteristics, and the output range of the error signal with respect to the phase error is the smallest between the error signal UPB side and the DWB side; FIG. 4 is a characteristic diagram showing a graph of a relationship between pulse widths in a state in which the pulse width is changed.

FIG. 12 is a block diagram showing a state in which a charge pump is connected to the output side of the phase comparator according to the present invention.

FIG. 13 is a block diagram showing a configuration of a second embodiment of the phase comparator according to the present invention.

FIG. 14 is a block diagram showing the configuration of a third embodiment of the phase comparator according to the present invention.

FIG. 15 is a block diagram showing a configuration of a conventional phase date acknowledgment device.

FIG. 16 shows the NA in the conventional phase comparator shown in FIG.
FIG. 4 is a block diagram illustrating a configuration of a phase comparator in which a connection of an ND circuit is replaced with an RS flip-flop.

FIG. 17 is an equivalent circuit diagram of an RS flip-flop configured by a NAND circuit.

FIG. 18 is a timing chart for explaining the operation of the conventional phase comparator shown in FIG.

FIG. 19 is a timing chart showing the phase relationship between error signals UPB and DWB when reference signal REF leads by more than the phase of comparison signal IN for explaining the operation of the conventional phase comparator shown in FIG. is there.

20 shows error signals UPB and DWB when reference signal REF for explaining the operation of the conventional phase comparator shown in FIG. 16 is advanced in a smaller way than that in FIG. 19 with respect to the phase of comparison signal IN. FIG. 4 is a timing chart showing a phase relationship of FIG.

21 is a timing chart for explaining the operation of the conventional phase comparator shown in FIG. 16 and showing the phase relationship between error signals UPB and DWB when the phases of reference signal REF and comparison signal IN are in phase.

FIG. 22 is a timing chart illustrating the phase relationship between error signals UPB and DWB when reference signal REF lags behind the phase of comparison signal IN for explaining the operation of the phase comparator shown in FIG. 16;

FIG. 23 is a timing chart illustrating the operation of the phase comparator shown in FIG. 16;
FIG. 13 is a timing chart showing a phase relationship between the error signals UPB and DWB when the signal is delayed by a smaller delay amount than in the case of FIG.

FIG. 24 is a diagram for explaining the operation of the conventional phase comparator shown in FIG. 16; there is no variation in element characteristics, and the output range of the error signal for the phase error overlaps between the error signal UPB side and the DWB side; FIG. 4 is a characteristic diagram showing a graph of a relationship between pulse widths in a state where the pulse width is in a state of being in a state.

FIG. 25 is a diagram for explaining the operation of the conventional phase comparator shown in FIG. 16 in which the characteristics of the elements vary and the output range of the error signal with respect to the phase error is larger on the error signal UPB side and on the DWB side; FIG. 7 is a characteristic diagram showing a relationship between pulse widths in an overlapping state in a graph.

FIG. 26 is a diagram illustrating the operation of the conventional phase comparator shown in FIG. 16; there is a variation in element characteristics, and the output range of the error signal with respect to the phase error is the overlap range between the error signal UPB side and the DWB side; FIG. 5 is a characteristic diagram showing, in a graph, a relationship between pulse widths in a state where is minimized.

[Explanation of symbols]

11, 12, 14, 15a, 21, 22, 24, 25a
... NAND circuits, 13, 23, RS11, RS12a, RS
13, RS21, RS22a, RS23 ... RS flip-flop circuit, 15, 25 ... delay circuit, 15b, 25b ...
... Inverter, 16, 26, RS12b, RS22b ... A
ND circuit, 100: phase comparator, 200: charge pump, 201: capacitor, IN: comparison signal, ne
t11 to net15, net21 to net25 ... output signal, RE
F: Reference signal, DWB, UPB: Error signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L 7/089 G01R 25/00 H03K 5/26

Claims (11)

(57) [Claims] A first flip-flop circuit for outputting a first error signal in response to a change in the level of a reference signal; a second flip-flop circuit for outputting a second error signal in response to a change in a comparison signal level; A first error detection circuit that holds the level of the reference signal before the level change when the level of the signal changes, and detects an error due to a delay of the reference signal; A second error detection circuit for holding a level and detecting an error due to a delay of the comparison signal; and when the phase of the comparison signal lags behind the phase of the reference signal, the edge when the level of the comparison signal changes is a first delay. propagated delayed by the delay amount by the circuit produces a dead zone is enlarged by the time delay of the first delay circuit in the first direction in which the reference signal lags the comparison signal an error detection range of the error signal
A first reset circuit for resetting the first error detection circuit and, when the phase of the reference signal lags behind the phase of the comparison signal, an edge when the level of the reference signal changes is changed to a second delay circuit It is propagated with a delay by the time delay due to causes a dead zone to expand by the time delay of the second delay circuit to said second direction comparison signal from the reference signal is delayed error detection range of the error signal
Resetting the second error detection circuit as well as Nikuku, a phase comparator, characterized in that it comprises a second reset circuit which is independent of the first reset circuit. 2. The phase comparator according to claim 1, wherein said first error detection circuit comprises an RS flip-flop circuit. 3. The phase comparator according to claim 1, wherein said second error detection circuit comprises an RS flip-flop circuit. 4. The third flip-flop circuit according to claim 1, wherein the first error detection circuit outputs a high level signal when the reference signal falls when the phase of the reference signal lags behind the comparison signal. A fourth flip-flop circuit set by an output signal of the third flip-flop circuit and reset by a reset signal output from the first reset circuit, and an output signal of the fourth flip-flop circuit And a first AND circuit that calculates the logical product of the reset signal of the first reset circuit and the set terminal of the first flip-flop circuit and outputs the result to the reset terminal of the third flip-flop circuit. The phase comparator according to claim 1, wherein: 5. The fifth flip-flop circuit according to claim 5, wherein the second error detection circuit outputs a high level signal when the comparison signal falls when the phase of the comparison signal lags behind the reference signal. A sixth flip-flop circuit set by an output signal of the fifth flip-flop circuit and reset by a reset signal output from the second reset circuit, and an output signal of the sixth flip-flop circuit And a second AND circuit outputting a logical product of the AND signal of the second reset circuit and the set terminal of the second flip-flop circuit and outputting the result to the reset terminal of the fifth flip-flop circuit. The phase comparator according to claim 1, wherein: 6. The first flip-flop circuit according to claim 1, wherein
And the second NAND circuit.
The flip-flop circuit includes the third and fourth NAND circuits.
Is, the first reset circuit, the output signal of the first NAND circuit, the above was passed through the first delay circuit a 3N
NA of the output signal of the AND circuit, the output signal of the first error detection circuit, and the output signal of the second error detection circuit
2. The phase comparator according to claim 1, wherein the first flip-flop circuit and the first error detection circuit are reset by taking ND logic. 7. The first flip-flop circuit according to claim 1, wherein
And the second NAND circuit.
The flip-flop circuit includes the third and fourth NAND circuits.
Is, the second reset circuit, the output signal of said first 1 NAND circuit through the second delay circuit and said second 3N
NA of the output signal of the AND circuit, the output signal of the first error detection circuit, and the output signal of the second error detection circuit
2. The phase comparator according to claim 1, wherein the second flip-flop circuit and the second error detection circuit are reset by taking ND logic. 8. The first flip-flop circuit according to claim 1, wherein
And is constructed from a 2NAND circuitry, said second flip
The flip-flop circuit includes the third and fourth NAND circuits.
Is, the first reset circuit includes an AND circuit for taking a logical product of the output signal of the output signal and the second error detection circuit of the first 3NAND circuit through said first delay circuit,
NAN of the output signal of the first NAND circuit, the output signal of the first error detection circuit, and the output signal of the AND circuit
2. The phase comparator according to claim 1, further comprising: a NAND circuit that resets the first error detection circuit and the first flip-flop circuit by taking D logic. 9. The first flip-flop circuit according to claim 1, wherein
And the second NAND circuit.
The flip-flop circuit includes the third and fourth NAND circuits.
Is, the second reset circuit includes an AND circuit for taking a logical product of the output signal of the output signal and the first error detection circuit of the first NAND circuit through the second delay circuit,
NAN of the output signal of the third NAND circuit, the output signal of the second error detection circuit, and the output signal of the AND circuit
2. The phase comparator according to claim 1, further comprising: a NAND circuit for resetting the second error detection circuit and the second flip-flop circuit by taking D logic. 10. The second flip-flop circuit according to claim 1, wherein
A third NAND circuit, wherein the first delay circuit is a NAND circuit that performs NAND logic on an output signal of the third NAND circuit and an output signal of the second error detection circuit.
2. The phase comparator according to claim 1, further comprising: a D circuit; and an inverter for inverting an output signal of the NAN circuit. 11. The first flip-flop circuit according to claim 1, wherein
A second NAND circuit, wherein the second delay circuit is a NAND circuit that performs NAND logic on an output signal of the first NAND circuit and an output signal of the first error detection circuit.
2. The phase comparator according to claim 1, further comprising: a D circuit; and an inverter for inverting an output signal of the NAND circuit.