JP2001069000A - Pll system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL system that has a short lockup time and requires less power. SOLUTION: The PLL system is provided with a generating means 6 that generates a plurality of reference signals whose phases differ from each other, a plurality of variable frequency dividers 11-14 that frequency-divides an output of a voltage controlled oscillator 15 to provide an output of each feedback signal, a plurality of phase comparators 7-10 that compares a phase of each reference signal with a phase of each feedback signal, and a control section 30. Then the control section 30 controls a preset signal of each of the variable frequency dividers 11-14 in matching with each phase of each reference signal to start frequency-division of each of the variable frequency dividers 11-14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PLL device.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus has been known, for example, as "SA".
NYO TECHNICAL REVIEW ”, VO
L. 10, NO. 1, FEB. This is shown in FIG. 1 on page 32 of 1978. According to FIG. 1, a reference oscillator that generates a reference signal RF, a variable frequency divider that divides an output signal FO to generate a feedback signal FV, and sets the phase and frequency of the feedback signal FV to the phase and frequency of the reference signal. Compared to the frequency,
One phase comparator for generating the error signal ER is provided. A low-pass filter that generates a control voltage CV in response to the error signal ER and a voltage-controlled oscillator that generates an output signal FO in response to the control voltage CV are provided.

[0003]

However, in this PLL device, the relationship between the frequency of the reference signal RF and the lock time is theoretically and unitarily determined if it is optimally designed.
Therefore, there is a first disadvantage that the lock time cannot be further reduced. In order to solve this, the inventor tried a configuration in which a plurality of reference signals having different phases are generated, and a phase comparator and a variable frequency divider are provided in multiple stages.

However, even with the above configuration, the lock time is not shortened. The inventor of the present invention has investigated the cause, and has found that the frequency division start timing of each variable frequency divider does not match the phase of each reference signal. Furthermore, in the above configuration, since the multi-stage variable frequency divider is operated even after the lock,
There is a second disadvantage of high power consumption. Therefore, the present invention provides a PLL device having a short lock-up time and low power consumption in consideration of such conventional disadvantages.

[0005]

In order to solve the above-mentioned problems, according to the present invention, there are provided a generating means for generating a plurality of reference signals having different phases, an output of a voltage-controlled oscillator being frequency-divided, and each feedback being provided. A plurality of variable frequency dividers that output signals, a plurality of phase comparators that compare the phases of the reference signals and the feedback signals, and a control unit, wherein the control unit adjusts the phase of each of the reference signals. By controlling the preset signal of each of the variable frequency dividers, the frequency dividing operation of each of the variable frequency dividers is started.

According to the second aspect of the present invention, when one of the variable frequency dividers starts the frequency dividing operation, the other variable frequency divider stops the frequency dividing operation. Control.

According to a third aspect of the present invention, when the one variable frequency divider starts a frequency dividing operation, the other variable frequency divider controls the control so that frequency-divided data is preset. I do.

According to the present invention, when the control unit detects a locked state or a state close to the locked state after dividing all of the variable frequency dividers, the control unit performs division by one of the variable frequency dividers. The frequency dividing operation is continued, and the frequency dividing operation of the other variable frequency divider is stopped.

According to a fifth aspect of the present invention, one of the variable frequency dividers that continues the frequency dividing operation is the variable frequency divider in which the control unit detects a locked state or a state close to the locked state. .

[0010]

FIG. 1 is a block diagram showing a PLL device according to an embodiment of the present invention. FIG.
The reference oscillator 2 outputs a reference signal FR1. The delay circuits 3, 4, 5 respond to the reference signal FR1 and a plurality of reference signals FR2, FR3, FR having different phases from each other.
4 is generated. These reference oscillator 2, delay circuit 3,
4 and 5 constitute (reference signal) generating means 6. More specifically, the reference signal FR1 is
Is input to The delay circuit 3 delays the reference signal FR1 by １ ／ cycle, and outputs it to the phase comparator 8 as the reference signal FR2. The delay circuit 4 sets the reference signal FR1 to 1
/ 2 period, and outputs it to the phase comparator 9 as the reference signal FR3. The delay circuit 5 receives the reference signal FR1
Is delayed by 3/4 cycle, and the result is output to the phase comparator 10 as the reference signal FR4.

Each input side of the variable frequency dividers 11, 12, 13, 14 is connected to the output side of the voltage controlled oscillator 15,
The frequency is divided by an integer division ratio. Variable frequency divider 1
1 will be described with reference to the block diagram of FIG. Variable frequency divider 1
2, 13, and 14 have the same configuration as the variable frequency divider 11.
In FIG. 2, the variable frequency divider 11 includes, for example, an input terminal a, an inverter b, and toggle flip-flops c, d, e,
f, g, an inverter h, an AND gate i, a D-flip-flop j, an output terminal k, and the like. The inverter b is connected between the input terminal a and the toggle flip-flop c. Each of the toggle flip-flops c to g has, for example, a built-in input inversion function, and is connected in series. The J terminals of the toggle flip flops c to g are input terminals D1, D2, D3, D
4, D5.

A counter m is constituted by the toggle flip-flops c to g. The counter m uses an inverted signal of the output signal VO as a clock pulse and a frequency division ratio (divided data) N given to the input terminals D1 to D5. Count down,
The down count is preset by the preset signal PR applied to the preset terminal n. The matching circuit p includes an inverter h and an AND gate i. Each output terminal Q of the toggle flip-flops c, e, f, and g is connected to the input terminal of the AND gate i. The output terminal Q of the toggle flip-flop d is connected via an inverter h.
It is connected to the input terminal of AND gate i. Thus, when the output of the counter m becomes "2", the coincidence circuit p outputs the detection signal CO which becomes High.

The D flip-flop j has, for example, a built-in input inversion function, and uses the inverted signal of the output signal VO as a clock pulse to detect the detection signal CO of the coincidence circuit p.
Is delayed by one division of the output signal VO to a terminal Q.
Output from That is, the feedback signal FV1 is output from the output terminal k. One input side of the OR gate q is connected to the output terminal Q of the D-flip-flop j, and the other input side is connected to the enable terminal 22 via the inverter r. The output side of OR gate q is preset terminal n
It is connected to the. The enable terminal 22 is connected to an output terminal of a gate control circuit 31 (described later). The variable frequency divider 11 is configured by the above components. Note that enable terminals 23, 24, 25 provided in the variable frequency dividers 12, 13, 14 are connected to respective output terminals provided in the gate control circuit 31.

Referring again to FIG. 1, the phase comparator 7 compares the phase and frequency of the output (feedback signal FV1) of the variable frequency divider 11 with the phase and frequency of the reference signal FR1.
As a result of the comparison, the phase comparator 7 outputs a pump-up signal and a pump-down signal to two output terminals (not shown), respectively. The detector 7a is composed of an AND gate or the like, and ANDs the pump-up signal and the pump-down signal, and outputs the signal (lock detection signal) to a microcomputer (microcomputer) 16. The locked state is detected by the detector 7a. The charge pump 17 receives a pump-up signal and a pump-down signal, and outputs an error signal ER.
Outputs 1. Similarly, the phase comparator 8 includes a variable frequency divider 12
Of the feedback signal FV2 and the reference signal FR
Compare the phase and frequency of the two. As a result of the comparison, the phase comparator 9 outputs a pump-up signal and a pump-down signal to the detector 7b, and the detector 7b ANDs the two signals and outputs the result to the microcomputer 16. The charge pump 18 receives the two signals and outputs an error signal ER2.

Also, the phase comparator 9 is configured to determine the phase and frequency of the feedback signal FV3 of the variable frequency divider 13 and the reference signal FR3.
Are compared with each other in phase and frequency. As a result of the comparison, the phase comparator 9 outputs a pump-up signal and a pump-down signal to the detector 7c, and the detector 7c ANDs the two signals and outputs the result to the microcomputer 16. The charge pump 19 receives the two signals and outputs an error signal ER3. The phase comparator 10 compares the phase and frequency of the feedback signal FV4 of the variable frequency divider 14 with the phase and frequency of the reference signal FR4. As a result of the comparison, the phase comparator 10 outputs a pump-up signal and a pump-down signal to the detector 7d. The detector 7d performs an AND operation on the two signals and outputs the result to the microcomputer 16. The charge pump 20 receives the two signals and outputs an error signal ER4. As described above, each of the phase comparators 7, 8, 9, and 10 outputs the reference signal FR1, FR2, F
R3, FR4 and each feedback signal FV1, FV2, FV3,
FV4, and as a result, each error signal E
R1, ER2, ER3, and ER4 are output.

The low-pass filter 21 includes a phase comparator 7,
Error signals ER1, ER2, ER3 from 8, 9, 10
In response to the control signal ER4, the control voltage CV is
Output to The voltage controlled oscillator 15 controls the control voltage CV
Generates an output signal VO. Gate 26
The output side of the charge pump 17 and the low-pass filter 21
Is provided between the input side. The gate 27 is provided between the output side of the charge pump 18 and the input side of the low-pass filter 21. The gate 28 is provided between the output side of the charge pump 19 and the input side of the low-pass filter 21. The gate 29 is provided between the output side of the charge pump 20 and the input side of the low-pass filter 21.

The control unit 30 comprises, for example, the microcomputer 16, a gate control circuit 31, and the like. The gate control circuit 31 outputs control signals G1, G2, G3, and G4 based on each signal from the microcomputer 16 and the input of the reference signals FR1 to FR4. The control signal G1 is supplied to the enable terminal 22 and the gate 26, the control signal G2 is supplied to the enable terminal 23 and the gate 27, the control signal G3 is supplied to the enable terminal 24 and the gate 28, and the control signal G4
Is supplied to the enable terminal 25 and the gate 29.

Next, the gate control circuit 31 will be described with reference to the block diagram of FIG. In FIG. 3, one of the OR gates 32
A start signal is input to the other input side. The tuning key (not shown) is connected to the microcomputer 16, and when the user selects a frequency of, for example, 300 KHZ with the tuning key and presses a start key (not shown), the start signal becomes O.
Input to the R gate 32. If the user changes the frequency to, for example, 500 KHZ with the selection key while outputting a signal having a frequency of 300 KHZ, a frequency change command is input to the OR gate 32. Further, the unlock signal is input to the other input side of the OR gate 32. The unlock signal is an output signal V during lock due to a cause other than the above-mentioned input by the user (for example, a disturbance factor).
This signal indicates that O has been unlocked.

The input terminal S of the flip-flop 33 is OR
It is connected to the output side of the gate 32. The input terminal R of the flip-flop 33 is connected to the input terminal S of the flip-flop 34, and the output terminal Q of the flip-flop 33 is connected to the one-shot circuit 35. The lock detection signal is input to the input terminal S of the flip-flop 34. The lock detection signal is, as described above, the charge pump 1
Detectors 7a, 7 respectively connected to 7, 18, 19, 20
b, 7c and 7d are signals output via the microcomputer 16. The lock detection signal is a signal that detects that the output signal VO output from the voltage controlled oscillator 15 has reached the set frequency.

The input terminal R of the flip-flop 34 is connected to the input terminal S of the flip-flop 33. The output terminal Q of the flip-flop 34 is connected to one input side of the OR gate 36. The input terminal D of the D-flip-flop 37 is connected to the output terminal Q of the flip-flop 33, the clock terminal CL receives the reference signal FR1, and the output terminal Q is connected to the input terminal D of the D-flip-flop 38. ing. Also, flip-flop 3
The output terminal Q of 7 is connected to one input side of the AND gate 39. The reference signal FR2 is input to the clock terminal CL of the D-flip-flop 38, the output terminal Q is connected to the input terminal D of the D-flip-flop 40, and the output terminal Q is connected to one input side of the AND gate 41. Have been.

A reference signal FR3 is input to a clock terminal CL of the D-flip-flop 40, and its output terminal Q is
The output terminal Q is connected to one input side of the AND gate 43; A reference signal FR4 is input to a clock terminal CL of the D-flip-flop 42, and an output terminal Q thereof is connected to one input side of the AND gate 44. Also, AN
The other input side of each of the D gates 39, 41, 43, and 44 is
It is connected to the output terminal Q of the flip-flop 33 via the lead wire 45. The output side of the AND gate 39 is
Connected to the other input side of the R gate 36, the OR gate 3
6 outputs a control signal G1. A control signal G is output from each output side of the AND gates 41, 43 and 44, respectively.
2, G3 and G4 are output. With these parts, P
The LL device 1 is configured.

Next, referring to FIG. 1 to FIG.
The operation of the device 1 will be described. FIG. 4 is a timing chart of each signal used in the PLL device 1. In these figures, the user selects a frequency of, for example, 300 KHZ with a channel selection key, presses a start key, outputs an output signal VO of 300 KHZ, and then the user selects a frequency of, for example, 500 KHZ with a channel selection key. An example in which the frequency is changed to is shown. When the output signal VO of 300 KHZ is first output (the output signal VO is locked at this time), the detectors 7a to 7a to
7d outputs a lock detection signal. Since the signal is a one-shot signal, at time A1 (see FIG. 4), Lo is detected.
Signal.

Next, the user operates the tuning key, and
Suppose that KHZ is changed to 500KHZ. In accordance with the above change, a frequency change command is input to the OR gate 32. At this time, since the command is formed in a one-shot type, it becomes a Hi signal for a short time and then becomes a Lo signal (see A2 in FIG. 4). At this time, the Hi signal is input to the input terminal S of the flip-flop 33, and the L level is input to the input terminal R.
o signal is input, a Hi signal is output from the output terminal Q,
This signal is output as a reset signal via the one-shot circuit 35 (see A3 in FIG. 4). The Lo signal is input to the input terminal S of the flip-flop 34 and the input terminal R
, And the output terminal Q outputs a Lo signal. As a result, the Lo signal is input to both input sides of the OR gate, and the control signal G1 is switched from the Hi signal to the Lo signal, and is maintained in the Lo state until a predetermined time elapses after the switching (A4 in FIG. 4). See). Similarly, after the reset signal is output (A3 in FIG. 4), the control signals G2, G3, and G4 are maintained in the Lo state for a predetermined time (A in FIG. 4).
5, A6, A7).

At this time, the variable frequency dividers 11, 12, 13, 1
The Lo signal is input to the enable terminals 22, 23, 24 and 25 of No. 4. As a result, as shown in FIG. 2, the Lo signal is converted into a Hi signal by the inverter r, and the Hi signal is input to the other input side of the OR gate q. The OR gate q is connected to the PE provided in the toggle flip-flops c, d, e, f and g via the preset terminal n.
A preset signal (Hi signal) is output to terminals 1, 2, PE3, PE4, and PE5.

As a result, each of the flip-flops c to
g stops the counting operation and sets the count value to a predetermined value. That is, the variable frequency dividers 11, 12, 13, and 14 all stop the frequency division operation, and the frequency division data is preset. At this time, the gates 26, 27, 28, and 29 are also closed, so that the error signals ER1, ER2, ER3, and ER4 are closed.
Are not output to the low-pass filter 21. As described above, the control unit 30 resets each of the variable frequency dividers 11 before the variable frequency dividers 11 to 14 start the frequency dividing operation.

Further, even after the predetermined time has elapsed, the flip-flop 33 continues to output the Hi signal, and the Hi signal continues to be input to the input terminal D of the D-flip-flop 37. Then, the output of the D-flip-flop 37 rises as a Hi signal in accordance with the rise of the reference signal FR1 input from the clock terminal CL (see A8 in FIG. 4).
At this time, since both input sides of the AND gate 39 are Hi signals, a Hi signal is output, one input side of the OR gate 36 becomes a Lo signal, the other becomes a Hi signal, and the control signal G1 becomes a Hi signal. (See A9 in FIG. 4). At this time, the control signals G2, G3, G4 are L
o signal remains.

As described above, since the control signal G1 has risen as a Hi signal, the Hi signal is input to the enable terminal 22 of the variable frequency divider 11 as shown in FIG. As a result, the Hi signal is converted into a Lo signal by the inverter r, and the Lo signal is input to the other input side of the OR gate q. The OR gate q is connected to P via a preset terminal n.
A preset release signal (Lo signal) is output to terminals E1 to PE5. By the above signal, the variable frequency divider 11
Start the frequency division operation. The control unit 30 includes input terminals D1 to D
5, a Hi signal or a Lo signal has already been output corresponding to the set frequency division ratio. At this time, the input terminal a
The output signal Vo is input, and a signal obtained by inverting the output signal VO is input to the toggle flip-flop c. And the signal Q
1 is delayed by one division of the output signal VO, and
The waveform is obtained by dividing O by two.

The signal Q2 is delayed from the signal Q1 by a predetermined phase, and has a waveform obtained by dividing the signal Q1 by two. Signal Q3
Is a waveform obtained by delaying the signal Q2 by a predetermined phase and dividing the signal Q2 by two. The signal Q4 is delayed from the signal Q3 by a predetermined phase, and has a waveform obtained by dividing the signal Q3 by two. The signal Q5 has a waveform obtained by delaying the signal Q4 by a predetermined phase and dividing the signal Q4 by two.

The AND gate i logically ANDs the signals Q1, Q2, Q3, Q4, and Q5 and outputs a signal CO. The detection signal CO is delayed by one division of the output signal VO, and is output from the output terminal k as a feedback signal FV1. Terminals PE1 to P of toggle flip-flops c to g
By applying the preset signal PR to E5, the signals Q1 to Q5 have waveforms in which the down-count is preset. In this way, the variable frequency divider 11 outputs the output signal VO
Is output to the phase comparator 7 by dividing N by N.

As described above, when the control signal G1 rises (see A9 in FIG. 4), the control signals G2, G3, G4
Remains Lo (see A5, A6, A7 in FIG. 4). As described above, when the Lo signal is input to the enable terminals 23, 24, and 25 of the variable frequency dividers 12, 13, and 14,
As described above, the Hi signal is input to the other input side of each of the OR gates q of the variable frequency dividers 12, 13, and 14. As a result, the OR gate q outputs a preset signal (Hi signal) to the terminals PE1 to PE5. Then, each of the toggle flip-flops c to g stops the counting operation and sets the count value to a predetermined value. That is, each of the variable frequency dividers 11 to 1
When one of the four (for example, the variable frequency divider 11) starts the frequency division operation, the other variable frequency dividers 12, 13, and 14 stop the frequency division operation, and the frequency division data is preset.

After a further lapse of time, the Hi signal is input to the input terminal D of the D flip-flop 38, and the rising edge of the reference signal FR2 input from the clock terminal CL (FIG. 4).
A10), the output of the D-flip-flop 38 is input to one input side of the rising AND gate 41 as a Hi signal. At this time, since the other input side of the AND gate 41 is also a Hi signal, the control signal G2 rises as a Hi signal (see A11 in FIG. 4).

A Hi signal is input to the input terminal D of the D-flip-flop 40, and the D-flip-flop 40 is driven in accordance with the rising edge of the reference signal FR3 input from the clock terminal CL (see A12 in FIG. 4). The output rises as a Hi signal and is input to one input side of the AND gate 43. At this time, since the other input side of the AND gate 43 is also a Hi signal, the control signal G3 rises as a Hi signal (see A13 in FIG. 4).

Further, a Hi signal is input to the input terminal D of the D-flip-flop 42, and the rising edge of the reference signal FR4 input from the clock terminal CL (see A14 in FIG. 4) causes the D-flip-flop 42 to input the Hi signal. The output rises as a Hi signal and is input to one input side of the AND gate 44. At this time, since the other input side of the AND gate 44 is also a Hi signal, the control signal G4 rises as a Hi signal (see A15 in FIG. 4).

That is, in response to the rise (A8) of the reference signal FR1, the control signal G1 rises (A9) and the variable frequency divider 1
1, a Hi signal is input to the enable terminal 22 of PE1.
A preset release signal is input to the PE5 terminal, and the variable frequency divider 11 starts a frequency dividing operation. At this time, gate 26
Is open, and the phase comparator 7 outputs the feedback signal FV1 and the reference signal FV1.
R1 and the phase of the error signal ER1 (A16 in FIG. 4).
Is output. Further, since the control signals G2, G3, G4 are Lo signals, the variable frequency dividers 12, 13, 14 stop the frequency division operation, and the frequency division data is preset.

When the time further elapses, the control signal G2 rises (A11 in FIG. 4) in response to the rise (A10) of the reference signal FR2, and the variable frequency divider 12 starts the frequency dividing operation.
At this time, the gate 27 opens and the phase comparator 8 outputs the feedback signal FV.
2 and the reference signal FR2 (A1 in FIG. 4).
7) Output the error signal ER2. Also, the control signal G
3 and G4 are Lo signals, so that the variable frequency dividers 13 and 14
Stops the frequency division operation, and the frequency division data is preset.

After a further lapse of time, the control signal G3 rises (A12) according to the rise (A12) of the reference signal FR3.
13), the variable frequency divider 13 starts the frequency dividing operation. At this time, the gate 28 opens, and the phase comparator 9 outputs the feedback signal FV3
And the reference signal FR3 in phase comparison (A18 in FIG. 4),
An error signal ER3 is output. The control signal G4 is Lo.
Since the signal is a signal, the variable frequency divider 14 stops the frequency dividing operation,
Divided data is preset. Further time elapses, and the control signal G is set according to the rise (A14) of the reference signal FR4.
4 rises (A15), and the variable frequency divider 14 starts the frequency dividing operation. At this time, the gate 29 opens and the phase comparator 10
Compares the phase of the feedback signal FV4 with the phase of the reference signal signal FR4 (A19 in FIG. 4) and outputs an error signal ER.

As described above, the control unit 30 controls each reference signal FR
1 to FR4 (for example, rising A8, A10, A1
2, A14, etc.), the frequency dividing operation of each of the variable frequency dividers 11 to 14 is started. Specifically, the gate control circuit 31 of the control unit 30 controls each of the variable frequency dividers 11 to 11 according to the control signals G1 to G4 in accordance with the phases of the reference signals FR1 to FR4.
14 preset signals are controlled. Also, as mentioned above,
The reference oscillator 2 has a reference frequency FR (period TR = 1 / FR)
The reference signal FR1 having the following is generated. The delay circuits 3, 4, and 5 cause the reference signals FR2, FR3, FR4
Are each 1/4 cycle (TR /
4) It is formed with a sequential delay.

Then, each of the variable frequency dividers 11, 12, 13,
The start of the frequency division operation of each of the reference signals FR1, FR2, F
The phase is adjusted to the phases of R3 and FR4. Therefore, at the start of the frequency division operation, the signals are sequentially delayed by approximately TR / 4, and the phase comparison timings of the phase comparators 7, 8, 9, and 10 are each delayed by approximately TR / 4. It was done. In this way, by starting the frequency dividing operation of each of the variable frequency dividers 11 to 14 in accordance with the phase of each of the reference signals FR1 to FR4, the phase comparison timing of each of the phase comparators 7 to 10 becomes substantially equal intervals. And accurate phase comparison can be performed. In this way, the reference signals FR1 to FR4 have different phases (for example, the phases are shifted by π / 2 each other in the above description), and the phase comparison is performed for each of the reference signals FR1 to FR4. . As a result, during one cycle (TR) of the reference signal FR1, the phase comparison is performed a plurality of times (in the above description,
A4, A17, A18, and A19), and the lock-up time is reduced to about 1/4 of the conventional lock-up time.

In the above description, the case where the frequency change command is input has been described. However, even when there is no frequency change command (Lo signal) and an out-of-lock signal is input, the output of the OR gate 32 is a Hi signal. At this time,
The PLL device 1 performs the same operation as described above, and the control unit 3
0 starts the frequency dividing operation of each of the variable frequency dividers 11 to 14 in accordance with the phase of each of the reference signals FR1 to FR4. Further, when time elapses and the above-described phase comparison is repeated (see A20, A21, A22, and A23 in FIG. 4), the output signal V
O reaches (locks) the set frequency. At this time, the detectors 7a to 7d connected to any one of the phase comparators 7, 8, 9, and 10 output a lock detection signal to the microcomputer 16. The microcomputer 16 outputs a lock detection signal to the gate control circuit 31 (see A24 in FIG. 4, the lock detection signal is a one-shot type).

Then, a Hi signal (reset signal) is input to the input terminal R of the flip-flop 33, and the flip-flop 33 outputs a Lo signal. As a result, one input side of the AND gates 39, 41, 43, and 44 receives the Lo signal via the lead wire 45, and the gate 39,
41, 43 and 44 output Lo signals. Therefore, the control signals G2, G3, and G4 are Lo signals (A2 in FIG. 4).
6, A27, A28). One input side of the OR gate 36 is connected to the output terminal Q of the flip-flop 34. Since the Hi lock detection signal is input to the input terminal S of the flip-flop 34, the flip-flop 34 outputs the Hi signal and outputs the OR signal to the OR gate 3
The Hi signal is input to one input side of the signal No. 6. As a result, the control signal G1 output from the OR gate 36 becomes H
i, and the Hi state is maintained (see A25 in FIG. 4).

As a result, the enable terminals 23, 24, 2
5, the Lo signal is input, and the variable frequency dividers 12, 13, and 14 stop the frequency dividing operation. At this time, the control signals G2, G3, G
Gates 27, 28 and 29 controlled by 4 are also closed. As a result, the error signals ER2, ER3, ER4 are not output to the low-pass filter 21. As described above, the power consumption can be reduced by stopping the frequency dividing operation of the variable frequency dividers 12, 13, and 14 after the lock is detected. Further, since the control signal G1 is maintained in the Hi state, the Hi signal continues to be input to the enable terminal 22, and the variable frequency divider 11 continues the frequency dividing operation. Then, the phase comparator 7 compares the phase of the feedback signal FV1 output from the variable frequency divider 11 with the phase of the reference signal FR1 (see A29 and A30 in FIG. 4). At this time,
Since the gate 26 controlled by the control signal G1 is open, the charge pump 17 outputs an error signal ER1 to the low-pass filter 21. Low-pass filter 21
Outputs a control signal CV to the voltage controlled oscillator 15, and the voltage controlled oscillator 15 continues to output the output signal VO having the set frequency.

In summary, when the control unit 30 detects a lock (when a lock detection signal is input to the control unit 30), the control unit 30 uses one variable frequency divider (in the above description, the variable frequency divider). To perform the frequency dividing operation. Then, the control unit 30 causes another variable frequency divider (variable frequency dividers 12, 13, and 14 in the above description) to stop the frequency dividing operation. It is also assumed that one of the detectors 7a to 7d (for example, the detector 7d connected to the phase comparator 10) among the detectors connected to the phase comparators 7, 8, 9, and 10 has detected lock. At this time, the control unit 30 performs the frequency division operation only on the variable frequency divider 14 (in the above description, the variable frequency divider 14 connected to the detector 7d connected to the phase comparator 10) that has detected the lock. Let it continue. Then, the control unit 30 causes the other variable frequency dividers 11, 12, and 13 to stop the frequency division operation.

Further, the detectors 7a to 7d may detect a state close to lock, instead of detecting the lock state. That is, when the detectors 7a to 7d detect the predetermined threshold value, the control unit 30 determines that the state is close to the lock. The control unit 30 detects (determines) a state close to lock.
Then, the frequency dividing operation of any one of the variable frequency dividers (11 or 12 or 13 or 14) is continued, and the frequency dividing operation of the other variable frequency dividers is stopped. Desirably, the control unit 30 performs one variable frequency divider (11 or 12 or 13 or 14) detected as a state close to lock to continue the frequency division operation,
Another variable frequency divider is used to stop the frequency dividing operation.

[0044]

According to the first aspect of the present invention, a generating means for generating a plurality of reference signals having different phases, a plurality of variable frequency dividers for dividing the output of the voltage controlled oscillator and outputting respective feedback signals, A plurality of phase comparators for comparing the phases of the reference signals and the feedback signals; and a control unit, wherein the control unit controls the preset signals of the variable frequency dividers in accordance with the phases of the reference signals. By doing so, the frequency dividing operation of each of the variable frequency dividers is started. In this way, by starting the frequency dividing operation of each variable frequency divider in accordance with the phase of each reference signal, the phase comparison timing by each phase comparator becomes substantially equal,
Accurate phase comparison can be performed. The reference signals have different phases, and a phase comparison is performed for each reference signal. As a result, the phase comparison is performed a plurality of times during one cycle of the reference signal, and the lock-up time is shortened as compared with the related art. Since the preset signal of each variable frequency divider is controlled to start the frequency dividing operation of each variable frequency divider, there is no need to provide an external component (such as a gate), and the cost is low.

According to the second aspect of the present invention, when one of the variable frequency dividers starts the frequency dividing operation, the other variable frequency divider stops the frequency dividing operation, Control. In this way, when one variable frequency divider starts the frequency dividing operation, the power consumption can be reduced by stopping the frequency dividing operation of the other variable frequency dividers.

According to the third aspect of the present invention, when one of the variable frequency dividers starts the frequency dividing operation, the other variable frequency divider controls the control so that the frequency division data is preset. I do. As described above, when one variable frequency divider starts the frequency division operation, the other variable frequency divider starts the frequency division operation because the frequency division data is preset in the other variable frequency dividers. , Accurate frequency division with correct frequency division data.

According to the fourth aspect of the present invention, when the control section detects a locked state or a state close to the locked state after dividing all the variable frequency dividers, the control section performs division by one variable frequency divider. The frequency dividing operation is continued, and the frequency dividing operation of the other variable frequency divider is stopped. As described above, after detecting the locked state or the state close to the locked state, the power consumption can be reduced by continuing the frequency dividing operation by one variable frequency divider and stopping the other variable frequency dividers. Further, the output signal having the set frequency can be stably output by the frequency division operation of one variable frequency divider.

According to a fifth aspect of the present invention, one of the variable frequency dividers that continues the frequency dividing operation is the variable frequency divider in which the control unit detects a locked state or a state close to the locked state. . As described above, the variable frequency divider that detects the locked state or the state close to the locked state performs the dividing operation continuously, so that even after the detection, the accurate phase comparison can be performed and the set frequency can be obtained. An output signal can be output stably.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL device 1 according to an embodiment of the present invention.

FIG. 2 shows a variable frequency divider 11 used in the PLL device 1.
It is a block diagram of.

FIG. 3 is a block diagram of a gate control circuit 31 used in the PLL device 1.

FIG. 4 is a timing chart of signals used in the PLL device 1;

[Explanation of symbols]

 Reference Signs List 6 generating means 7, 8, 9, 10 phase comparator 11, 12, 13, 14 variable frequency divider 15 voltage controlled oscillator 30 controller

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC30 CC38 CC41 CC53 CC58 DD08 DD32 DD34 DD42 DD43 DD48 GG09 HH08 HH09 HH10 KK03 KK40 PP03 QQ09 QQ12 RR18

Claims (5)

[Claims] 1. A generator for generating a plurality of reference signals having different phases, a plurality of variable frequency dividers for dividing an output of a voltage controlled oscillator and outputting respective feedback signals, the respective reference signals and the respective feedbacks A plurality of phase comparators for comparing the phases of the signals; and a control unit, wherein the control unit controls the preset signal of each of the variable frequency dividers in accordance with the phase of each of the reference signals, thereby controlling each of the variable frequency dividers. A PLL device for starting a frequency dividing operation of a frequency divider. 2. The control section controls such that when one of the variable frequency dividers starts a frequency dividing operation, the other variable frequency divider stops the frequency dividing operation. Claim 1
PLL device. 3. The control section controls such that when one of the variable frequency dividers starts a frequency dividing operation, the other variable frequency divider presets frequency-divided data. The PLL device according to claim 2. 4. The control unit, after dividing all of the variable frequency dividers and detecting a locked state or a state close to lock, continues the frequency dividing operation of one of the variable frequency dividers, 2. The PLL device according to claim 1, wherein the frequency dividing operation of another variable frequency divider is stopped. 5. The variable frequency divider that continues the frequency dividing operation is the variable frequency divider in which the control unit detects a locked state or a state close to locked.
PLL device.