JP2002217719A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that is short in lockup time and does not reflects error signal onto post-stages. SOLUTION: The PLL circuit is provided with a generating means 2 that generates reference signals, variable frequency dividers 4, 8 that apply frequency division to an output signal of a voltage controlled oscillator VCO and output each feedback signal, and a phase comparator 13 that compares the phases of the reference signals with each other and the PLL circuit is configured not to reflect the error signal onto the voltage controlled oscillator VCO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, this type of circuit is, for example, "SANY
O TECHNICAL REVIEW ”, VOL. 1
0, NO. 1, FEB. It is shown on page 32 of 1978. However, this circuit is a one-stage phase comparator (using only one position comparator) and performs only one phase comparison during one cycle of the reference signal, so that the lock-up time (output The first disadvantage is that the time until the signal is synchronized is short.

[0003] In order to solve this drawback, Japanese Patent Laid-Open No.
No. 135822 has been proposed. According to this publication, generating means for generating a plurality of reference signals having different phases, a plurality of (for example, four) frequency dividers for dividing an output signal of the voltage controlled oscillator, and a feedback signal of each frequency divider are provided. A plurality of phase comparators for comparing each reference signal are provided.

[0004]

However, the circuit disclosed in the above publication has a second drawback in that the power consumption is large. The inventor of the present invention has investigated the cause and found that the reason is that a plurality of frequency dividers are provided. Further, if the phase comparison is performed 16 times during one cycle of the reference signal in order to further reduce the lock-up time, 16 frequency dividers are required, and the power consumption is further increased.

Further, since a plurality of frequency dividers requiring a relatively large amount of space are used, there is a third disadvantage that the size of the apparatus is increased, the cost is increased, and it is difficult to implement an LSI.

The present applicant has filed Japanese Patent Application No. 2000-76250 in order to solve these drawbacks. According to this application, two variable frequency dividers 4 and 9 each have a first feedback circuit. And a second feedback signal. Variable frequency divider 9
Is divided by the division number of an integer part of N / n (N and n are integers) (because a variable frequency divider that performs fractional frequency division has a high cost and a disadvantage that the operation becomes unstable).

As described above, since the frequency is divided by the integer part, the variable frequency divider 9 has an error from the feedback signal to be frequency-divided by the frequency division number N / n. Therefore, the phase comparator PC2 connected to the variable frequency divider 9 outputs a phase comparison signal including the above error (this is called an error signal in this specification). As a result, there is a fourth disadvantage that an output signal having a frequency shifted from the set frequency is output.

Therefore, the present invention provides a PLL circuit which has a short lock-up time, has low power consumption, is low in cost, is easy to be integrated into an LSI, and has a reduced influence of an error signal.

[0009]

In order to solve the above problems, according to the present invention, a generating means for generating a plurality of reference signals, an output signal of a voltage controlled oscillator is divided, and each feedback signal And a phase comparator for comparing the phase of each feedback signal with each reference signal, so that the voltage-controlled oscillator does not reflect an error signal.

According to the second aspect of the present invention, the error signal is reflected at the time of a search, and the error signal is not reflected at the time of near steady state or at the time of steady state.

According to a third aspect of the present invention, the variable frequency divider comprises a first variable frequency divider and a second variable frequency divider, and the first variable frequency divider has a frequency division number N (N is A value obtained by dividing a set frequency by a reference frequency) is set, and the frequency division number N / n (n is an integer of 3 or more) is set in the second variable frequency divider.

According to a fourth aspect of the present invention, there is provided a generating section for generating a signal for determining a dead band width, and a phase comparator connected to the second variable frequency divider uses the signal to generate an error signal at a subsequent stage. Do not tell

According to the fifth aspect of the present invention, the frequency division number N / n
Is composed of an integer part and a remainder part, the second variable frequency divider divides the frequency by the integer part, and the phase comparator does not transmit the error signal generated by the error according to the remainder part to the subsequent stage. .

According to the present invention, the signal is generated according to a reference signal input to the phase comparator.

According to the present invention of claim 7, the generation unit is configured to set the rising or falling time of the reference signal as a center.
The signal is generated so as to distribute the dead band width, and the phase comparison signal of the phase comparator is ANDed with the signal.

In the present invention according to claim 8, the generating means includes:
A plurality of reference signals having different phases are generated, one of the reference signals is a first reference signal, and a first feedback signal output from the first variable frequency divider is compared with a phase of the first reference signal. A phase comparator was provided.

In the ninth aspect of the present invention, a sum of (n-1) reference signals excluding the first reference signal among the n reference signals is a second reference signal, A second phase comparator for comparing the phase of a second feedback signal output from the second variable frequency divider with the second reference signal is provided.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit 1 according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the PLL circuit 1, and FIG. 2 is a time chart of each signal used in the PLL circuit 1.

In these figures, the generating means 2 comprises, for example, a reference oscillator OSC, a fixed frequency divider M, a ring counter RIC, an OR gate 3, and the like. Fixed frequency divider M
Is divided at a frequency division ratio of 64, for example, and is connected between the reference oscillator OSC and the ring counter RIC. The fixed frequency divider M converts the signal (oscillation frequency is, for example, 25.6 MHz) output from the reference oscillator OSC into 64 and divides the signal (frequency is 400 KHz) by a ring counter R
Output to IC.

The ring-type counter RIC is connected to, for example, 16 flip-flops (not shown), and outputs 16 reference signals FR1 to FR16 in response to the input of the 400 kHz signal.

The reference signal FR2 is 1/1 of the reference signal FR1.
It is delayed from the reference signal FR1 by six periods (TR). Similarly, the reference signal FRA (A is an integer from 2 to 16)
Is delayed from the reference signal FR1 by (A-1) / 16 cycle. In this way, each reference frequency of the reference signals FR1 to FR16 is 400 KHz ÷ 16 = 25 KHz, which matches the desired channel space (inter-station frequency). As described above, the generating means 2 generates a plurality of reference signals FR1 to FR16 having different phases.

The first reference signal (reference signal) FR1 is
It is input to one input side of the phase comparator PC1. Reference signal F
Each of R2 to FR16 is input to the input side of the OR gate 3, and the output of the OR gate 3 is input to one input side of the second phase comparator PC2. That is, one first reference signal FR1
Is input to the first phase comparator PC1, the plurality of reference signals FR2 to FR16 are added by the OR gate 3, and the added second reference signal FR is output to the second phase comparator PC1.
2 is input. As described above, the generation unit 2 generates the first reference signal FR1 and the second reference signal FR.

The first variable frequency divider 4 includes, for example, a 2-coefficient prescaler 5, a swallow counter A1, and a course counter N1.
And so on. The 2 coefficient prescaler 5 is, for example,
The frequency division of 64 or 65 is performed. A first match circuit (not shown) is connected to the swallow counter A1, and a second match circuit (not shown) is connected to the course counter N1. The load signal L1 output from the first variable frequency divider 4 is applied to a swallow counter A1 and a course counter N1.

For example, it is assumed that the user has set 1,650,025 KHz using a set frequency key (not shown). The control unit 6 (comprising a microcomputer or the like) connected to the set frequency key calculates the frequency division number N of the first variable frequency divider 4 and outputs it to the first variable frequency divider 4. That is, N =
1,650,025 KHz ÷ 25 KHz = 66,001
(Because the reference frequency is 25 KHz). That is, the first
The variable frequency divider 4 calculates a value obtained by dividing the set frequency by the reference frequency,
The frequency division number N is set.

Based on the frequency division number N, the controller 6 determines the number of times K1 of the swallow counter A1 has been operated and the course counter N1.
Is calculated and set (for example, K1 = 17).
Times, K2 = 1031 times). Thus, the first variable frequency divider 4
Can be switched by the pulse swallow counter with only two types of frequency division, so that the propagation delay time can be reduced and the operation speed can be improved.

As described above, the first feedback signal FP1 obtained by dividing the output signal VO of the voltage controlled oscillator VCO by N is input to the other input side of the first phase comparator PC1.

The first phase comparator PC1 compares the phase of the first reference signal FR1 with the phase of the first feedback signal FP1, and compares the phase comparison signal (pump-up signal U1) with the phase comparison signal (pump-down signal D1). To the first charge pump CP1
Output to That is, the first phase comparator PC1 compares the phase of one first reference signal FR1 with one first feedback signal FP1 output from the first variable frequency divider 4.

The first charge pump CP1 generates a first output voltage ER1 based on the phase comparison signals U1 and D1, and outputs the first output voltage ER1 to the low-pass filter LPF.

The low-pass filter LPF generates a control voltage CV from which the high-frequency component of the first output voltage ER1 has been cut, and outputs it to the voltage-controlled oscillator VCO. The first PLL frequency synthesizer 7 is composed of the generating means 2, the first phase comparator PC1, the first charge pump CP1, the low-pass filter LPF, the voltage-controlled oscillator VCO, the first variable frequency divider 4, and the like. It is configured.

The second variable frequency divider 8 comprises, for example, a 2-coefficient prescaler 9, a swallow counter A2, a course counter N2 and the like. The two-coefficient prescaler 9 performs, for example, frequency division of 32 or 33. A first match circuit (not shown) is connected to the swallow counter A2, and a second match circuit (not shown) is connected to the course counter N2. The load signal L2 output from the second variable frequency divider 8 is applied to a swallow counter A2 and a course counter N2.

As described above, a predetermined frequency division number is given to the second variable frequency divider 8. Assuming that the total number of the plurality of reference signals FR1 to FR16 is n, the second variable frequency divider 8
For example, N / n is given (set). At this time, the second reference signal FR includes (n-1) reference signals FR.
2 to FR16 are added.

For example, if n = 16, the controller 6
Gives the second variable frequency divider 8 a frequency division number consisting of an integer part of N / n. As described above, when N = 66001, N / n = 66601/16 = 4125 + 1/16.

Thus, the frequency division number N / n is composed of an integer part (for example, 4125) and a remainder part (for example, 1/16).
The second variable frequency divider 8 divides the frequency by an integer part, that is, a frequency division number of 4125. For example, if N = 66000, N / n
= 66000/16 = 4125. At this time, the second variable frequency divider 8 divides the frequency by 4125. That is, N
Is an integral multiple of n, the second variable frequency divider 8 calculates the frequency division number N /
n is set.

In the following description, it is assumed that N = 66001, and the second variable frequency divider 8 divides the frequency by a dividing number of 4125. The control unit 6 determines the number of times K3 of the swallow counter A2 has been operated and the course counter N
2 is calculated and set (for example, K3 =
29 times, K4 = 128 times).

As described above, the second variable frequency divider 8 divides the output signal VO of the voltage controlled oscillator VCO by the integer part of N / n, and outputs 16 Hi level signals (TR) per one period TR. Signal, see the dashed line indicated by FP in FIG. 2) fp
1. A second feedback signal FP including FP2 to FP16 is output.

As described above, the phase generated by the generating means 2 is different on one input side of the second phase comparator PC2 (n-
1) A second reference signal FR obtained by adding the reference signals FR2 to FR16 is input. The second feedback signal FP output from the second variable frequency divider 8 is input to the other input side of the second phase comparator PC2.

The second phase comparator PC2 compares the phase of the second feedback signal FP output from the second variable frequency divider 8 with the second reference signal FR, and outputs a phase comparison signal (pump-up signal U2).
And outputs a phase comparison signal (pump-down signal D2).

Thus, the first variable frequency divider 4 and the second
The variable frequency divider 8 constitutes the variable frequency divider 12. The phase comparator 13 is configured by the first phase comparator PC1 and the second phase comparator PC2.

As described above, a plurality of variable frequency dividers 4 and 8 for dividing the output signal VO of the voltage controlled oscillator VCO and outputting the feedback signals FP1 and FP are provided. The phase comparator 13 outputs the feedback signals FP1 and FP and the reference signals FR
1. Compare the phases of FR.

The generator 14 is composed of, for example, a pulse generating circuit, and generates a signal P (see FIG. 1) for determining the dead zone width G (see FIG. 2).

The input side of the generation unit 14 is connected to the output side of the OR gate 3 and receives the second reference signal FR. The output side of the generation unit 14 is commonly (commonized), and the AND gate 15 , 16 are connected to each input side.

The input side of the AND gate 15 is connected to one output side of the second phase comparator PC2, and the pump-up signal U
2 is input. The output side of the AND gate 15 is connected to one input side of the second charge pump CP2.

The input side of the AND gate 16 is connected to another output side of the second phase comparator PC2, and the pump-down signal D
2 is input. The output side of the AND gate 16 is connected to another input side of the second charge pump CP2.

As described above, the generator 14 receives the second reference signal FR. The generator 14 generates the signal P according to the second reference signal FR input to the second phase comparator PC2.

The generating section 14 generates a signal P in which the dead zone G is distributed so that the left and right sides are equalized, for example, around the rising points FR2, FR3,... FR16 of the reference signal FR, and AND gates 15, 16 Is output.

By the AND gates 15 and 16, the phase comparison signals U2 and D2 of the second phase comparator PC2 and the signal P
Is ANDed and output to the second charge pump CP2 as integrated signals U3 and D3.

The second charge pump CP2 generates a second output voltage ER2 based on the integrated signals U3 and D3.
The second output voltage ER2 is output to the low-pass filter LPF.

The low-pass filter LPF has a second output voltage E
A control voltage CV in which a high-frequency component of R2 is cut off is generated,
Output to the voltage controlled oscillator VCO. These generating means 2
, A second phase comparator PC2, a generator 14, AND gates 15 and 16, a second charge pump CP2, a low-pass filter LPF, a voltage controlled oscillator VCO, a second variable frequency divider 8, and the like. 2PLL frequency synthesizer 1
0 is configured.

Next, the operation of the PLL circuit 1 will be described with reference to FIGS. First, it is assumed that, for example, the user sets 1,650,025 KHz with the set frequency key and presses the start key.

The control section 6 controls the first variable frequency divider 4 to divide the frequency N = 1,650,025 KHz / 25 KHz = 66.
001 is output. At the same time, the control unit 6 supplies the second variable frequency divider 8 with an integer part of N / 16, that is, a frequency division number 412
5 is output.

The oscillation signal from the reference oscillator OSC (25.
6 MHz) is divided by the fixed frequency divider M so as to be 400 KHz, and the generating means 2 outputs a plurality of reference signals FR1 to FR16 having different phases. Reference signal FR
1 to FR16 have a reference frequency of 25 KHz and rise at timings t1 to t16, respectively (see FIG. 2).

The first variable frequency divider 4 includes a voltage controlled oscillator VC
The output signal VO from O is divided by a division number N = 66000 to generate a first feedback signal FP1, and the first feedback signal FP
1 (see FP1 shown by a broken line in FIG. 2) as the first
Output to the phase comparator PC1.

The first phase comparator PC1 outputs the first reference signal F
R1 and the first feedback signal FP1 (broken line) are compared in phase, and the first
For the charge pump CP1, the phase comparison signals U1, D1
Is output.

The first charge pump CP1 supplies a low-pass filter LPF according to the phase comparison signals U1 and D1.
The first output voltage ER1 is output. Low-pass filter LP
F is a voltage controlled oscillator VCO according to the first output voltage ER1.
Outputs a control voltage CV.

The second variable frequency divider 8 divides the frequency of the output signal VO by the dividing number of the integer part (4125) of N / 16,
Second feedback signal FP (Hi level signals fp1, FP2 to FP
P16, and outputs the FP indicated by the broken line in FIG. 2).

Next, the second phase comparator PC2 compares the phases of the second reference signal FR and the second feedback signal FP, and outputs the phase comparison signals U2 and D2 to the AND gates 15 and 16, respectively.

That is, the second phase comparator PC2 makes a phase comparison between the rising FR2 of the second reference signal FR and the Hi level signal (feedback signal) FP2 (broken line) in the second feedback signal FP. U2 and D2 are output. Similarly, the second
The phase comparator PC2 detects the rising FRA of the second reference signal FR.
(A is an integer from 3 to 16) and a Hi level signal (feedback signal) FPA (A is an integer from 3 to 16) in the second feedback signal FP, and the phase comparison signals U2 and D
2 is output.

At this time, as described above, the second variable frequency divider 8
Is divided by a frequency division number composed of an integer part of N / 16 (for example, 4125), so that an accurate frequency division number N / 16 (for example, 4125)
125.0625). Therefore, at this time, the second
The phase comparator PC2 compares the phase of the second feedback signal FP having the deviation (error) of the frequency division number with the phase of the second reference signal FR, and outputs phase comparison signals U2 and D2. Therefore, the phase comparison signals U2 and D2 are error signals based on the error.

At this time, the generator 14 outputs a signal P (at this time, a Hi level signal) to the AND gates 15 and 16. The Hi level signal in the signal P and the second
Hi level signal (FP2 to FP1) in the feedback signal FP
6 (broken line portions) are integrated by the AND gates 15 and 16 to become integrated signals U3 and D3.

The second charge pump CP2 outputs the integrated signal U
3, the second output voltage ER2 is output to the low-pass filter LPF according to the inputs of D3. The low-pass filter LPF outputs a control voltage CV to the voltage controlled oscillator VCO according to the second output voltage ER2.

As described above, at the time of the search of the PLL circuit 1, the second phase comparator CP2 reflects the error signal in the subsequent stage (that is, outputs the error signal to the second charge pump CP2). At the time of search, the frequency of the output signal VO is apart from the set frequency, so that the second phase comparator C
Even if P2 outputs an error signal, there is no problem in practical use.

With this configuration, 1 of the first reference signal FR1
Since the phase comparison is performed 16 times during the period TR (FIG. 2)
), The lock-up time (the time until the output signal VO substantially reaches the set frequency) is reduced to about 1/16 times as compared with the conventional single-stage phase comparator.

Thus, when the above phase comparison is repeated,
The output signal VO approaches the set frequency (this state is referred to as "when the state is near steady state").

When the steady state is reached, the first feedback signal FP
1 (see FP1 shown by a solid line in FIG. 2) approaches the first reference signal FR1 (that is, the phase difference between the two becomes smaller).

The first phase comparator PC1 outputs the first reference signal F
R1 and the first feedback signal FP1 (solid line) are compared in phase.
For the charge pump CP1, the phase comparison signals U1, D1
Is output.

The first charge pump CP1 supplies a low-pass filter LPF according to the phase comparison signals U1 and D1.
The first output voltage ER1 is output. Low-pass filter LP
F is a voltage controlled oscillator VCO according to the first output voltage ER1.
Outputs a control voltage CV. As a result, the frequency of the output signal VO further approaches the set frequency.

The second feedback signal FP (in FIG. 2,
FP2 to FP16 indicated by solid lines) approach the rising edges FR2 to FR16 of the second reference signal FR.

Next, the second phase comparator PC2 compares the phase of the rising edge FR2 of the second reference signal FR with the Hi level signal FP2 (solid line) of the second feedback signal FP, and compares the phase comparison signals U2 and D2. Is output.

Similarly, the second phase comparator PC2 outputs the rising FRA (A is an integer from 3 to 16) of the second reference signal FR and the Hi level signal FP in the second feedback signal FP.
A (A is an integer from 3 to 16 and FPA is a solid line) performs phase comparison and outputs phase comparison signals U2 and D2. At this time, as described above, the phase comparison signals U2 and D2 are error signals having a frequency division number error.

When the second feedback signal FP (solid line) is H
When outputting the i-level signal, the generation unit 14 outputs a signal P (at this time, a Lo-level signal) to the AND gate (see FIG. 2). The Lo level signal of this signal P and the Hi level signal (FP2) of the second feedback signal FP
To FP16) are integrated (and) by the AND gates 15 and 16, and the integrated signal U which is a Lo signal.
3, D3.

The second charge pump CP2 outputs the integrated signal U
3, low-pass filter L according to input of D3 (Lo signal)
The second output voltage ER2 (Lo signal) is output to the PF. The low-pass filter LPF is connected to the second output voltage ER2
In accordance with the (Lo signal), a control voltage CV (Lo signal) is output to the voltage controlled oscillator VCO.

As described above, when the PLL circuit 1 is close to the steady state, the second phase comparator P connected to the second variable frequency divider 8
C2 outputs a Lo signal according to the Lo signal input to the AND gates 15 and 16. That is, the second phase comparator P
The signal C2 does not transmit (do not output) an error signal to a subsequent stage (that is, components after the second charge pump CP2) in response to the signal P.

In other words, the second phase comparator PC2 calculates N
An error signal generated by an error according to the remainder of / 16 (in the above description, 1/16) is not transmitted to the subsequent stage. In other words, the configuration is such that the error signal is not reflected on the voltage controlled oscillator VCO when it becomes close to the steady state.

As described above, in the second PLL frequency synthesizer 10, no error signal is output to the voltage controlled oscillator VCO, but in the first PLL frequency synthesizer 7, the above-described phase synchronization operation is continuously performed.

As described above, when the above-mentioned phase comparison is repeated in the first PLL frequency synthesizer 7, the output signal VO is output.
Is within the set frequency ± 300 Hz. This state is called a steady state.

Even in this steady state, the second PLL frequency synthesizer 10 controls the voltage controlled oscillator VCO
The error signal is not reflected (output).

As described above, after reaching the steady state, the lock detector 11 outputs a Hi signal (synchronous detection signal) to the control unit 6. In response to the input of the synchronization detection signal, the control unit 6 stops the second variable frequency divider 8, and the second phase comparator P
C2 is stopped, and the second tube pump CP2 is stopped.

Further, in response to the input of the synchronization detection signal, the control section 6 continues the operation of only the first variable frequency divider 4 and the first PL
The operation of the L frequency synthesizer 7 is continued, and the second PLL
The operation of the frequency synthesizer 10 is stopped.

As described above, the error signal is not output to the voltage controlled oscillator VCO when the PLL circuit 1 is near the steady state or in the steady state.

Therefore, the first PLL frequency synthesizer 7
Here, the first feedback signal FP1 accurately divided by the division number N by the first variable frequency divider 4 has no error. As a result, the first phase comparator PC1 makes a phase comparison between the accurate first feedback signal FP1 containing no error and the first reference signal FR1.

Therefore, the first phase comparator PC1 outputs accurate phase comparison signals U1 and D1 including no error signal to the first charge pump CP1. As a result, an accurate control voltage CV that does not include the above error is supplied to the voltage-controlled oscillator VCO via the low-pass filter LPF.

Therefore, in the steady state, the voltage controlled oscillator VCO
Can stably output an output signal VO that exactly matches the set frequency of 1,650,025 KHz.

[0083]

According to the first aspect of the present invention, a generating means for generating a plurality of reference signals, a plurality of variable frequency dividers for dividing the output signal of the voltage controlled oscillator and outputting each feedback signal, and A phase comparator for comparing the phase of the feedback signal with each of the reference signals is provided, and the voltage-controlled oscillator is configured not to reflect an error signal. In this way, a plurality of variable frequency dividers are provided,
In the second PLL frequency synthesizer having one variable frequency divider, the voltage controlled oscillator is configured not to reflect the error signal. As a result, in the first PLL frequency synthesizer having another variable frequency divider, an output signal that exactly matches the set frequency can be output by dividing the frequency by an accurate frequency.

According to the second aspect of the present invention, the error signal is reflected at the time of search, and the error signal is not reflected at the time of near steady state and at the time of steady state. In this way, even if the error signal is reflected at the time of the search, the output signal has not yet reached the set frequency, so that there is no practical problem. Then, since the error signal is not reflected at the time of near steady state and at the time of steady state, an output signal that exactly matches the set frequency can be output.

In the third aspect of the present invention, the variable frequency divider comprises a first variable frequency divider and a second variable frequency divider, and the first variable frequency divider has a frequency dividing number N (N is A value obtained by dividing a set frequency by a reference frequency) is set, and the second variable frequency divider is configured to set a frequency division number N / n (n is an integer of 3 or more). As described above, since the division number N / n is set for the second variable frequency divider, a plurality of second variable frequency dividers, that is, (n−n) are provided during one cycle of the first reference signal. 1) Output Hi level signals (feedback signals). The first variable frequency divider outputs one first feedback signal during one cycle. As a result, the phase comparator performs the phase comparison n times (n is an integer of 3 or more) during one cycle, and the lock-up time is shortened. Further, two variable frequency dividers may be used to perform the phase comparison n times in one cycle. As a result, the number of variable frequency dividers can be reduced, cost is reduced, and
It is easy to make an LSI.

According to a fourth aspect of the present invention, there is provided a generating section for generating a signal for determining a dead band width, and a phase comparator connected to the second variable frequency divider uses an error signal in a subsequent stage according to the signal. Is not transmitted. With this configuration, when the signal generated by the generation unit is located in the dead zone width G,
The error signal output from the phase comparator becomes a Lo level signal by the above signal. As a result, no error signal is transmitted to the subsequent stage (parts after the charge pump). Therefore, an output signal that exactly matches the set frequency can be output.

According to the fifth aspect of the present invention, the frequency division number N / n
Is composed of an integer part and a remainder part, the second variable frequency divider divides the frequency by the integer part, and the phase comparator does not transmit the error signal generated by the error according to the remainder part to the subsequent stage. Configuration. As described above, when the division number N / n is composed of an integer part and a remainder part, the second variable frequency divider divides the frequency by the integer part, so that it is not necessary to use the fraction variable frequency divider, and the cost is reduced. It becomes cheaper and operation becomes stable. Further, since the error signal generated by the error according to the remainder is not transmitted to the subsequent stage, an output signal that exactly matches the set frequency can be output.

According to a sixth aspect of the present invention, the signal is generated in accordance with a reference signal input to the phase comparator. Thus, a signal for determining the dead band width according to the reference signal input to the phase comparator is generated. as a result,
The mutual positional relationship between the feedback signal output by the variable frequency divider and the dead band width (that is, the timing of both) is accurately controlled. Therefore, when the phase difference between the reference signal and the feedback signal becomes equal to or smaller than a predetermined value, the error signal can be output at an accurate timing by setting the signal to Lo level.

[0089] According to the present invention of claim 7, the generation unit may be configured such that the rising point or the falling point of the reference signal is centered.
The signal is generated so as to distribute the dead band width, and the phase comparison signal of the phase comparator is ANDed with the signal. Since the dead band width is distributed around the rising time or falling time of the reference signal, when the phase difference between the reference signal and the feedback signal becomes equal to or less than a predetermined value, the signal is set to Lo level so that accurate timing can be obtained. , An error signal can be output.

According to the present invention of claim 8, the generating means includes:
A plurality of reference signals having different phases are generated, one of the reference signals is a first reference signal, and a first feedback signal output from the first variable frequency divider is compared with a phase of the first reference signal by a first signal. A configuration is provided in which a phase comparator is provided. In this manner, the first phase comparator compares the phase of one first reference signal with one first feedback signal divided by the division number N (integer), so that the first phase comparator has an accurate phase. You can compare. As a result, at steady state,
An output signal that exactly matches the set frequency can be output.

In the ninth aspect of the present invention, a sum of (n-1) reference signals excluding the first reference signal among the n reference signals is a second reference signal, A second phase comparator for comparing the phase of a second feedback signal output from the second variable frequency divider with the second reference signal is provided.
As described above, the second reference signal obtained by adding the (n-1) reference signals having different phases is input to the second phase comparator.
During one cycle of the first reference signal, (n-1) phase comparisons are performed at accurate timing. Also, like this (n-
1) Since the reference signals are added, the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit 1 according to an embodiment of the present invention.

FIG. 2 is a time chart of each signal used in the PLL circuit 1;

[Explanation of symbols]

 2 Generation means 4, 8 Variable frequency divider 13 Phase comparator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC03 CC15 CC20 CC24 CC30 CC38 CC53 DD20 DD32 DD43 KK03 PP03 QQ09 RR06 RR07 RR18

Claims (9)

[Claims] A generating means for generating a plurality of reference signals;
Dividing the output signal of the voltage-controlled oscillator, comprising a plurality of variable frequency dividers that output each feedback signal, and a phase comparator that compares the phase of each feedback signal and each reference signal, for the voltage-controlled oscillator, A PLL circuit characterized in that an error signal is not reflected. 2. The PLL circuit according to claim 1, wherein the error signal is reflected at the time of a search, and the error signal is not reflected at the time of near steady state or at the time of steady state. 3. The variable frequency divider includes a first variable frequency divider and a second variable frequency divider, and the first variable frequency divider has a frequency division number N (where N is a set frequency and a reference frequency. 2. The PL according to claim 1, wherein a division number N / n (n is an integer of 3 or more) is set in the second variable frequency divider.
L circuit. 4. A phase detector connected to the second variable frequency divider, wherein the phase comparator connected to the second variable frequency divider does not transmit an error signal to a subsequent stage according to the signal. 4. The PLL circuit according to claim 3, wherein 5. The frequency dividing number N / n includes an integer part and a remainder part, the second variable frequency divider divides the frequency by the integer part, and the phase comparator uses an error according to the remainder part. 5. The PLL circuit according to claim 4, wherein the generated error signal is not transmitted to the subsequent stage. 6. The PLL circuit according to claim 4, wherein said signal is generated according to a reference signal input to said phase comparator. 7. The generating section generates the signal such that the dead band width is distributed around a rising time or a falling time of the reference signal, and a phase comparison signal of the phase comparator and the signal are generated. 5. The PLL circuit according to claim 4, wherein AND operation is performed. 8. The generating means generates a plurality of reference signals having different phases, one of the reference signals being a first reference signal, and a first feedback signal output by the first variable frequency divider and the first feedback signal. 4. The PLL circuit according to claim 3, further comprising a first phase comparator for comparing a phase of the first reference signal. 9. A signal obtained by adding (n-1) reference signals excluding the first reference signal among the n reference signals is a second reference signal, and the second variable frequency division is performed. A second feedback signal output by the detector and a second signal comparing the phase of the second reference signal.
9. The PLL circuit according to claim 8, further comprising a phase comparator.