JP2001267920A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that is easily integrated as an LSI with a short lockup time, less power consumption, and high C/N. SOLUTION: The PLL circuit is provided with a variable frequency divider PD that divides a frequency of an output signal from a voltage controlled oscillator VCO with a frequency division rate of N+B/C (N, B, C are integers and B<=C) and provides an output of a feedback signal and with phase comparators PC1, PC2 that compare a phase of the reference signal with a phase of the feedback signal. The phase comparators PC1, PC2 conduct normal phase comparison once per C times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, this type of circuit is, for example, "SANY".
O TECHNICAL REVIEW ”, VOL. 1
0, NO. 1, FEB. It is shown on page 32 of 1978. However, this circuit is a one-stage phase comparator (using only one position comparator) and performs only one phase comparison during one cycle of the reference signal, so that the lock-up time (output The first disadvantage is that the time until the signal is synchronized is short.

[0003] In order to solve this drawback, Japanese Patent Laid-Open No.
No. 135822 has been proposed. According to this publication, generating means for generating a plurality of reference signals having different phases, a plurality of (for example, four) variable frequency dividers for dividing an output signal of a voltage controlled oscillator, and a feedback signal of each frequency divider And a plurality of phase comparators for comparing each of the reference signals.

[0004]

However, the circuit disclosed in the above publication has a second drawback in that the power consumption is large. The inventor of the present invention has investigated the cause and found that the reason is that a plurality of variable frequency dividers are provided. Further, if the phase comparison is performed four times during one cycle of the reference signal in order to further reduce the lock-up time, four frequency dividers are required, and the power consumption is further increased.

In addition, since a plurality of variable frequency dividers requiring a relatively large space are used, there is a third disadvantage that the size of the apparatus is increased, the cost is increased, and it is difficult to implement an LSI. Furthermore, in the above circuit, since the phase comparison is not performed accurately, the C / N ratio (carrier to noise)
There is a fourth disadvantage of low ratio. Therefore, the present invention provides a PLL circuit having a short lock-up time, low power consumption, easy LSI, and a high C / N ratio in consideration of such conventional disadvantages.

[0006]

In order to solve the above problem, according to the present invention, a generating means for generating a reference signal, a frequency dividing ratio N + B / C (N, B and C are integers, and B ≦
(C) a variable frequency divider for dividing the output signal of the voltage controlled oscillator and outputting a feedback signal; and a phase comparator for comparing the phase of the reference signal and the feedback signal. At the time, a normal phase comparison is performed.

According to the second aspect of the present invention, a generating means for generating a plurality of reference signals having different phases, and a frequency dividing ratio N + B / C
(N, B and C are integers, and B ≦ C) a variable frequency divider for dividing the output signal of the voltage controlled oscillator and outputting a plurality of feedback signals, each of the reference signals and each of the feedback signals And a phase comparator that outputs a plurality of phase comparison signals, and performs a normal phase comparison once every C times.

According to the present invention, at the start,
All of the phase comparison signals are output, and just before or after locking, only the phase comparison signal for which the normal phase comparison has been performed is output.

According to the present invention, the frequency of the reference signal is the same as a value obtained by multiplying the inter-station frequency by the C.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit 1 according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the PLL circuit 1, and FIG. 2 is a block diagram of a variable frequency divider and the like used in the PLL circuit 1.

In these figures, the generating means 2 is, for example,
A reference oscillator OSC, a fixed frequency divider M, a delay circuit D1,
D2, D3, D4, etc. The fixed frequency divider M divides the frequency by a frequency division ratio of 20, for example, and is connected between the reference oscillator OSC and the delay circuit D1. Fixed frequency divider M
Outputs a reference signal FR1 (frequency: 5 KHZ) obtained by dividing a signal (oscillation frequency: 100 KHZ) output from the reference oscillator OSC by 20 to the phase comparator PC1.

The delay circuit D1 is １ ／ of the reference signal FR1.
The reference signal FR1 is delayed by the period, and the reference signal FR2 is delayed.
Is output to the OR gate 3. The delay circuit D2 delays the reference signal FR1 by 2/5 cycle of the reference signal FR1 and outputs the result to the OR gate 3 as the reference signal FR3.

The delay circuit D3 is ３ of the reference signal FR1.
The reference signal FR1 is delayed by the period and the reference signal FR4
Is output to the OR gate 3. The delay circuit D4 delays the reference signal FR1 by 4/5 period of the reference signal FR1 and outputs the result to the OR gate 3 as the reference signal FR5.
As described above, the generating means 2 generates a plurality of reference signals FR1 to FR5 having different phases and outputs the signals to the OR gate 3.

The variable frequency divider PD has a frequency dividing ratio N + B / C (N
, B and C are integers, and B ≦ C).
The output signal VO of O is divided to output an intermediate signal A.

As shown in FIG. 2, the variable frequency divider PD has N ′
N 'frequency dividing circuit 4 for dividing by (integer), and N' + 1/2
(N ′ is an integer) and an N ′ + ／ divider circuit 5 for dividing the frequency. The N 'frequency dividing circuit 4 and the N' + 1/2 frequency dividing circuit 5 are separated for explanation of the operation. However, the actual configuration is based on the N '+ 1/2 frequency dividing circuit 5, and based on a control signal from the control circuit 6 described later, an integrated logic circuit is added to add a logic circuit so as to perform N' frequency dividing. Configuration.

The control circuit 6 has an accumulator 7 for storing the data of addition, and controls the variable frequency divider PD based on an external designation (input) of the frequency division ratio N + B / C. R
The OM 8 contains a control program for causing the control circuit 6 to operate. The RAM 9 stores data (N, B, C, etc.) necessary for the operation of the control circuit 6.

The counter COU is basically the same as the counter 44a disclosed in Japanese Patent Application No. 11-201752 by the present applicant, and a detailed description thereof will be omitted. In brief, the counter COU has an input terminal connected to a plurality of toggle flip-flops. Each output side of the toggle flip-flop is connected to, for example, a signal Q1, Q2Q.
3 is output.

For example, the signal Q1 is a signal obtained by dividing the intermediate signal A by two, the signal Q2 is a signal obtained by dividing the intermediate signal A by four, and the signal Q3 is a signal obtained by dividing the intermediate signal A by eight. In this way, the counter COU outputs, for example, the signal Q
1, Q2 and Q3 are output to the decoder DEC.

The input side of the decoder DEC is connected to the output side of the counter COU. The decoder DEC is
For example, the basic configuration is the same as that of the distribution circuit 32 shown in Japanese Patent Application No. 11-201752 by the present applicant, and a detailed description is omitted.

In brief, the decoder DEC includes three conductive lines, five AND gates, and the like. The three conductive lines are connected to signals Q1, Q2, Q3, respectively. Each of the three conductive lines is connected to a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal provided on each AND gate.

The first to fourth input terminals of each AND gate are provided with an input inverting function as appropriate. The output sides of the AND gates are respectively provided with feedback signals FP1 to FP5.
Is output.

Each of the feedback signals FP2 to FP5 is input to the OR gate 10. The OR gate 10 includes a variable frequency divider P
From among the plurality of feedback signals FP2 to FP5 generated by D, the counter COU, and the decoder DEC, one feedback signal is sequentially output to another input side of the phase comparator PC2. The distribution circuit 11 is composed of the counter COU, the decoder DEC and the like.

To one input side of the phase comparator PC2, one of the reference signals FR2 to FR5 is sequentially input from the plurality of reference signals generated by the generation means 2. Also,
One of the feedback signals FP2 to FP5 is sequentially input to the other input side of the phase comparator PC2 from among the plurality of feedback signals generated by the OR gate 10.

The phase comparator PC2 detects each of the reference signals FR2 to FR2.
5 and each of the feedback signals FP2 to FP5, outputs a plurality of phase comparison signals U2 to U5 to the charge pump CP2, and outputs a plurality of phase comparison signals D2 to D5 to the charge pump CP2. The charge pump CP2 outputs error signals ER2, ER3, ER4, ER5 according to the plurality of phase comparison signals U2, D2 to U5, D5.

The feedback signal FP1 is supplied to the phase comparator PC
1 is input to the other input side. In this manner, the phase comparator PC1 outputs the reference signal FR1 and the feedback signal FP
1 and outputs phase comparison signals U1 and D1 to the charge pump CP1.

The charge pump CP1 outputs an error signal ER1 to the low-pass filter LPF according to the phase comparison signals U1 and D1.

The low-pass filter LPF generates a control voltage CV in which harmonic components of the error signals ER1, ER2, ER3, ER4, and ER5 are cut, and a voltage-controlled oscillator V
Output to CO.

The voltage controlled oscillator VCO outputs an output signal VO having a frequency according to the control voltage CV. The output signal VO is output to the variable frequency divider PD and to an external device (not shown) via the output terminal 12.

Hereinafter, features of the PLL circuit 1 will be described. In the PLL circuit 1, a generating means 2 for generating a plurality of reference signals FR1 to FR5 having different phases is provided. Division ratio N + B / C (N, B and C are integers, and B ≦
In C), the output signal of the voltage controlled oscillator VCO is divided,
Via the distribution circuit 11 and the like, a plurality of feedback signals FP1 to FP
5 is provided.

Each of the reference signals FR1 to FR5 and each of the feedback signals FP1 to FP5 are compared with each other in phase, and a plurality of phase comparators U1, D1 to U5, and phase comparators PC1,
A PC 2 is provided.

Next, according to FIG. 1 to FIG.
The operation of the circuit 1 will be described. FIG. 3 shows a time chart of each signal used in the PLL circuit 1.

In these figures, first, for example, when the user presses a frequency key (not shown) set to 1001 KHZ.
Is set, and the start key is pressed. At this time, for example, 1001 KHZ, 1002 KHZ, 100
It is assumed that the frequency can be set for each 1 KHZ, such as 3 KHZ. That is, inter-station frequency (channel space)
Is 1 KHZ.

At this time, the control circuit 6 sets the set frequency 1
In response to the input of 001KHZ, the set frequency division ratio N + B / C = 200 + ／ of the variable frequency divider PD is calculated. That is,
Find N = 200, B = 1, C = 5. As described above, the frequency 5KHZ of the reference signals FR1 to FR5 is the inter-station frequency 1
It is the same as the value obtained by multiplying KHZ by C = 5. That is, the set frequency division ratio is equal to the set frequency 1001 KHZ of the output signal VO.
Is divided by the frequency 5 KHZ of the reference signals FR1 to FR5 (200 + ／).

The generating means 2 has a frequency of 5 KHZ.
Five reference signals FR, each having a different phase by 1/5 cycle
1 to FR5 are output.

At this time, the control circuit 6 applies the N 'frequency dividing circuit 4 for the first time, the N' frequency dividing circuit 4 for the second time, and the N '+ 1/2 frequency dividing for the third time for the variable frequency divider PD. Circuit 5 and 4
In the fifth circuit, the N ′ + ／ frequency dividing circuits 5 are respectively output (see FIG. 3).

In FIG. 3, 1/5, 2/5, 1/10, and 3/10 are errors between the reference signal FR1 and the feedback signal FP1 in the first to fourth times, respectively. With the above configuration, the output timing of the feedback signal FP1 is one for every five times.
It can be seen that the time coincides with the output timing of the reference signal FR1.

In the above description, the frequency division of 200 + ／ was described.
By appropriately selecting the number of outputs of the divide-by-2 circuit 5, 20
0 + 2/5, 200 + 3/5, 200 + 4/5, 200
In each frequency division of +5/5, it can be seen that the output timings coincide once every five times.

Similarly, when performing N + B / C frequency division,
The number of outputs of the N ′ frequency dividing circuit 4 and the N ′ + ／ frequency dividing circuit 5
, The output timing of the feedback signal FP1 matches the output timing of the reference signal FR1 once every C times. That is, a regular phase comparison is performed once every C times the feedback signal FP1 is output.

As described above, the variable frequency divider PD divides the output signal VO of the voltage controlled oscillator VCO by 200 + 1/5 and divides the divided intermediate signal A through the distribution circuit 11 into the feedback signal. Output to the phase comparator PC1 as FP1.

The intermediate signals A are output one by one to the phase comparator PC2 as feedback signals FP2 to FP5 via the distribution circuit 11 and the OR gate 10.

The phase comparators PC1 and PC2 receive the reference signal FR
1 to FR5 and the feedback signals FP1 to FP5,
A plurality of (all) phase comparison signals U1, D1 to U5, D5
To the charge pumps CP1 and CP2.

The charge pumps CP1 and CP2 output error signals ER1 to ER5 to the low-pass filter LPF according to the phase comparison signal. Low-pass filter LP
F outputs a control voltage CV to the voltage controlled oscillator VCO according to the error signal. As a result, the output signal VO output from the voltage controlled oscillator VCO becomes the reference signal FR.
It approaches the phase and frequency of 1 to FR5. Such a phase comparison operation is repeated.

As described above, since all the phase comparison signals are output at the start, the phase comparison is performed five times during one cycle of the reference signal FR1.
The lock-up time is reduced to about 1/5 as compared with the step type.

When the above phase comparison is repeated, the output signal V
O is immediately before the lock. That is, the first detector (not shown) for detecting the phase comparison signal of the phase comparator PC1 and / or the second detector (not shown) for detecting the phase comparison signal of the phase comparator PC2 has a detection signal of When it is detected that the lock signal has reached 80 to 95% of the lock signal (when the frequency of the output signal VO has almost reached the set frequency) (this is called "immediately before lock"), a signal to that effect is output to the control circuit 6. I do.

The control circuit 6 stops the operation of the phase comparator PC2 in response to the input of the signal. At the same time, the control circuit 6 continuously operates the variable frequency divider PD and the phase comparator PC1. That is, just before locking, only the phase comparison signals U1 and D1 (output from the phase comparator PC1) for performing the normal phase comparison are output.

By repeating the operation in the above loop, the PLL circuit 1 stably outputs the output signal VO having the set frequency 1001 KHZ to the output terminal 12 connected to the voltage controlled oscillator VCO, and locks. State is reached and synchronization is achieved.

Unlike the above description, at the start, all the phase comparison signals are output, and after locking (after the output signal VO substantially reaches the set frequency), the phase comparison signal for which the normal phase comparison has been performed is performed. Only the signals U1 and D1 may be output.

Also, unlike the above description, if necessary,
Instead of performing a plurality of phase comparisons, a single phase comparison may be performed. That is, in FIG. 1, the intermediate signal A output from the variable frequency divider PD is output to the phase comparator PC1 as the feedback signal FP1. Then, delay circuits D1 to D4, OR gate 3, phase comparator PC2, charge pump CP2
, The OR gate 10, the distribution circuit 11, and the like.

In the above case, the configuration is as follows. A generator 2 for generating the reference signal FR1 is provided. Division ratio N
+ B / C (where N, B and C are integers and D ≦ C), divides the output signal VO of the voltage controlled oscillator VCO and returns the feedback signal F
A variable frequency divider PD for outputting P1 is provided. Reference signal FR
1 and a phase comparator PC1 for comparing the phase of the feedback signal FP1. Once every C times, normal phase comparison is performed.

[0050]

According to the first aspect of the present invention, the output of the voltage controlled oscillator is generated by the generation means for generating the reference signal and the dividing ratio N + B / C (N, B and C are integers and B ≦ C). A variable frequency divider that divides a signal and outputs a feedback signal; and a phase comparator that compares the phase of the feedback signal with the reference signal, and performs a normal phase comparison once every C times. I do.
In this way, fractional frequency division is possible, so that a relatively high reference frequency can be used even in a case where a relatively small inter-station frequency is required, and the lock-up time is shortened. Further, in the fractional frequency division type PLL circuit, the normal phase comparison is performed once every C times, so that the phase comparison can be performed accurately and the C / N
The ratio increases.

According to the second aspect of the present invention, a generating means for generating a plurality of reference signals having different phases, and a dividing ratio N + B / C
(N, B, and C are integers and B ≦ C) a variable frequency divider that divides the output signal of the voltage controlled oscillator and outputs a plurality of feedback signals, each of the reference signal and each of the feedback signals And a phase comparator that outputs a plurality of phase comparison signals, and performs a normal phase comparison once every C times. Since a plurality of phase comparison signals are output in this manner, the phase comparison is performed a plurality of times during one cycle of the reference signal, and the lock-up time is shortened. In addition, a single variable frequency divider is required for comparing a plurality of phases, so that the cost is low, it is easy to implement an LSI, and the power consumption is small. Furthermore, in the fractional frequency division type PLL circuit, the normal phase comparison is performed once every C times, so that the phase comparison can be performed accurately and the C / N
The ratio increases.

According to the third aspect of the present invention, at the start,
All the phase comparison signals are output, and immediately before or after locking, only the phase comparison signal for which the normal phase comparison has been performed is output. As described above, since all the phase comparison signals are output at the start, the lock-up time is shortened. Also, just before or after locking,
Since only the phase comparison signal subjected to the normal phase comparison is output, a plurality of phase comparison signals are prevented from interfering with each other, accurate phase comparison can be performed, and the C / N ratio increases.

According to a fourth aspect of the present invention, the frequency of the reference signal is the same as a value obtained by multiplying the inter-station frequency by the C. As described above, a relatively large reference frequency (a value obtained by multiplying the inter-station frequency by C) can be used even when a relatively low inter-station frequency is required in the fractional frequency division PLL circuit. Since a large number of phase comparisons can be made within a unit time, the lock-up time is shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit 1 according to an embodiment of the present invention.

FIG. 2 shows a variable frequency divider PD used in the PLL circuit 1.
FIG.

FIG. 3 is a time chart of each signal used in the PLL circuit 1;

[Explanation of symbols]

 1 PLL circuit 2 generating means

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC24 CC30 CC38 CC41 CC53 CC58 DD32 DD43 EE08 GG04 HH08 KK03 KK24 KK37 KK40

Claims (4)

[Claims] 1. A reference signal generating means for generating a reference signal; dividing the output signal of the voltage controlled oscillator by a dividing ratio N + B / C (N, B and C are integers and B ≦ C); And a phase comparator for comparing the phase of the reference signal and the feedback signal, and performs a normal phase comparison once every C times. 2. A generator for generating a plurality of reference signals having different phases, and dividing the output signal of the voltage controlled oscillator by a dividing ratio N + B / C (N, B and C are integers and B ≦ C). Go around
A variable frequency divider that outputs a plurality of feedback signals; and a phase comparator that compares the phases of the reference signals and the feedback signals and outputs a plurality of phase comparison signals.
The PLL circuit performs a regular phase comparison. 3. The method according to claim 2, wherein all the phase comparison signals are output at the start, and only the phase comparison signal for which the normal phase comparison has been performed is output immediately before or after locking. PLL circuit. 4. The frequency of the reference signal is equal to a value obtained by multiplying the inter-station frequency by the C.
Or the PLL circuit according to claim 2.