JP2001257585A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit where lock-up time is short and an arbitrary inter-station frequency can be obtained. SOLUTION: The PLL circuit is provided with a generation means 2 having a reference oscillator 3 and generating plural reference signals different in phases, a variable frequency dividing means 13 which frequency-divides the output signal of a voltage control oscillator 6 and outputs plural feedback signals and phase comparators A1 to A13 which phase-compare the plural reference signals with the plural feedback signals. The number of reference signals is set so that it becomes equal to a quotient obtained by dividing the oscillation frequency of the reference oscillator 3 by an actual frequency by the plural reference signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus is, for example, "SANY
O TECHNICAL REVIEW ”, VOL. 1
0, NO. 1, FEB. It is shown on page 32 of 1978. However, this device is a one-stage phase comparator (using only one stage comparator), and performs only one phase comparison during one cycle of the reference signal. The first disadvantage is that the time until the signal is synchronized is short.

[0003] In order to solve this drawback, Japanese Patent Laid-Open No.
No. 135822 has been proposed. According to this publication, generating means for generating a plurality of reference signals having different phases from each other, a plurality of frequency dividers for dividing the output signal of the voltage controlled oscillator, and comparing a feedback signal of each frequency divider with each reference signal. Are provided.

[0004]

However, in the above device,
There is a second disadvantage that a desired inter-station frequency cannot be obtained. This is because, for example, using a reference oscillator having an oscillation frequency of 13 MHz and a fixed frequency divider having a frequency division ratio of 5, an inter-station frequency of 200K
If HZ is desired, the number of phase comparators is selected from a power of two. In the above case, 16 phase comparators are selected. As a result, the inter-station frequency (real frequency based on a plurality of reference signals) is 13000 KHZ ÷ 5 ÷ 16 = 1.
62.5 KHZ, which is not desired.

Accordingly, the present invention provides a PLL circuit which has a short lock-up time and can obtain an arbitrary inter-station frequency in consideration of such a conventional disadvantage.

[0006]

In order to solve the above problems, according to the present invention, there is provided a generator having a reference oscillator for generating a plurality of reference signals having different phases, and an output of a voltage controlled oscillator. Variable frequency dividing means for dividing a signal and outputting a plurality of feedback signals, each comprising a plurality of the reference signals and a plurality of the feedback signals, and a phase comparator for comparing phases, wherein an oscillation frequency of the reference oscillator is , The number of the reference signals is set to be equal to a quotient of an integer divided by a substantial frequency of the plurality of reference signals.

According to the present invention, a fixed frequency divider is provided between the reference oscillator and the phase comparator, and the quotient is equal to an integer value obtained by dividing the quotient by the dividing ratio of the fixed frequency divider. Thus, the number of the reference signals is set.

According to the present invention, the number of the phase comparators is set to be equal to the quotient or the value.

According to a fourth aspect of the present invention, one reference signal is selected from the plurality of reference signals, and one feedback signal is selected from the plurality of feedback signals. By comparing the phases of the two signals, a single phase comparator is formed.

[0010]

FIG. 1 is a block diagram showing a PLL circuit according to a first embodiment of the present invention. In FIG. 1, the generating means 2 is, for example, a reference oscillator 3
, And twelve delay circuits D1, D2,...
D12 and the like. The fixed frequency divider 4 divides the frequency by a frequency division ratio of 5, for example, and is connected between the reference oscillator 3 and the delay circuit D1.

The reference signal FR1 output from the fixed frequency divider 4
Has a reference frequency of 13 MHZ ÷ 5 = 2.6 MHZ, and is input to one input side of the phase comparator A1.

The delay circuit D1 is only 1/13 (1/13) of one cycle of the reference signal FR1 (about 3.85 × 10−7 seconds).
Period), the reference signal FR1 is delayed, and
This is given to the phase comparator A2 as R2.

The delay circuit D2 converts the reference signal FR1 to 2/1.
The signal is delayed by three periods, and is supplied to the phase comparator A3 as the reference signal FR3.

Similarly, a delay circuit Dn (n is 3 to 1
(Integer up to 2) delays the reference signal FR1 by n / 13 periods, and supplies it to the phase comparator A (n + 1) as the reference signal FR (n + 1).

As described above, the generating means 2 has the reference oscillator 3 and generates a plurality of reference signals FR1 to FR13 having different phases. Each of the reference signals FR1 to FR13 is 2.96.
It rises at timings T1 to T13 shifted every × 10−8 seconds.

The feedback signals FP1, FP2, FP3,..., F
P13 (described later) are phase comparators A1, A2, and A, respectively.
3,..., Are input to the other side of A13.

The phase comparator A1 compares the phase of the feedback signal FP1 with the phase of the reference signal FR1, and as a result of the comparison, outputs a phase comparison signal (pump-up signal pump-down signal) to the charge pump B1. Charge pump B
1 outputs an error signal ER1 to the low-pass filter 5 according to the phase comparison signal.

Similarly, the phase comparator An (n is 2 to 13)
) Are the phase of the feedback signal FPn and the reference signal F
Compare the phases of Rn. As a result of the comparison, the phase comparator A
n outputs a phase comparison signal to the charge pump Bn. The charge pump Bn outputs an error signal ERn to the low-pass filter 5 according to the phase comparison signal.

As described above, the phase comparator An (n is 1 to 1)
(An integer up to 3) compares the phases of the plurality of reference signals FRn and the plurality of feedback signals FPn.

[0020] The low-pass filter 5 is provided for each error signal ER1.
ER13, the control voltage CV is output to the voltage controlled oscillator 6. The voltage controlled oscillator 6 controls the control voltage C
In response to V, output signal VO is output via output terminal 7.

The variable frequency divider 8 has its input side connected to the output side of the voltage controlled oscillator 6 and its output side connected to the phase comparator A.
1 is connected to the input side. The control unit (comprising a microcomputer or the like, not shown) sets the set frequency division ratio N to the variable frequency divider 8.

With this configuration, the variable frequency divider 8 divides the output signal VO output from the voltage controlled oscillator 6 by the set frequency division ratio N, and outputs the output (feedback signal FP1) to the phase comparator A.
Output to 1. Thus, the variable frequency divider 8 has at least one
And outputs the feedback signal FP1 to at least one phase comparator (the phase comparator A1 in the above example).

The distribution means 9 includes, for example, a programmable frequency divider 10, a counter 11, a decoder 12, and the like. The programmable frequency divider 10 has its input side connected to the output side of the voltage controlled oscillator 6 and its output side connected to the input side of the counter 11. The control section sets the set frequency division ratio N / 13 for the programmable frequency divider 10.

With this configuration, the programmable frequency divider 1
0 indicates that the output signal VO output from the voltage controlled oscillator 6 is divided by the set dividing ratio N / 13, and the output (intermediate signal) A
Is output to the counter 11.

The counter 11 is, for example, a 4-bit counter 4 disclosed in Japanese Patent Application No. 11-201752 filed by the present applicant.
4a, and the detailed description is omitted. In brief, the counter 11 has an input terminal connected to a plurality of toggle flip-flops. Each output side of the toggle flip-flop is, for example, a signal Q1, Q2, Q
3. Output Q4.

For example, the signal Q1 is a signal obtained by dividing the intermediate signal A by two, the signal Q2 is a signal obtained by dividing the intermediate signal A by four, the signal Q3 is a signal obtained by dividing the intermediate signal A by eight, The signal Q4 is a signal obtained by dividing the frequency of the intermediate signal A by 16.
As described above, the counter 11 outputs, for example, the signals Q1, Q2, Q
3, and outputs Q4 to the decoder 12.

The input side of the decoder 12 is the counter 1
1 is connected to the output side. The decoder 12 has the same basic configuration as, for example, the distribution circuit 32 shown in Japanese Patent Application No. 11-201752 by the present applicant, and a detailed description thereof will be omitted.

In brief, the decoder 12 includes four conductive lines, thirteen AND gates, and the like. The four conductive lines are connected to signals Q1, Q2, Q3, Q4, respectively. The four conductive lines are respectively connected to a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal provided on each AND gate.

The first to fourth input terminals of each AND gate are provided with an appropriate input inversion function. And
The output sides of the AND gates are respectively feedback signals FP2 to FP
13 is output.

As described above, the distribution means 9 distributes the output of the variable frequency divider 8. Each of the phase comparators A1 to A13 includes a feedback signal FV1 output from the variable frequency divider 8 and the distribution unit 9.
FV13 and the respective reference signals FR1 to FR13, and outputs a plurality of phase comparison signals. As described above, the variable frequency divider 13 includes the variable frequency divider 8 and the distributor 9. The variable frequency dividing means 13 divides the frequency of the output signal VO of the voltage controlled oscillator 6 and generates a plurality of feedback signals FP1 having different phases.
To FP13.

The detector C1 comprises, for example, an AND gate and a resistor. The detector C1 takes the AND of the pump-up signal and the pump-down signal of the phase comparator A1, and outputs the ANDed detection signal to the control unit. . Similarly, the detectors C2 to C13 are connected to the phase comparators A2 to A13. The above components constitute the present PLL device 1.

Next, the operation of the present PLL circuit 1 will be described with reference to FIG. First, for example, as a set frequency, 2.08
It is assumed that GHZ is input to the control unit via input means (not shown). The control unit sets N = 2080 × 103 KHZ / 200 KHZ = 10 as the set frequency division ratio of the variable frequency divider 8.
400 (because the real frequency of the reference signal is 200 KHZ)
Is calculated and set. Then, the control unit calculates and sets the set frequency division ratio N / 13 = 800 for the programmable frequency divider 10. The variable frequency divider 8 has a set frequency division ratio of 1040
At 0, the output signal VO is frequency-divided and a feedback signal FP1 is output to the phase comparator A1.

The programmable frequency divider 10 divides the output signal VO at a set frequency division ratio of 800 and outputs an intermediate signal A. The counter 11 receives the signal Q from the input of the intermediate signal A.
1, Q2, Q3, and Q4 are output. The decoder 12 receives the signals Q1, Q2, Q3, and Q4 and receives the signals from the phase comparator A2.
ＡA13 to output feedback signals FP2 to FP13.
At this time, as described above, each of the feedback signals FP2 to FP13 has a waveform delayed by 1/13 cycle,..., 12/13 cycle of the feedback signal FP1.

That is, the rises of the feedback signals FP1 to FP13 coincide with the rise timings T1 to T13 of the reference signals FR1 to FR13, respectively.

As described above, the phase comparators A1 to A13 output the feedback signal FP1 at the timings T1 to T13, respectively.
FP13 are compared with the respective phases of reference signals FR1 to FR13.

That is, at the time of start, the variable frequency divider 8, the distribution means 9 and the phase comparators A1 to A13 are operated, and
The phases are compared in three stages.

According to this configuration, the phase comparison is performed 13 times during one cycle of the reference signal FR1, so that the lock-up time (the output signal VO) is shorter than that of the conventional one-stage phase comparator.
(The time it takes to substantially reach the set frequency) is reduced to about 1/13 times.

Thus, when the above phase comparison is repeated,
The output signal VO is immediately before the lock (the state immediately before the frequency of the output signal VO reaches the set frequency). Like this
The detectors C1 to C13 detect that the detection signal is 80% of the lock signal (when the frequency of the output signal VO substantially reaches the set frequency).
When it is detected that it has reached 〜95% (this is called “immediately before locking”), a signal to that effect is output to the control unit.

The control section stops the operation of the distribution means 9 and the phase comparators A2 to A13 in response to the input of the signal. At the same time, the control unit continuously operates the variable frequency divider 8 and the phase comparator A1.

Thus, the phase comparator A1 compares the phase of the feedback signal FP1 from the variable frequency divider 8 with the phase of the reference signal FR1, and outputs a phase comparison signal to the charge pump B1. The charge pump B1 is connected to the low-pass filter 5,
An error signal ER1 is output. The low-pass filter 5 outputs a control voltage CV to the voltage controlled oscillator 6.

By repeating the operation in the above loop, the PLL device 1 outputs the output signal VO having the set frequency 2.08 GHZ to the output terminal 7 of the voltage controlled oscillator 6.
Is output stably, the lock state is reached, and synchronization is achieved.

Next, the features of the PLL circuit 1 will be summarized below. The reference oscillator 3 outputs, for example, an oscillation frequency of 13 MHz. The fixed frequency divider 4 having a frequency division ratio of 5 divides the oscillation frequency by 5, and outputs a 2.6 MHZ signal.

If an inter-station frequency of 200 KHZ is required, the actual frequency of the reference signals FR1 to FR13 is also 200KHZ. At this time, the reference signals FR1 to FR
13, the oscillation frequency of the reference oscillator 3 is 13 MHZ.
Is divided by the real frequency 200 KHZ, that is, the integer quotient, that is, 65 is divided by the division ratio 5 of the fixed frequency divider 4 so as to be equal to 13 (ie, 13). .

As described above, the reference signals FR1 to FR13 are set to 1
By setting the number to three, a desired inter-station frequency (that is, a substantial frequency) of 200 KHZ can be obtained. At this time, the number of the phase comparators A1 to A13 is set to 13 so as to be equal to the integer value.

Further, unlike the above example, a configuration in which the fixed frequency divider 4 is omitted may be employed. At this time, the number of the reference signals FR is determined by calculating the oscillation frequency 13 MHZ of the reference
It is set to be equal to the integer quotient divided by 0KHZ (ie, 65). At this time, the number of the phase comparators A is
The number is set to 13 so as to be equal to the above quotient.

Next, the PLL circuit 14 according to the second embodiment of the present invention will be described with reference to the block diagram of FIG. In FIG. 2, those having the same numbers as those in FIG. 1 indicate the same parts.

The generating means 2 comprises a reference oscillator 3, delay circuits D1 to D12 and the like, and outputs a plurality of reference signals FR1 to FR13 having different phases to the first selecting means 15 (for example, comprising an OR gate).

The variable frequency dividing means 16 comprises, for example, a programmable frequency divider 10, a counter 11, and a decoder 12. The variable frequency dividing means 16 outputs the output signal VO of the voltage controlled oscillator 6 in the same manner as the distribution means 9 described above.
A plurality of feedback signals FP <b> 1 to FP <b> 13 divided by a frequency division ratio N / 13 and having different phases are output to the second selecting unit 17 (for example, composed of an OR gate).

One input side of the phase comparator A 1 is connected to the output side of the first selection means 15, and the other input side of the phase comparator A 1 is connected to the output side of the second selection means 17. The detector C1 receives the phase comparison signal of the phase comparator A1, and
This is to detect the lock state.

The charge pump B 1 receives the phase comparison signals PU and PD of the phase comparator A 1 and receives the low-pass filter 5.
, An error signal ER is output. The low-pass filter 5 outputs a control voltage CV corresponding to the input error signal ER to the voltage-controlled oscillator 6. With the above parts,
The PLL circuit 14 is configured.

Next, the operation of the present PLL circuit 14 will be described with reference to FIG. First, for example, as a set frequency,
It is assumed that 08GHZ is input to the control unit via the input unit. The control unit sets the dividing ratio of the variable dividing unit 16 as:
N / 13 = 2080 × 103 ÷ 200 ÷ 13 = 800 is calculated and set.

The variable frequency dividing means 16 frequency-divides the output signal VO from the voltage controlled oscillator 6 at a frequency dividing ratio of 800, and supplies a plurality of feedback signals FP1 to FP1 having different phases to the second selecting means 17.
FP13 is output at each rising timing T1 to T13.

The second selection means 17 includes a plurality of feedback signals FP
Feedback signals FP1, FP one by one from 1 to FP13
, FP13 are selected and output to the other input side of the phase comparator A1.

The reference oscillator 3 outputs an oscillation frequency of, for example, 13 MHZ, and outputs a reference signal FR output from the fixed frequency divider 4.
1 has a reference frequency of 13 MHZ ÷ 5 = 2.6 MHZ, and is input to the first selecting means 15. Similarly, the generation means 2 sends a plurality of reference signals FR1 to FR13 having different phases to the first selection means 15 at each rising timing T.
Output at 1 to T13.

The first selecting means 15 includes a plurality of reference signals FR.
Reference signals FR1 and FR one by one from 1 to FR13
, FR13 are selected and output to one input side of the phase comparator A1.

The phase comparator A1 operates at timings T1 to T13.
, The selected feedback signals FP1, FP2,.
P13 and the selected reference signals FR1, FR2,
, FR13 are compared in phase with each other, and the phase comparison signals PU and PD are output to the charge pump B1. Thus, by providing the first selecting means 15 and the second selecting means 17, the single phase comparator A1 can be constituted.

In response to the phase comparison signals PU and PD,
The charge pump B1 outputs an error signal ER to the low-pass filter 5. The low-pass filter 5 supplies the voltage-controlled oscillator 6 with a control voltage CV responsive to the error signal ER.
Is output. Voltage controlled oscillator 6 outputs output signal VO via output terminal 7 in response to control voltage CV.

By repeating the operation in the loop, the PLL circuit 14 stably outputs the output signal VO having the set frequency of 2.08 GHZ to the output terminal 7, reaches the locked state, and Can be taken.

[0059]

According to the first aspect of the present invention, a generator having a reference oscillator for generating a plurality of reference signals having different phases, an output signal of the voltage controlled oscillator is divided, and a plurality of feedback signals are output. Variable frequency dividing means, and a plurality of the reference signals and a plurality of the feedback signals, each comprising a phase comparator for comparing the phase, the oscillation frequency of the reference oscillator is divided by the substantial frequency of the plurality of reference signals. The number of the reference signals is set so as to be equal to an integer quotient. With this configuration, by selecting the number of reference signals, a desired inter-station frequency (substantial frequency based on a plurality of reference signals) can be set.
You can get it. Further, since the phase comparison is performed a plurality of times during one cycle of the reference signal, the lock-up time is shortened.

According to a second aspect of the present invention, a fixed frequency divider is provided between the reference oscillator and the phase comparator, and the quotient is equal to an integer value obtained by dividing the quotient by the dividing ratio of the fixed frequency divider. In this manner, the number of reference signals is set. Thus, by providing the fixed frequency divider, the number of reference signals can be reduced while obtaining a desired inter-station frequency. As a result, the number of delay circuits and the number of phase comparators can be reduced, and the configuration is simplified and the cost is reduced.

According to a third aspect of the present invention, the number of the phase comparators is set to be equal to the quotient or the value. With this configuration, the number of phase comparators is equal to the number of reference signals, and each phase comparator can perform accurate phase comparison.

According to the fourth aspect of the present invention, one reference signal is selected from the plurality of reference signals, and one feedback signal is selected from the plurality of feedback signals. By comparing the phases of the two signals, a single phase comparator is formed. With this configuration, the phase comparison can be realized for each reference signal having a different phase using a single phase comparator, and the cost is reduced. Further, since the number of phase comparators is one, a small LSI can be obtained when this PLL circuit is formed into an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit 1 according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a PLL circuit 14 according to a second embodiment of the present invention.

[Explanation of symbols]

 2 generating means A1 to A13 phase comparator 6 voltage controlled oscillator 13 variable frequency dividing means

Continued on the front page F term (reference) 5J106 AA04 CC01 CC30 CC38 CC41 CC52 CC53 CC58 DD09 DD17 DD32 DD34 DD46 DD48 FF01 KK03 KK39 PP03 QQ09 RR13 RR20

Claims (4)

[Claims] A generating means for generating a plurality of reference signals having different phases, a frequency dividing means for dividing an output signal of the voltage controlled oscillator and outputting a plurality of feedback signals; Each of the reference signal and the plurality of feedback signals,
A phase comparator for comparing the phases, wherein the number of the reference signals is set so that the oscillation frequency of the reference oscillator is equal to an integer quotient obtained by dividing the oscillation frequency by a plurality of the reference signals. PLL circuit. 2. A fixed frequency divider is provided between the reference oscillator and the phase comparator, and the reference signal is set to be equal to an integer value obtained by dividing the quotient by the division ratio of the fixed frequency divider. 2. The PLL circuit according to claim 1, wherein the number is set. 3. The method according to claim 1, wherein the number of the phase comparators is set to be equal to the quotient or the value.
Or the PLL circuit according to claim 2. 4. A reference signal is selected one by one from a plurality of said reference signals, a feedback signal is selected one by one from a plurality of said feedback signals, and the selected two signals are compared in phase. 3. The PLL circuit according to claim 1, wherein the phase comparator comprises a single phase comparator.