JP2002325033A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit whose lockup time is quick, whose power consumption is small, and whose switching timing is proper. SOLUTION: This PLL circuit is provided with a generating means 2 for generating a plurality of reference signals, a first variable frequency divider 9 and a second variable frequency divider 15 for frequency-dividing the output signal of a voltage control oscillator 11, and for outputting each feedback signal, a first phase comparator 7 and a second phase comparator 8 for phase- comparing each feedback signal with each reference signal, and a generating part 16 for preventing the output of the second phase comparator 8 from being transmitted to the post stage according to the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, this type of circuit is, for example, "SANY".
O TECHNICAL REVIEW ”, VOL. 1
0, NO. 1, FEB. It is shown on page 32 of 1978. However, this circuit has one phase comparator,
Since the phase comparison is performed only once during one cycle of the reference signal, there is a first disadvantage that the lock-up time is long.

[0003] In order to solve this drawback, Japanese Patent Laid-Open No.
No. 135822 has been proposed. According to this publication, a generating means for generating a plurality of reference signals having different phases, a plurality of (for example, 16) frequency dividers for dividing the output signal of the voltage controlled oscillator, and a plurality of phase comparators are provided. ing.

[0004]

However, the circuit disclosed in the above publication has a second drawback in that the power consumption is large. The inventor of the present invention has investigated the cause and found that the reason is that a plurality of frequency dividers are provided.

The present applicant has filed an application in Japanese Patent Application No. 2001-15789 in order to solve these disadvantages. In FIG. 4 showing this application, generating means 100 for generating a plurality of reference signals, variable frequency dividers 102 and 103 for dividing the output signal VO of the voltage controlled oscillator 101, and a phase comparator 10
4 and 105 are provided. During the search, the phase comparators 104 and 105 are both operating. When the output signal VO is locked (steady state), the generation unit 106 operates, the output of the phase comparator 105 stops, and the phase comparator 1
The switching operation is performed so that only 04 is output.

However, in the above-mentioned circuit, the above-mentioned switching is performed at the time of the search before locking, and the switching timing is too early. The present inventor has investigated the cause, and found that the frequency of the clock signal output from the reference oscillator 107 to the generating unit 106 is low, so that the width of the dead zone generated by the generating unit 106 does not become narrow. Was. In view of the above, the present invention provides a PLL circuit having a fast lock-up time, low power consumption, and appropriate switching timing in consideration of the conventional disadvantages.

[0007]

In order to solve the above problems, according to the present invention, a generating means for generating a plurality of reference signals, an output signal of a voltage controlled oscillator is divided, and each feedback signal A first variable frequency divider and a second variable frequency divider that output a signal; a first phase comparator and a second phase comparator that compare the phase of each feedback signal with each reference signal; A generation unit that operates so as not to transmit the output of the phase comparator to the subsequent stage.

According to the present invention, the generation unit uses the output signal as a clock to generate a dead band of the second phase comparator before and after the reference signal.

According to the third aspect of the present invention, the generation section is provided so as to vary the width of the dead zone.

According to the present invention, the generation unit determines the generation timing and width of the dead band in accordance with the input instruction signal and the reference signal.

According to a fifth aspect of the present invention, there is provided a detector for detecting whether or not the output signal is locked, and a control unit,
The control unit stops the operation of the generating unit when unlocked, and operates the generating unit when locked.

According to the present invention, the first variable frequency divider has a frequency division number N (N is a value obtained by dividing a set frequency by a reference frequency), and the second variable frequency divider has a frequency division number. Number N / n
(N is an integer of 3 or more).

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit 1 according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the PLL circuit 1, and FIG. 3 is a time chart of each signal used in the PLL circuit 1.

In these figures, the generating means 2 is, for example,
Reference oscillator 3, fixed frequency divider 4, ring counter 5
And an OR gate 6. The fixed frequency divider 4 divides the frequency by, for example, a frequency division number of 64, and is connected between the reference oscillator 3 and the ring counter 5. Fixed frequency divider 4
Is a signal obtained by dividing the signal output from the reference oscillator 3 (the oscillation frequency is, for example, 25.6 MHz) by 64 (frequency is 400
KHz) is output to the ring counter 5.

The ring type counter 5 is connected to, for example, 16 flip-flops (not shown).
In response to the input of the 400 KHz signal, 16 signals FR1, FR2,..., FR16 are output.

The signal FR2 is a signal FR1 (first reference signal).
Is delayed from the signal FR1 by 1/16 period (TR). Similarly, the signal FRA (A is an integer from 2 to 16)
Is delayed from the signal FR1 by (A-1) / 16 cycle. In this way, each frequency of the reference signals FR1 to FR16 is 400 KHz ＝ 16 = 25 KHz, which matches the desired channel space (inter-station frequency).

The first reference signal FR1 is supplied to the first phase comparator 7
Is input to one input side. Each of the signals FR2 to FR16 is input to the OR gate 6, and the output of the OR gate 6 is input to one input side of the second phase comparator 8. That is, the first reference signal FR1 is input to the first phase comparator 7, the plurality of signals FR2 to FR16 are added by the OR gate 6, and the added second reference signal FR is input to the second phase comparator 8. You. As described above, the generation means 2 includes a plurality of reference signals,
That is, a first reference signal FR1 and a second reference signal FR are generated.

The first variable frequency divider 9 is, for example, a programmable divider. Further, the first variable frequency divider 9 may be composed of a two-coefficient prescaler, a swallow counter, a course counter, and the like, if necessary.

For example, it is assumed that the user has set 1600 MHz using a set frequency key (not shown). The control unit 10 (comprising a microcomputer or the like) connected to the set frequency key provides a frequency division number N for the first variable frequency divider 9.
And outputs it to the first variable frequency divider 9 (in FIG. 1, a connection line between the control unit 10 and the first variable frequency divider 9 is not shown).

That is, N = 1600 × 1000 KHz ÷ 2
5KHz = 64000 (reference frequency is 25KHz
Because). As described above, the first variable frequency divider 9 is set to the value obtained by dividing the set frequency by the reference frequency, ie, the frequency division number N.

As described above, the first feedback signal FV 1 obtained by dividing the output signal VO of the voltage controlled oscillator 11 by N is input to the other input side of the first phase comparator 7.

The first phase comparator 7 has a first reference signal FR1.
And the first feedback signal FV 1, and outputs a pump-up signal U 1 and a pump-down signal D 1 to the first charge pump 12. That is, the first phase comparator 7 outputs the first reference signal FR1 and the first variable frequency divider 9
The phase of the feedback signal FV1 is compared.

The first charge pump 12 outputs the signal U
1, a first error signal is generated based on D1, and the first error signal ER1 is output to the low-pass filter 13.

The low-pass filter 13 outputs the first error signal E
A control voltage CV in which the high frequency component of R1 is cut off is generated,
Output to the voltage controlled oscillator 11.

These generating means 2 and first phase comparator 7
, A first charge pump 12 and a low-pass filter 13
, The voltage-controlled oscillator 11, the first variable frequency divider 9, etc., constitute a first PLL frequency synthesizer 14.

The second variable frequency divider 15 is, for example, a program divider, or may be composed of a two-coefficient prescaler 9, a swallow counter, a course counter, and the like, if necessary.

Assuming that the total number of a plurality of signals output from the ring counter 5 is n (n is an integer of 3 or more), the frequency division number N / n is given to the second variable frequency divider 15 (set). ). At this time, the second reference signal FR is, for example, a signal obtained by adding 15 signals FR2 to FR16.

For example, if n = 16, the control unit 1
0 is N / n = 64000 / for the second variable frequency divider 15.
A division number of 16 = 4000 is given (connection lines are not shown in FIG. 1).

In this manner, the second variable frequency divider 15 divides the output signal VO of the voltage controlled oscillator 11 by N / 16 and 16 Hi level signals (FP1 to FP1) per one cycle TR.
FP16, but not shown), to a selector (not shown). The selector includes 15 Hi level signals FP2 to FP2.
FP16 is selected, and the second feedback signal FV obtained by adding the signals FP2 to FP16 is output to the second phase comparator 8.

As described above, one input side of the second phase comparator 8 has a different phase (n-
1) A second reference signal FR (see FIG. 3B) obtained by adding the signals FR2 to FR16 is input.

The second phase comparator 8 includes a second variable frequency divider 15
Compares the phase of the second feedback signal FV and the second reference signal FR, and outputs a pump-up signal U2 and a pump-down signal D2.

As described above, the first variable frequency divider 9 and the second variable frequency divider 15 for dividing the output signal VO of the voltage controlled oscillator 11 and outputting the feedback signals FV1 and FV are provided. I have. First phase comparator 7 and second phase comparator 8
Are the feedback signals FV1, FV and the reference signals FR1, FR
Are compared in phase.

The generation unit 16 (to be described in detail later) receives the first reference signal FR1, the second reference signal FR, the output signal VO, the frequency division number data, the lock signal, and the like, and outputs the generation signal S. Is what you do.

A generation signal S is input to one input side of the AND gate 17, and a pump-up signal U2 of the second phase comparator 8 is input to another input side. AND gate 17
Is connected to one input side of the second charge pump 18.

A generation signal S is input to one input side of the AND gate 19, and a pump-down signal D2 of the second phase comparator 8 is input to another input side. And Gate 19
Is connected to another input side of the second charge pump 18.

The second charge pump 18 generates a second error signal ER2 based on the outputs of the AND gates 17 and 19, and supplies the second error signal ER2 to the low-pass filter 13.
Is output.

The low-pass filter 13 outputs the second error signal E
A control voltage CV in which a high-frequency component of R2 is cut off is generated,
Output to the voltage controlled oscillator 11. These generating means 2
, A second phase comparator 8, a generator 16, AND gates 17, 19, a second charge pump 18, a low-pass filter 13, a voltage controlled oscillator 11, a second variable frequency divider 15, and the like. The second PLL frequency synthesizer 20 is configured.

The first reference signal FR1 is input to one input side of the detector 21, and the first feedback signal FV1 is input to the other input side.
Is entered. The detector 21 detects whether or not the output signal VO is locked (reached a steady state).

For example, the detector 21 outputs a Lo level signal when unlocked (at the time of search). Then, for example, when the frequency of the output signal VO reaches ± 5% of the set frequency (this is called lock), the detector 21 outputs a synchronization detection signal composed of a Hi level signal.

The control section 10 outputs to the generation section 16 a lock signal R obtained by inverting the synchronization detection signal. That is, at the time of search, the control unit 10 outputs a Hi level signal to the generation unit 16, and at the time of locking, outputs a Lo level signal (this is called a lock signal R).

Next, the generator 16 used in the PLL circuit 1 will be described mainly with reference to the block diagram of FIG. In FIG. 2, the generating unit 16 includes a subtractor 22 and an OR gate 2.
3, a first counter 24, a second counter 25, a flip-flop 26, an OR gate 27, and the like.

The subtracter 22 stores the set frequency division number data Pr
eSet (that is, N / n) and the instruction signal P_Width
Is entered. The instruction signal is a signal for instructing a value of a half G (see (f) in FIG. 3) of the width of the Lo level signal in the generation signal S.

As described above, the subtracter 22 subtracts the instruction signal P_Width from the set frequency data PreSet, and outputs the subtracted value H to the first counter 24.

The OR gate 23 has a first reference signal FR1
And the second reference signal FR are input, and the output side of the OR gate 23 is connected to the first counter 24 and the second counter 25. In this manner, the OR gate 23 outputs the addition signal I obtained by adding the first reference signal FR1 and the second reference signal FR.
Is output to the first counter 24 and the second counter 25.

As described above, the subtraction value H is set (set) in the first counter 24, and the output signal VO (VCO
clk) and the addition signal I are input. Then, the first counter 24 detects the rising of the addition signal I, that is, the timing T.
Reset is performed at 1, T2,..., T9.

The first counter 24 outputs the output signal VCO starting at each reset point, that is, T1,..., T9.
Using clk as a clock, a subtraction value H is used as a count. Then, when the count value reaches the set value, the first counter 24 outputs an end signal A (see FIG. 3C).

In the second counter 25, an instruction signal P_Width indicating the G value of the generation signal S is set.
The output signal VCOclk and the addition signal I are input. Then, the second counter 25 is reset at the rise of the addition signal I, that is, at timings T1, T2,..., T9.

The second counter 25 outputs the output signal VCOcl starting at each of the reset points T1,..., T9.
The G value is counted using k as a clock. When the count value reaches the set value, the second counter 25
An end signal B is output (see FIG. 3D).

The end signal A output from the first counter 24 and the end signal B output from the second counter 25 are input to the flip-flop 26. Then, the flip-flop 26 is reset by the end signal A, and the end signal B
Is set by

As a result, the flip-flop 26 outputs the Lo level signal from the time when the end signal A is output to the time when the end signal B is output. In other periods, the flip-flop 26 outputs a Hi-level signal (see FIG. 3E).

In FIG. 2, the synchronization detection signal LOCK detected by the detector 21 is converted into a lock signal R by an inverter 28 in the control unit 10 and input to one input side of the OR gate 27. The signal output from the flip-flop 26 is input to another input side of the OR gate 27.

The OR gate 27 is connected to the flip-flop 26
And the lock signal R are added and output as a generated signal S.

That is, at the time of unlocking (at the time of searching), the lock signal R is a Hi level signal,
Outputs a generation signal S which is a Hi level signal. As described above, at the time of the search, the phases of the reference signals FR1 and FR and the feedback signals FV1 and FV are greatly shifted, so that the generation signal S is controlled to be a Hi level signal.

Also, at the time of locking, since the lock signal R is a Lo level signal, the OR gate 27 outputs the same generation signal S as the output of the flip-flop 26 (FIG. 3).
(F)). That is, when the control unit 10 is unlocked,
Operation of the generation unit 16 (that is, output of the generation signal S)
Is stopped, and the operation of the generation unit 16 is performed at the time of locking. The generation unit 16 is configured by the components 22, 23, 24, 25, 26, 27, and the like.

The features of the generator 16 are summarized below. The generating unit 16 uses the output signal VCOclk (VO) as a clock to generate a dead band C of the second phase comparator 8 before and after the reference signals (FR1 and FR) (FIG. 3).
(F)).

Instruction signal P_Wi input to generation section 16
The width of the dead zone C is determined by the G value indicated by dth. That is, the generation unit 16 is provided to change the width of the dead zone C.

Further, the generating section 16 calculates the following according to the input instruction signal P_Width and the reference signals FR1 and FR.
The generation timings T1, T2,..., T9 and the width (2G) of the dead zone C are determined.

In this manner, as shown in FIG. 1, the AND gate 17 outputs a signal obtained by adding the pump-up signal U2 of the second phase comparator 8 and the generation signal S to the second charge pump 18. I do. The AND gate 19 outputs to the second charge pump 18 a signal obtained by adding the pump-down signal D2 of the second phase comparator 8 and the generation signal S.

As a result, when the generation signal S is at the Lo level,
The added signal becomes Lo level, and the pump-up signal U2 and the pump-down signal D2 are not transmitted to the second charge pump 18. That is, the generation unit 16 operates according to the output signal VCOclk so as not to transmit the output of the second phase comparator 8 to the subsequent stage. With the above parts, this PL
The L circuit 1 is configured.

Next, according to FIG. 1 to FIG.
The operation of the circuit 1 will be described. First, for example, it is assumed that the user sets 1600 MHz using the set frequency key and presses the start key.

The control unit 10 controls the first variable frequency divider 9
Dividing number N = 1600 × 1000KHz / 25KHz = 6
4000 is output (connection lines are not shown). At the same time, the control unit 10 controls the second variable frequency
= 4000 is output (connection lines are not shown).

The oscillation signal from the reference oscillator 3 (25.6M
Hz) is divided by a fixed frequency divider 4 so as to be 400 KHz.
To FR16 are output. The signals FR1 to FR16 have a reference frequency of 25 KHz and timings T1, T2,.
Respectively (see FIG. 3).

The first variable frequency divider 9 has a voltage controlled oscillator 11
Is divided by the frequency division number N = 64000 to generate a first feedback signal FV 1 and output it to the first phase comparator 7.

The first phase comparator 7 outputs the first reference signal FR1
And the first feedback signal FV1 and outputs a pump-up signal U1 and a pump-down signal D1 to the first charge pump 12.

The first charge pump 12 outputs the signal U
1, the first error signal ER1 is output to the low-pass filter 13 in accordance with D1. The low-pass filter 13 is the first
A control voltage CV is output to the voltage control oscillator 11 according to the error signal ER1.

The second variable frequency divider 15 calculates N / 16 =
The output signal VO is frequency-divided by a frequency division number of 4000, and the second feedback signal FV is output.

Next, the second phase comparator 8 sets the rising edge FR2 of the second reference signal FR and Hi in the second feedback signal FV.
The phase of the level signal FP2 is compared, and the pump-up signal U
2. Output the pump down signal D2. Similarly, the second phase comparator 8 calculates the rising FRA (A is an integer from 3 to 16) of the second reference signal FR and the Hi level signal FPA (A is 3 to 16) in the second feedback signal FV. ), And outputs a pump-up signal U2 and a pump-down signal D2.

At this time, since it is unlocked, the detector 21 detects unlocking, and the control unit 10
Output a Hi-level signal to the OR gate 27.
As a result, the generation unit 16 stops operating, and the generation signal S becomes H
The i-level signal is maintained.

The AND gate 17 receives the pump-up signal U
A signal obtained by adding 2 to the generation signal S is output to the second charge pump 18. The AND gate 19 outputs a signal obtained by adding the pump-down signal D2 and the generation signal S to the second charge pump 18.

The second charge pump 18 outputs a second error signal ER2 to the low-pass filter 13 according to the added signal. The low-pass filter 13 outputs a control voltage CV to the voltage controlled oscillator 11 according to the second error signal ER2.

With this configuration, 1 of the first reference signal FR1
Since the phase comparison is performed 16 times during the period TR (FIG. 3
reference). The lock-up time is reduced to about 1/16 of that of the conventional one-stage phase comparator.

As described above, when the above phase comparison is repeated, output signal VO approaches the set frequency. When the frequency of the output signal VO reaches, for example, ± 5% of the set frequency, the detector 21 detects that the output signal VO is locked.

As a result, the control unit 10 outputs a Lo level signal (lock signal R) to the OR gate 27 of the generation unit 16. At this time, the generation unit 16 performs an operation and outputs a generation signal S to the AND gates 17 and 19 (FIG. 3).
(F)).

When the dead zone C is reached, the generation unit 1
6 outputs a Lo level signal to the AND gates 17 and 19. As a result, the outputs U2, D2 of the second phase comparator 8
Is controlled in the latter stage, that is, not to be transmitted to the second charge pump 18. Thus, the second charge pump 18
Stops the output of the second error signal ER2, and the switching operation starts.

At this time, it is assumed that the G value indicated by the instruction signal P_Width is set to, for example, one clock of the output signal VCOclk. The width 2G of the dead zone C is 2G
= 2 ÷ (1600 × 10 ⁶ ) seconds = 1.25 nanoseconds. In the conventional PLL circuit, since the clock of the reference oscillator is used, the width of the dead band is 2 ÷ (25.6).
× 10 ⁶ ) seconds = 78 nanoseconds.

As described above, the width of the dead zone C is reduced to about 1/62 times that of the related art. The switching timing (at the time when the phase comparison is switched from 16 times to 1 time in one cycle) is later than the conventional one, and the timing becomes appropriate. as a result,
Lock-up time is shorter than before.

After the switching operation, the control unit 10
By stopping the operation of the second variable frequency divider 15 and the second charge pump 18, power consumption can be reduced. Thus, the second PLL frequency synthesizer 20
Stop the operation of.

After the switching operation, the first PLL frequency synthesizer 14 is continuously operated. By continuously operating the synthesizer 14, the set frequency 16
An output signal VO that exactly matches 00 MHz can be stably output.

[0079]

According to the first aspect of the present invention, a generating means for generating a plurality of reference signals, a first variable frequency divider for dividing an output signal of a voltage controlled oscillator and outputting each feedback signal, and a second variable frequency divider for outputting respective feedback signals.
A variable frequency divider, a first phase comparator and a second phase comparator for comparing phases of each feedback signal and each reference signal, and an output of the second phase comparator is not transmitted to a subsequent stage according to the output signal. And an operating generator. Like this
Since the operation of the generating unit is performed according to the output signal of the control oscillator, the width of the dead band can be reduced. As a result, the timing of switching from the multi-stage phase comparison to the one-stage phase comparison becomes appropriate (later than before).

According to a second aspect of the present invention, the generation section uses the output signal as a clock and generates a dead band of the second phase comparator before and after the reference signal. With the above configuration, the width of the dead band can be narrowed, so that the switching timing is later than before. As a result, the period of the multi-stage phase comparison becomes longer, and the speed is further increased.

According to a third aspect of the present invention, the generation section is provided so as to vary the width of the dead zone.
Thus, by changing the width of the dead band, the switching timing from the multi-stage phase comparison to the one-stage phase comparison can be arbitrarily set.

According to a fourth aspect of the present invention, the generation section determines the generation timing and width of the dead band in accordance with the input instruction signal and the reference signal. With the above configuration, the generation timing and width of the dead band can be set accurately.

According to a fifth aspect of the present invention, there is provided a detector for detecting whether or not the output signal is locked, and a control unit, wherein the control unit stops the operation of the generation unit when unlocked, and Sometimes, the configuration is such that the generation unit operates.
As described above, since the generation unit operates only at the time of locking,
The timing at which the output of the second phase comparator is not transmitted to the subsequent stage can be set accurately.

According to a sixth aspect of the present invention, the first variable frequency divider has a frequency division number N (N is a value obtained by dividing a set frequency by a reference frequency), and the second variable frequency divider has a frequency division number. Number N / n
(N is an integer of 3 or more). With the above configuration, the phase comparator performs the phase comparison n times in one cycle, and the lock-up time is shortened. Also, 1
In order to perform the phase comparison n times during the period, two variable frequency dividers may be used. As a result, the number of variable frequency dividers can be reduced as compared with the related art, so that the cost is reduced, the LSI is easily implemented, and the power consumption is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit 1 according to an embodiment of the present invention.

FIG. 2 is a block diagram of a generation unit 16 used in the PLL circuit 1.

FIG. 3 is a time chart of each signal used in the PLL circuit 1;

FIG. 4 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 2 generator 7 first phase comparator 8 second phase comparator 9 first variable frequency divider 11 voltage controlled oscillator 15 second variable frequency divider 16 generator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC30 CC38 CC41 CC52 CC53 DD32 DD43 EE09 FF06 FF09 GG04 GG15 HH08 KK03 KK40

Claims (6)

[Claims] A generating means for generating a plurality of reference signals;
A first variable frequency divider and a second variable frequency divider for dividing the output signal of the voltage controlled oscillator and outputting each feedback signal; a first phase comparator for comparing the phase of each feedback signal with each reference signal; A PLL circuit comprising: a two-phase comparator; and a generation unit that operates according to the output signal so as not to transmit an output of the second phase comparator to a subsequent stage. 2. The PLL circuit according to claim 1, wherein the generation unit generates the dead band of the second phase comparator before and after the reference signal using the output signal as a clock. . 3. The PL according to claim 2, wherein the generation unit is provided to change a width of the dead band.
L circuit. 4. The PLL according to claim 3, wherein the generation unit determines a generation timing and a width of the dead band in accordance with the input instruction signal and the reference signal.
circuit. 5. A detector for detecting whether or not the output signal is locked, and a control unit, wherein the control unit stops the operation of the generation unit when unlocked, and the generation unit when locked. 2. The PLL circuit according to claim 1, wherein 6. The first variable frequency divider has a frequency division number N (N is a value obtained by dividing a set frequency by a reference frequency), and the second variable frequency divider has a frequency division number N / n (n 2. The PLL circuit according to claim 1, wherein an integer of 3 or more is set.