JP2002111493A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a quick pulling to a lock of a PLL circuit and also to attain a stability when the circuit is locked. SOLUTION: In the PLL circuit, with applying a lock signal S indicating whether in a locked state or not to a gated inverter 12 and 14, signal passes 1a and 1b are switched. Delays owing to delay lines 1 and 2 are reduced in a non-locked state, and increased in a locked state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION PLL including a phase comparator for comparing the phases of an input signal and a reference signal, and a charge pump driven by the output of the phase comparator, for locking the phase of the input signal to the reference signal (Phase Locked Loop) circuit.

[0002]

2. Description of the Related Art Conventionally, PLLs have been used in various devices.
A circuit is used, and is also used in a tuner circuit of a radio receiver to create a local oscillation signal for extracting a desired station signal. The PLL circuit includes: a phase comparison circuit that compares a phase of an input signal with a phase of a reference signal and outputs a signal about the phase difference; and a charge pump driven by an output of the phase comparison circuit. The oscillation frequency of the voltage controlled oscillator (VCO) is controlled by the output of the charge pump.

[0003]

Here, the phase comparator detects a phase difference between two input signals, and the phase comparator has a dead zone corresponding to the circuit configuration.

When the dead zone is small, even a small phase difference between the input signal and the reference signal can be detected, and the charge pump can be driven to speed up the convergence of the lock. But,
In the lock state, it reacts to minute fluctuations of the input signal and the reference signal, and the lock state is released, so that a stable lock state cannot be obtained.

On the other hand, if the dead zone is large, a stable locked state can be maintained. However, with a small phase difference between the input signal and the reference signal, no signal is output from the phase comparator, and the convergence time of the lock becomes long.

For this reason, conventionally, a compromise between the lock-up time and the stability of the lock state has been found, and the characteristics and dead band width of the phase comparator have been determined. Therefore, there is a problem that it takes a long time for final convergence after driving the minute phase difference between the input signal and the reference signal.

[0007] In particular, in RDS (Radio Data System) in Europe, when receiving a radio wave from one broadcast station, a process of checking the reception state of another broadcast station is performed. In this case, the state of another broadcasting station must be checked within a very short time, and the tuning frequency must be controlled at a high speed. Therefore, there has been a demand for quicker locking of the PLL circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a PLL circuit capable of shortening the time until final convergence and achieving lock stability.

[0009]

SUMMARY OF THE INVENTION The present invention includes a phase comparator for comparing the phases of an input signal and a reference signal, and a charge pump driven by the output of the phase comparator. In a PLL circuit for locking to a reference signal, the phase comparator can switch the accuracy of detecting the phase difference between the input signal and the reference signal according to a control signal indicating whether the PLL circuit is in a locked state or an unlocked state. Features.

Therefore, in the unlocked state, the accuracy is increased, and the phase comparator outputs a signal even with a small error to speed up the pulling into the lock. In the locked state, the accuracy is reduced. In the above, the stability at the time of locking can be ensured by not outputting a signal in the case of a small error.

The phase comparator delays an input signal to generate a delayed input signal, a first delay line that delays a reference signal, and generates a delayed reference signal. A first flip-flop circuit whose state is controlled based on the phase difference between the signal and the delayed reference signal, and a second flip-flop circuit whose state is controlled based on the phase difference between the reference signal and the delayed input signal Preferably, the output of the first and second flip-flops drives the charge pump. By selecting such a delay line, it is possible to select an appropriate system of the phase comparison circuit.

Further, it is preferable that the first and second delay lines include a gated inverter, and the gated inverter is controlled by the control signal. By using the gated inverter, the delay line can be constituted by a plurality of inverters, and the characteristics at that time can be matched.

Each of the first and second delay lines has a plurality of paths, and the paths are switched by the control signal. When the control signal is in the first state, a path with a short delay is selected. Thereby, the amount of delay of the set or reset signal of the flip-flop with respect to the clock signal is reduced to reduce the phase difference, the output of the charge pump is reduced, and the dead zone of the phase comparator is increased,
When the control signal is in the second state, by selecting a path with a long delay, the amount of delay of the set or reset signal of the flip-flop with respect to the clock signal is increased, the phase difference is increased, and the output of the charge pump is increased. It is preferable to reduce the dead zone of the phase comparator by increasing the dead zone. By controlling such a dead zone, an appropriate precision of the phase comparator can be selected.

When the frequency output from the PLL circuit is changed, the control signal is brought into the second state, and
It is preferable that the second state be maintained during the non-locking period and be changed to the first state after locking.

[0015]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a phase comparator and a charge pump according to the embodiment. The input signal PI is input to the delay line 1, and a signal A, which is an inverted delay signal of the input signal PI which is delayed and inverted by a predetermined time, is output from the delay line 1. On the other hand, the reference signal RI is input to the delay line 2 and is delayed by a predetermined time and then inverted.
Signal B, which is an inverted delay signal of I, is output from delay line 2.

The input signal PI is also input to the clock signal input terminal of the flip-flop with reset 3, and the flip-flop 3 receives the inverted signal of the signal B. Therefore, the flip-flop 3
The signal at the D input terminal is taken in at the rise of the input signal PI, and is reset to “L” at a stage delayed by a predetermined time from the rise of the reference signal RI.

The reference signal RI is also input to the clock input terminal of the flip-flop 4 with a set, and the inverted signal of the signal A is input to the set input terminal of the flip-flop 4. Therefore, the flip-flop 4 captures the signal at the D input terminal at the rise of the reference signal RI, and is set to “H” at a stage delayed by a predetermined time from the rise of the input signal PI.

Further, a signal C which is an inverted Q output of the flip-flop 4 is inputted to a D input terminal of the flip-flop 3, and a signal D which is a Q output of the flip-flop 3 is inputted to the D input terminal of the flip-flop 4. Is entered.

The inverted Q output of the flip-flop 3 is connected to the gate of the P-channel transistor 5a on the power supply side of the charge pump 5, and the inverted Q output of the flip-flop 4 is connected to the grounded N-channel transistor 5b of the charge pump 5. Connected to the gate. The power supply side transistor 5a and the ground side transistor 5b are connected in series between the power supply and the ground. Then, the output φE becomes “H” by turning on the power supply side transistor 5a,
The output φE becomes “L” by turning on the ground side transistor 5b.
become.

Each of the delay lines 1 and 2 is configured by connecting inverters in series, and each has two signal paths. That is, signal path 1
Is a signal path 1a in which the inverter 11a, the gated inverter 12, and the inverters 11b, 11c, 11d are connected in series, and the input inverter connected in parallel to the gated inverter 12 (connected between the output of the inverter 11a and the inverter 11b). 13a, 13b, 13
c, 13d, and a signal path 1b in which gated inverters 14 are connected in series.

To the two upper and lower input terminals of the gated inverter 12, a signal obtained by further inverting a signal obtained by inverting the lock signal S by the inverter 15 and an output of the inverter 15 are supplied. The gated inverter 12 passes when the upper input terminal is “L”, and is in the prohibited state when the lower input terminal is “L”.
When the lock signal S is “L”, the state becomes the passing state.

On the other hand, a signal obtained by inverting the lock signal S by the inverter 17 and a lock signal S are supplied to two upper and lower input terminals of the gated inverter 14. Therefore, the gated inverter 15 enters the passing state when the lock signal S is “H”.

In this manner, either "L" or "H" of the lock signal S turns on one of the gated inverters 12 or 14, and the signal path is a short signal path with five inverters or a long signal path with nine inverters. A signal path is selected.

Although the above description has been made with respect to the delay line 1 for the input signal PI, the configuration of the delay line 2 is completely the same, and depending on the "L" or "H" of the lock signal S, Either the gated inverter 12 or 14 is turned on, and a short signal path with five inverters or a long signal path with nine inverters is selected as a signal path.

Therefore, the length of the signal path in the delay lines 1 and 2 is selected in accordance with the "L" or "H" state of the lock signal S, and the size of the dead zone for phase comparison is determined. As a result of the phase comparison, the output φE of the charge pump 5 is output.

Next, the operation of such a circuit will be described with reference to FIG.
It will be described based on. First, when the lock signal S is "L",
The case where the lock state is not set will be described. When the input signal PI and the reference signal RI become "H", the flip-flop 3 is reset to "L" and the flip-flop 4 is set to "H" by the signals A and B which are the delay signals. Normally, the flip-flop 3 is "L" and the signal D is "L", the flip-flop 4 is "H", and the signal C is "H". In this state,
When both the input signal PI and the reference signal RI rise,
The flip-flop 3 takes in the signal C which is the Q output of the flip-flop 4 at the rise of the input signal PI, and the flip-flop 4 takes in the signal D which is the Q output of the flip-flop 3 at the rise of the input RI. Therefore, the signal C which is the Q output of the flip-flop 4 becomes “L”,
The signal D output from the flip-flop 3 returns to “H”.

On the other hand, after the delay time in the delay lines 1 and 2, the signals A and B fall. As a result, the flip-flop 4 is set, the flip-flop 3 is set, the signal C becomes “H”, and the signal D becomes “L”.

When the signal D is "H", the signal E, which is the inverted Q output of the flip-flop 3, becomes "L", and the transistor 5a is turned on. On the other hand, when the signal C is "L", the signal F, which is the inverted Q output of the flip-flop 4, becomes "H", so that the transistor 5b is turned on.

Thus, the output φ of the charge pump 5
E slightly fluctuates, but “H” or “L” is not substantially output.

Next, when only the reference signal RI rises,
The flip-flop 4 captures “L” of the signal D corresponding to “L” of the flip-flop 3, the signal C falls, and the signal F rises. Thereafter, the signal B, which is a delay signal of the reference signal RI, falls and the flip-flop 3 is reset. However, the flip-flop 3 remains at "L" and does not affect the signals D and E.

Next, when the input signal PI rises,
The flip-flop 3 takes in the signal C. At this time, the signal C is “L”, the data of the flip-flop 3 does not change, and the signals D and E do not change. Then, after a predetermined delay time, since the signal A falls, the flip-flop 4 is set, and the signal C returns to “H” and the signal F returns to “L”. Therefore, during the period when the signal F is “H”, the charge pump 5
Transistor 5b is turned on, and output φE
Is output as "L".

Next, when only the input signal PI rises,
The flip-flop 3 takes in “H” of the signal C and outputs “H”.
Becomes As a result, the signal D rises and the signal E falls. Thereafter, the signal A falls, but the flip-flop 4 is at "H", and the setting does not affect the signals C and F. Next, when the reference signal RI rises, the flip-flop 4 captures the signal D. At this time, the signal D is “H”, the data of the flip-flop 4 does not change, and the signals C and F do not change. . Then, after a predetermined delay time, since the signal B falls,
The flip-flop 3 is reset, the signal D becomes “L”,
The signal E returns to "H". As a result, the signal E becomes “L”.
During this period, the transistor 5a of the charge pump 5 is turned on, and “H” is output as the output φE during the corresponding period.

As described above, when the input signal PI precedes, the transistor 5a is turned on for a period corresponding to the phase difference between the input PI and the reference RI, and the output φE of the charge pump 5 is turned on.
When the reference signal RI precedes, the transistor 5b is turned on according to the phase difference, and the output φE of the charge pump 5 outputs “L”.

Here, signals A, B, C, D, E, F, φ
The slow rise and fall of E is due to the characteristics of the transistor. The inverters 11a to 11d and 13a to 13d are also formed of the same CMOS as the charge pump, and generate the same dullness as the charge pump 5. Further, the gated inverters 12, 1
4 also has the same basic configuration and a similar signal transmission characteristic except that a switch is added.

Therefore, when the phase difference is small, the period during which the transistor 5a or 5b is turned on becomes short. Therefore, the variation of the output φE is small. For example, when the input signal PI slightly precedes the reference signal RI as shown in the last part of the left waveform diagram in FIG. 2, the period during which the signal E becomes "L" is short. Thus, the voltage change of the output φE is reduced. On the other hand, if the output φE change does not exceed a predetermined value,
The change is removed by a low pass filter etc.
The control voltage to the VCO is basically unchanged. For this reason,
The phase difference in the set range becomes a dead zone, in which case there is no change in the control voltage to the VCO.

Here, in the circuit of this embodiment, when the lock signal S becomes "H", the signal paths of the delay lines 1 and 2 are switched. Therefore, when the delay amounts of the delay lines 1 and 2 increase, the rising of the input signal PI and the reference signal RI is affected. The falling timing of the signals A and B is delayed. As a result, the reset / set timings of the flip-flops 3 and 4 are delayed, so that the period of “L” or “H” of the signals E and F becomes longer for the same phase difference between the input signal PI and the reference signal RI. As a result, a large change in the output φE is likely to occur.

The right side of FIG. 2 shows a case where the input signal PI precedes the reference signal RI with the same phase difference as the last case on the left side of FIG. In this case, since the signal E falls at the rise of the input signal PI and the signal E rises at the fall of the signal B, the phase difference between the input signal PI and the reference signal RI + the delay line in the delay line 2 is obtained. The signal E becomes "L". Thus, the amount of change in output φE increases. Therefore, the delay lines 1, 2
, The sensitivity of the phase comparison circuit can be improved and a small phase difference can be followed.

FIG. 3 shows the relationship between the phase difference and the output of the charge pump when the circuits of the delay lines 1 and 2 are switched. In the figure, a black triangle indicates a state where the delay amount of the delay lines 1 and 2 is large when locked, and a black circle indicates a state where the delay amount of the delay lines 1 and 2 is small when unlocked. As described above, by reducing the delay amount of the delay lines 1 and 2, an output is obtained from the phase comparison circuit according to a minute phase difference.

Next, FIG. 4 shows the entire configuration of the PLL circuit. The reference signal from the crystal oscillator 40 is frequency-divided by the reference divider 41 at an appropriate frequency division ratio, and supplied to the phase comparator 43 as the reference signal RI.
The phase comparator 43 includes the delay lines 1 and 2, the flip-flops 3 and 4, and the charge pump 5. The input signal PI which is the output of the programmable divider 42 is also supplied to the phase comparator 43, and performs the above-described phase comparison. Phase comparator 43-2
Outputs (signals E and F) are supplied to the charge pump 5. Then, the output φE of the charge pump 5 is supplied to the VCO 46 via the low-pass filter 45.

The VCO 46 outputs the oscillation signal to the outside of the system, and supplies the oscillation signal to the phase comparator 43 via the programmable divider 42 as an input signal PI.

Therefore, the oscillation frequency of the VCO 46 depends on the frequency of the divided input signal P in the programmable divider 42.
Control is performed so that I becomes equal to the reference signal RI. Therefore, by changing the frequency division ratio of the programmable divider 42 according to the desired station frequency, the oscillation frequency of the VCO 46 can be set to a frequency corresponding to the desired station frequency.

The output of the phase comparator 43 is supplied to an unlock detection circuit 44, which detects lock or unlock from the output of the phase comparator 43. This unlock detection circuit 44
For example, a clock of an appropriate frequency (for example, 1 kHz) is counted, and if a pulse that has continued for a predetermined time after detecting a pulse at the output of the phase comparator 43 is not detected, the locked state is determined. If a pulse is detected within a predetermined time, it is determined to be in an unlocked state. Then, the lock signal S is set to “L” or “H” according to the determination result.

In particular, the unlock detection circuit 44 determines that the lock state is unlocked in the initial state, and sets the lock signal S to "L".
Set to. Then, the locked state is changed several times (for example, 2
Times), the lock state is determined and the lock signal S is set to "H". On the other hand, when the unlocked state is detected several times (for example, four times) in the locked state, the lock signal S is output.
To “L”. When the desired station is switched and the frequency division ratio of the programmable divider 42 is changed, the unlocked state is always established.

Thus, in the unlocked state, a signal line with a large delay can be selected in the delay lines 1 and 2, and a phase difference detection signal is output even if the phase difference is minute, so that the locked state is established. Retraction can be made faster. On the other hand, in the locked state, the signal lines with small delays of the delay lines 1 and 2 can be selected, and the dead zone is increased to ignore the minute phase difference.
A stable locked state can be maintained.

[0046]

As described above, according to the present invention,
In the unlocked state, the accuracy is increased and the phase comparator outputs a signal even in the case of a small error to speed up the pull-in to the lock. By not outputting the signal, the stability at the time of locking can be secured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a phase comparator according to an embodiment.

FIG. 2 is a waveform chart showing signals of respective units in the phase comparator of FIG.

FIG. 3 is a diagram illustrating characteristics of a phase comparator.

FIG. 4 is a diagram illustrating an entire configuration of a PLL circuit.

[Explanation of symbols]

1, 2 delay lines, 3, 4 flip-flops, 5
Charge pumps, 11a-11d, 13a-13d Inverters, 12,14 gated inverters.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC24 CC52 CC53 CC58 CC59 DD32 DD42 DD43 DD48 EE10 GG04 HH10 JJ02 KK03 KK25 LL02

Claims (5)

[Claims] 1. A PLL circuit comprising: a phase comparator for comparing a phase of an input signal with a reference signal; and a charge pump driven by an output of the phase comparator, wherein the PLL circuit locks the phase of the input signal to the reference signal. A phase comparator that switches the accuracy of detecting a phase difference between an input signal and a reference signal in accordance with a control signal indicating whether the PLL circuit is in a locked state or an unlocked state. 2. The circuit according to claim 1, wherein the phase comparator delays an input signal and generates a delayed input signal; and a first delay line that delays a reference signal and generates a delayed reference signal. A second delay line, a first flip-flop circuit whose state is controlled based on the phase difference between the input signal and the delay reference signal, and a second flip-flop circuit whose state is controlled based on the phase difference between the reference signal and the delay input signal And a flip-flop circuit, wherein the outputs of the first and second flip-flops are:
A PLL circuit in which the charge pump is driven. 3. The PLL circuit according to claim 2, wherein the first and second delay lines include a gated inverter, and the gated inverter is controlled by the control signal. 4. The circuit according to claim 2, wherein each of the first and second delay lines has a plurality of paths, and the paths are switched by the control signal. In the case of the state, by selecting a path with a short delay, the amount of delay of the set or reset signal of the flip-flop with respect to the clock signal is reduced, the phase difference is reduced, and the output of the charge pump is reduced to reduce the phase comparator. When the control signal is in the second state, by selecting a path with a long delay, the amount of delay of the set or reset signal of the flip-flop with respect to the clock signal is increased, and the phase difference is increased. A PLL circuit that increases the output of the charge pump to reduce the dead zone of the phase comparator. 5. The circuit according to claim 4, wherein the control signal changes to a second state when the frequency output from the PLL circuit is changed, and the control signal maintains the second state during a period in which the PLL is not locked. To be in the first state after locking
L circuit.