JP2001127625A - Pll device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL device which is short in lockup time, smooth in locking, free from lock coming off and small in power consumption. SOLUTION: The PLL device is provided with a generating means 6 that generates reference signals with different phases, variable frequency dividers 11-14 that frequency-divide an output of a voltage controlled oscillator 15 and output a feedback signal, and phase comparators 7-10 that compare a phase of each reference signal with a phase of the feedback signal. In the case of decreasing number of stages in use for the phase comparators 7-10, no output signals of the phase comparators 7-10 not in use are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PLL device.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus has been known, for example, as "SA".
NYO TECHNICAL REVIEW ”, VO
L. 10, NO. 1, FEB. This is shown in FIG. 1 on page 32 of 1978. According to FIG. 1, a reference oscillator that generates a reference signal RF, a variable frequency divider that divides an output signal FO to generate a feedback signal FV, and sets the phase and frequency of the feedback signal FV to the phase and frequency of the reference signal. Compared to the frequency,
One phase comparator for generating the error signal ER is provided. A low-pass filter that generates a control voltage CV in response to the error signal ER and a voltage-controlled oscillator that generates an output signal FO in response to the control voltage CV are provided.

[0003]

However, in this PLL device, the relationship between the frequency of the reference signal RF and the lock time is theoretically and unitarily determined if it is optimally designed.
Therefore, there is a first disadvantage that the lock time cannot be further reduced. In order to solve this, the inventor tried a configuration in which a plurality of reference signals having different phases are generated, and a phase comparator and a variable frequency divider are provided in multiple stages. However, even with the above configuration,
Lock time does not shorten. The present inventor has investigated the cause, and found that when the locks are close to each other, the outputs of the phase comparators interfere with each other, and the lock is not smoothly performed.

Further, in the above configuration, when the lock becomes close to the lock, the use of the phase comparator is switched from multiple stages to one stage, but there is a second disadvantage that the lock is released at this time. Further, in the conventional configuration, since the multi-stage variable frequency divider is operated even after locking, there is a third disadvantage that the power consumption is large. Therefore, the present invention provides a PLL device that has a short lock-up time, locks smoothly, does not lose lock, and consumes less power in consideration of the conventional drawbacks.

[0005]

In order to solve the above-mentioned problems, according to the present invention, there are provided a generating means for generating a plurality of reference signals having different phases, a frequency-divided output of a voltage controlled oscillator, and a feedback signal. And a plurality of phase comparators for comparing the phase of each of the reference signals and the feedback signal, and when the number of stages of the plurality of phase comparators is reduced, the number of the unused phase comparators is reduced. The output signal is not generated.

According to a second aspect of the present invention, each charge pump is provided at a subsequent stage of each of the phase comparators, and when the number of used stages is reduced, the charge pump connected to the unused phase comparator is set to a high impedance. .

According to a third aspect of the present invention, each detector is provided for detecting a locked state or a state close to the locked state based on an output of each of the phase comparators. To high impedance.

According to a fourth aspect of the present invention, the generation of the output signal of the phase comparator which is not used is stopped, and after a predetermined time,
The operation of the variable frequency divider connected to the phase comparator is stopped.

[0009]

FIG. 1 is a block diagram showing a PLL device 1 according to a first embodiment of the present invention.
In FIG. 1, a reference oscillator 2 outputs a reference signal FR1.
The delay circuits 3, 4, 5 respond to the reference signal FR1 and a plurality of reference signals FR2, FR having different phases from each other.
3. Generate FR4. The reference oscillator 2 and the delay circuits 3, 4, and 5 constitute (reference signal) generating means 6.

[0010] More specifically, the reference signal FR1 is input to the phase comparator 7. The delay circuit 3 sets the reference signal FR1 to 1
/ 4 cycle, and using it as a reference signal FR2,
Output to the phase comparator 8. The delay circuit 4 receives the reference signal FR
1 is delayed by 周期 cycle and output to the phase comparator 9 as the reference signal FR3. The delay circuit 5 delays the reference signal FR1 by 3/4 period, and delays it by the reference signal FR.
4 and output to the phase comparator 10.

Each input side of the variable frequency dividers 11, 12, 13, 14 is connected to the output side of the voltage controlled oscillator 15,
The frequency is divided by an integer division ratio.

The phase comparator 7 outputs the phase and frequency of the output (feedback signal FV1) of the variable frequency divider 11 and the reference signal F
Compare the phase and frequency of R1. As a result of the comparison, the phase comparator 7 outputs a pump-up signal and a pump-down signal to two output terminals, respectively. The detector 7a is composed of an AND gate or the like, takes the AND of the pump-up signal and the pump-down signal, and outputs the signal (detection signal) to a microcomputer (microcomputer) 16. The locked state is detected by the detector 7a. The charge pump 17 receives a pump-up signal and a pump-down signal, and outputs an error signal ER1.

Similarly, the phase comparator 8 determines the phase and frequency of the feedback signal FV2 of the variable frequency divider 12 and the reference signal FR2.
Are compared with each other in phase and frequency. As a result of the comparison, the phase comparator 9 outputs a pump-up signal and a pump-down signal to the detector 7b. The detector 7b ANDs the two signals and outputs the result to the microcomputer 16. The charge pump 18 receives the two signals and outputs an error signal ER2.

Further, the phase comparator 9 determines the phase and frequency of the feedback signal FV3 of the variable frequency divider 13 and the reference signal FR3.
Are compared with each other in phase and frequency. As a result of the comparison, the phase comparator 9 outputs a pump-up signal and a pump-down signal to the detector 7c, and the detector 7c ANDs the two signals and outputs the result to the microcomputer 16. The charge pump 19 receives the two signals and outputs an error signal ER3.

The phase comparator 10 compares the phase and frequency of the feedback signal FV4 of the variable frequency divider 14 with the phase and frequency of the reference signal FR4. As a result of the comparison, the phase comparator 10 outputs a pump-up signal and a pump-down signal to the detector 7d. The detector 7d performs an AND operation on the two signals and outputs the result to the microcomputer 16. The charge pump 20 receives the two signals and outputs an error signal ER4. As described above, each of the phase comparators 7, 8, 9, and 10 outputs the reference signal F
R1, FR2, FR3, FR4 and each feedback signal FV1,
The phases of FV2, FV3, and FV4 are compared, and as a result, error signals ER1, ER2, ER3, and ER4 are output.

The low-pass filter 21 includes a phase comparator 7,
Error signals ER1, ER2, ER3 from 8, 9, 10
In response to the control signal ER4, the control voltage CV is
Output to The voltage controlled oscillator 15 controls the control voltage CV
Generates an output signal VO.

The switches 22, 23, 24, 25 are composed of, for example, gates. The switch 22 is provided between the output side of the voltage controlled oscillator 15 and the input side of the variable frequency divider 11. The switch 23 is provided between the output side of the voltage controlled oscillator 15 and the input side of the variable frequency divider 12. The switch 24 is connected to the output side of the voltage controlled oscillator 15 and the variable frequency divider 1
3 is provided between the input side. The switch 25 is provided between the output side of the voltage controlled oscillator 15 and the input side of the variable frequency divider 14.

The control unit 26 includes, for example, the microcomputer 16 and a gate control circuit 27. The gate control circuit 27 outputs control signals G1, G2, G3, G4 and control signals g1, g2, g3, g4 in response to the signals from the microcomputer 16 and the input of the reference signals FR1 to FR4. Consists of circuits.

The control signal G1 is supplied to the switch 22.
The control signal G2 is supplied to the switch 23, and the control signal G3
Is supplied to the switch 24, and the control signal G4 is supplied to the switch 25.
Supplied to The control signals g1, g2, g3, and g4 output from the gate control circuit 27 are supplied to charge pumps 17, 18, 19, and 20, respectively. The gate control circuit 27 is disclosed in Japanese Patent Application No. 11-215 filed by the present applicant.
No. 251, and the detailed description of the circuit 27 is omitted in this specification.

Next, the charge pump 17 will be described with reference to the block diagram of FIG. In FIG. 2, the charge pump 17 is provided after the phase comparator 7. In the charge pump 17, one input side of the NAND gate 28 is connected to the first input terminal 29, and receives the control signal g1. The other input side of the NAND gate 28 is connected to the first output terminal 30 of the phase comparator 7, and receives the pump-up signal PU.

One input side of the AND gate 31 is connected to the second output terminal 32 of the phase comparator 7, and receives the pump-down signal PD. The other input side of the AND gate 31 is connected to the second input terminal 33, and receives the control signal g1.

The first transistor 34 is, for example, a P-channel MOS FET, and has a third input terminal 3 on the drain side.
5 and the power supply voltage VDD is supplied. The gate side of the first transistor 34 is connected to the output side of the NAND gate 28.

The second transistor 36 is, for example, an N-channel MOS FET, and the gate side is an AND gate 3
1 is connected to the output side. The source side of the second transistor 36 is grounded, and the drain side is the first transistor 3.
4 is connected to the source side.

The source side of the first transistor 34 and the second
The connection point of the transistor 36 with the drain side is the output terminal 3
7 and the error signal ER1 is output from the output terminal 37. The above components constitute a charge pump 17. The charge pumps 18, 19, and 20 have the same configuration as the charge pump 17. The PLL device 1 is configured by the above components.

Next, according to FIG. 1 to FIG.
The operation of the device 1 will be described. FIG. 3 is a timing chart of each signal used in the PLL device 1. In these figures, the user selects a frequency of, for example, 300 KHZ with a channel selection key, presses a start key, outputs an output signal VO of 300 KHZ, and then the user selects a frequency of, for example, 1500 KHZ with a channel selection key. An example in which the frequency is changed to is shown.

When the output signal VO of 300 KHZ is first output (the output signal VO is locked at this time), the detector 7a or 7b or 7c or 7d outputs a detection signal. Because it is a one shot, A
At time point 1 (see FIG. 3), the signal is a Lo signal.

Next, the user operates the channel selection key, and
It is assumed that KHZ has been changed to 1500 KHZ. According to the above change, the frequency change command is input to the gate control circuit 27. At this time, since the above-mentioned command is formed in a one-shot type, it becomes a Hi signal for a short time, and then becomes a low signal.
o signal (see A2 in FIG. 3).

At this time, the control signals G1 and g1 output from the gate control circuit 27 are switched from Hi signal to Lo signal.
The Lo state is maintained until a predetermined time elapses after the switching (see A4 in FIG. 3). Similarly, after the reset signal is output (A3 in FIG. 3), the control signal G
2, g2, G3, g3, G4, and g4 are maintained in the Lo state (see A5, A6, and A7 in FIG. 3). At this time, since the switches 22, 23, 24, and 25 are closed, the output signal VO is not output to each of the variable frequency dividers 11, 12, 13, and 14. Then, the frequency dividers 11, 12, 13, and 14 stop the counting operation and set the count value to a predetermined value (for example, 0).

At this time, the control signals g1 to g4 are Lo.
In this state, the charge pumps 17 to 20 become high impedance, and the error signals ER1, ER2, ER3, ER
4 is not output to the low-pass filter 21. Like this
The control unit 26 resets each of the variable frequency dividers 11 before each of the variable frequency dividers 11 to 14 starts the frequency dividing operation.

Then, in response to the rise (A8) of the reference signal FR1 by the gate control circuit 27, the control signal G1 rises (A9), the switch 22 starts to open, and the output signal VO changes to the variable frequency divider 11 The variable frequency divider 11 starts the frequency dividing operation. In accordance with the rise (A9) of the control signal g1, the charge pump 17 is released from the high impedance state, and the phase comparator 7 outputs the output signal VO divided by the variable frequency divider 11, that is, the feedback signal FV1 and the reference signal FR1.
(See A16 in FIG. 3) and the error signal ER
Outputs 1.

Similarly, the rising edge of the reference signal FR2 (A1
0), the control signal G2 rises (A11), the switch 23 starts opening, and the output signal VO changes to the variable frequency divider 12
, And the variable frequency divider 12 starts the frequency dividing operation. In accordance with the rise (A11) of the control signal g2, the charge pump 18 is released from the high impedance state, and the phase comparator 8 outputs the output signal VO divided by the variable frequency divider 12, ie, the feedback signal FV2 and the reference signal FR2. (See A17 in FIG. 3) and outputs an error signal ER2.

In response to the rise of the reference signal FR3 (A12), the control signal G3 rises (A13) and the switch 24
Forms an opening, the output signal VO is output to the variable frequency divider 13, and the variable frequency divider 13 starts the frequency dividing operation. In accordance with the rise (A13) of the control signal g3, the charge pump 19 is released from high impedance, and the phase comparator 9
The phase of the feedback signal FV3 is compared with that of the reference signal FR3 (see A18 in FIG. 3), and the error signal ER3 is output.

Further, the rise of the reference signal FR4 (A14)
, The control signal G4 rises (A15) and the switch 2
5 forms an open, the output signal VO is output to the variable frequency divider 14, and the variable frequency divider 14 starts the frequency dividing operation. Also,
In accordance with the rise (A15) of the control signal g4, the charge pump 20 is released from the high impedance state, and the phase comparator 10
Compares the phase of the feedback signal FV4 with the phase of the reference signal FR4 (see A19 in FIG. 3) and outputs an error signal ER4.

As described above, the control unit 26 controls each reference signal FR
1 to FR4 (for example, rising A8, A10, A1
2, A14, etc.), the frequency dividing operation of each of the variable frequency dividers 11 to 14 is started. Specifically, the gate control circuit 27 of the control unit 26 controls the switches 22 to 25 by using the control signals G1 to G4 in accordance with the phases of the reference signals FR1 to FR4.
Is started, and the high impedance of the charge pumps 17 to 20 is released by the control signals g1 to g4 (output signals are generated).

As described above, the reference oscillator 2 outputs the reference signal FR1 having the reference frequency FR (period TR = 1 / FR).
Occurs. The reference signals FR2, FR3, FR4 are sequentially delayed by 1/4 cycle (TR / 4) from the reference signal FR1 by the delay circuits 3, 4, 5, respectively.

Each of the variable frequency dividers 11, 12, 13,
The start of the frequency division operation of each of the reference signals FR1, FR2, F
The phase is adjusted to the phases of R3 and FR4. Therefore, at the start of the frequency division operation, the signals are sequentially delayed by TR / 4, and the phase comparison timings of the phase comparators 7, 8, 9, 10 are each delayed by approximately TR / 4. It was done.

As described above, by starting the frequency dividing operation of each of the variable frequency dividers 11 to 14 in accordance with the phase of each of the reference signals FR1 to FR4, the phase comparison timing of each of the phase comparators 7 to 10 becomes The intervals are substantially equal, and accurate phase comparison can be performed.

As described above, the reference signals FR1 to FR4 have different phases (for example, π / FR
Phase is shifted by two) and each reference signal F
A phase comparison is performed for each of R1 to FR4. As a result, during one cycle (TR) of the reference signal FR1, the phase comparison is performed a plurality of times (in the above description, four of A16, A17, A18, and A19).
Times), which is about 1 /
It is reduced by a factor of four.

Further, when the time has elapsed and the above-described phase comparison is repeated (A20, A21, A22, A23 in FIG. 3).
), The output signal VO reaches (locks) the set frequency. At this time, the detectors 7a, 7b, 7c, and 7d connected to any one of the phase comparators 7, 8, 9, and 10
Outputs a detection signal to the microcomputer 16. For example, suppose that the detector 7a detects lock. Microcomputer 1
6 outputs a lock detection signal to the gate control circuit 27 (see A24 in FIG. 3, the lock detection signal is a one-shot type).

As described above, each of the phase comparators 7, 8, 9, 10
Of each detector 7a or 7b or 7c or 7d
When the control unit 26 detects that the lock signal is in the locked state, the control unit 26 switches the control signals g2, g3, and g4 from the Hi signal to the Lo signal. As a result, the charge pumps 18, 19, 20 become high impedance (see FIG. 2). Therefore, the output signals of the phase comparators 8, 9, and 10 are not generated (that is, the output signals of the phase comparators 8, 9, and 10 are not output to the low-pass filter 21).

At this time, since the control signal g1 remains the Hi signal, the charge pump 17 is in an output enabled state (high impedance is released). As a result, the output signal of the phase comparator 7 is supplied to the low-pass filter 21 as an error signal ER1 via the charge pump 17.
, Is being output.

To summarize the above operation, each detector 7a,
When detecting the locked state or the state close to the locked state of 7b, 7c and 7d, the control unit 26 continues to output the control signal g1 in the Hi state and switches the control signals g2, g3 and g4.

As a result, the charge pumps 18 to 20 become high impedance, and the phase comparators 8 to 10 connected to the charge pumps 18 to 20 do not generate output signals. At this time, only the phase comparator 7 generates an output signal.
Thus, the number of stages used by the plurality of phase comparators 7 to 10 is 4
Reduced from one step to one step.

In other words, the plurality of phase comparators 7 to 10
When the number of stages used is reduced, the unused phase comparators 8 to 1
The charge pumps 18 to 20 connected to 0 are set to high impedance. At this time (see the time point T1 in FIG. 3), the control signals G1 to G4 remain in the Hi state, the variable frequency dividers 11 to 14 continue the frequency division operation, and output the feedback signals FV1 to FV4. to continue.

Further, after a lapse of a predetermined time (see the time T2 in FIG. 4) from the stop of the output signals of the phase comparators 8 to 10 (the time T1 in FIG. 3), the control unit 26 controls the control signals G2, G3
G4 is switched from the Hi signal to the Lo signal (A2 in FIG. 3).
6, A27, A28). The control signal G1 is H
The i state is maintained (see A25 in FIG. 3).

To summarize the above operation, the generation of the output signals of the unused phase comparators 8 to 10 is stopped (at time T1).
And after a lapse of a predetermined time (time T2), the variable frequency dividers 12 to 14 connected to the unused phase comparators 8 to 10
Stops the dividing operation (A26, A27, A28 in FIG. 3).
See). Thus, after locking, the variable frequency dividers 12-1
By stopping the number 4, power consumption can be reduced.

Further, since the control signal G1 is maintained in the Hi state, the switch 22 is continuously opened, and the variable frequency divider 11 continues the frequency dividing operation. Then, the phase comparator 7 compares the phase of the feedback signal FV1 output from the variable frequency divider 11 with the phase of the reference signal FR1 (see A29 and A30 in FIG. 3).

At this time, since the charge pump 17 controlled by the control signal g 1 is in an output enabled state, the charge pump 17 sends an error signal E to the low-pass filter 21.
Output R1. The low-pass filter 21 outputs a control signal CV to the voltage controlled oscillator 15 and
Keeps outputting the output signal VO having the set frequency.
That is, the locked phase comparator 7 keeps outputting.

The above contents will be summarized. Phase comparator 7,
Detectors 7a, 7b, 7c and 7 connected to 8, 9, 10
It is assumed that at least one (for example, 7a) of d has detected a lock. The detector 7a is connected to the microcomputer 1 of the control unit 30.
6, a lock detection signal is output.

The control unit 30 keeps outputting the locked or specific phase comparator 7 in response to the lock detection signal (see A25 in FIG. 3), and the other phase comparators 8, 9, 10
(See A26, A27, and A28 in FIG. 2), that is, the output signal is not generated.

After a lapse of a predetermined time of the above operation, the control unit 26
Keeps the frequency dividing operation of only the variable frequency divider 11 connected to the phase comparator 7 that keeps outputting. And the control unit 26
Stops the frequency dividing operation of the other variable frequency dividers 12, 13, 14.

[0052]

As described above, according to the first aspect of the present invention, a generating means for generating a plurality of reference signals having different phases and a variable frequency divider for dividing the output of the voltage controlled oscillator and outputting a feedback signal. A plurality of phase comparators for comparing the phase of each of the reference signals and the feedback signal, and when the number of stages of the plurality of phase comparators is reduced, an output signal of the unused phase comparator is not generated. I do.

According to the above configuration, the phase comparison is performed a plurality of times during one cycle of the reference signal before locking, and the lock-up time is shortened. Further, since the output signal of the unused phase comparator is not generated, it is possible to prevent the output of the phase comparator from interfering with the output of the used phase comparator.

According to the second aspect of the present invention, each charge pump is provided at the subsequent stage of each of the phase comparators, and when the number of used stages is reduced, the charge pump connected to the unused phase comparator is set to high impedance. Configuration. As described above, when the number of stages used is reduced by setting the charge pump connected to the unused phase comparator to high impedance, the output (error signal) of the charge pump is used as the output (error signal) of the charge pump used. ) Can be prevented. As a result, when the number of stages in which the phase comparator is used is reduced, it is possible to prevent the lock from being released (a sudden change from the locked state to the unlocked state).

According to a third aspect of the present invention, there is provided each detector for detecting a locked state or a state close to the locked state based on an output of each of the phase comparators. Is set to have a high impedance. As described above, when the detector detects that the detector is in the locked state or in the state close to the locked state, the charge pump is set to the high impedance state. Therefore, the amount of the output signal exceeding the target frequency (the amount of overshoot) is reduced. The lock-up time is shortened by the minute.

According to the present invention, the generation of the output signal of the phase comparator which is not used is stopped, and after a predetermined time,
The operation of the variable frequency divider connected to the phase comparator is stopped. As described above, when the number of stages of the phase comparator used is reduced, even if the generation of the output signal of the unused phase comparator is stopped, the frequency dividing operation of all the variable frequency dividers is continued for a predetermined time. As a result, it is possible to prevent output of an undesired output signal from a phase comparator that is not used when the number of stages used is reduced, so that locking can be performed smoothly and unlocking can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL device 1 according to an embodiment of the present invention.

FIG. 2 is a block diagram of charge pumps 17 to 20 used in the PLL device 1.

FIG. 3 is a timing chart of each signal used in the PLL device 1;

[Explanation of symbols]

 6 Generating means 7, 8, 9, 10 Phase comparator 11, 12, 13, 14 Variable frequency divider 15 Voltage controlled oscillator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC30 CC38 CC41 CC52 DD08 DD32 DD34 DD43 EE08 GG04 GG15 HH10 JJ02 JJ08 KK03 KK40

Claims (4)

[Claims] 1. A generator for generating a plurality of reference signals having different phases, a variable frequency divider for dividing the output of a voltage controlled oscillator and outputting a feedback signal, and comparing the phase of each of the reference signals and the feedback signal. A plurality of phase comparators, wherein when the number of stages used by the plurality of phase comparators is reduced, an output signal of the phase comparator that is not used is not generated. 2. The method according to claim 1, wherein each of said phase comparators is provided with a respective charge pump at a subsequent stage, and when reducing the number of stages to be used, said charge pump connected to said unused phase comparator is set to a high impedance. Item 1 PLL
apparatus. 3. A detector for detecting a locked state or a state close to a locked state based on an output of each of the phase comparators. When the detector detects the locked state, the charge pump is set to high impedance. 3. The PLL device according to claim 2, wherein: 4. The method according to claim 1, wherein the generation of the output signal of the phase comparator that is not used is stopped, and after a predetermined time, the operation of the variable frequency divider connected to the phase comparator is stopped. 1 PLL device.