JP2001127624A - Pll device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive PLL device that has a fast lockup time and where outputs of phase comparators are not interfered with each other. SOLUTION: The PLL device is provided with a generating means 6 that generates reference signals with different phases, variable frequency dividers 11-14 that frequency-divide an output of a voltage controlled oscillator 15 and output a feedback signal, and phase comparators 7-10 that compare a phase of each reference signal with a phase of the feedback signal. The dead band of the phase comparators 7-10 is made different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PLL device.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus has been known, for example, as "SA".
NYO TECHNICAL REVIEW ”, VO
L. 10, NO. 1, FEB. This is shown in FIG. 1 on page 32 of 1978. According to FIG. 1, a reference oscillator that generates a reference signal RF, a variable frequency divider that divides an output signal FO to generate a feedback signal FV, and sets the phase and frequency of the feedback signal FV to the phase and frequency of the reference signal. Compared to the frequency,
One phase comparator for generating the error signal ER is provided. A low-pass filter that generates a control voltage CV in response to the error signal ER and a voltage-controlled oscillator that generates an output signal FO in response to the control voltage CV are provided.

[0003]

However, in this PLL device, the relationship between the frequency of the reference signal RF and the lock time is theoretically and unitarily determined if it is optimally designed.
Therefore, there is a first disadvantage that the lock time cannot be further reduced. In order to solve this, the inventor tried a configuration in which a plurality of reference signals having different phases are generated, and a phase comparator and a variable frequency divider are provided in multiple stages. However, even with the above configuration,
Lock time does not shorten. The present inventor has investigated the cause, and found that when the locks are close to each other, the outputs of the phase comparators interfere with each other, and the lock is not smoothly performed.

In order to solve the above drawbacks, the present inventor has
A gate was provided after each phase comparator, a lock detector was provided, and a gate control circuit was provided. Before the lock is detected, all the phase comparators are output. After the lock is detected, one gate is opened, one phase comparator is output, the other gates are closed, and the outputs of the other phase comparators are stopped. Was. However, precise gate opening / closing timing is required, and if the timing is slightly shifted, the second disadvantage that the outputs of the phase comparators interfere with each other still remains. In addition, there is a fourth disadvantage that the cost is increased because components such as the lock detector are added. Therefore, the present invention provides a low-cost PLL device which takes into account such conventional disadvantages, has a fast lock-up time, does not interfere with the outputs of the phase comparators, and has a low cost.

[0005]

In order to solve the above-mentioned problems, according to the present invention, there are provided a generating means for generating a plurality of reference signals having different phases, a frequency-divided output of a voltage controlled oscillator, and a feedback signal. And a plurality of phase comparators for comparing the phases of the reference signal and the feedback signal, so that dead zones of the phase comparators are different.

According to the second aspect of the present invention, the number of output stages of each of the phase comparators is switched by providing different dead zones for the phase comparators without providing external switching means for each of the phase comparators.

According to the third aspect of the present invention, the phase comparator comprises a first phase comparator having a small dead zone and a second phase comparator having a large dead zone. And the second phase comparator outputs, and when the lock state is substantially established, only the first phase comparator outputs.

According to a fourth aspect of the present invention, the second phase comparator includes a first delay circuit to which the reference signal is inputted, and a second delay circuit to which the feedback signal is inputted.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL device 1 according to an embodiment of the present invention will be described with reference to the block diagram of FIG.
In FIG. 1, a reference oscillator 2 outputs a reference signal FR1. The delay circuits 3, 4, 5 respond to the reference signal FR1 and a plurality of reference signals FR2, FR having different phases from each other.
3. Generate FR4. The reference oscillator 2 and the delay circuits 3, 4, and 5 constitute (reference signal) generating means 6.

[0010] More specifically, the reference signal FR1 is input to the phase comparator 7. The delay circuit 3 sets the reference signal FR1 to 1
/ 4 cycle, and using it as a reference signal FR2,
Output to the phase comparator 8. The delay circuit 4 receives the reference signal FR
1 is delayed by 周期 cycle and output to the phase comparator 9 as the reference signal FR3. The delay circuit 5 delays the reference signal FR1 by 3/4 period, and delays it by the reference signal FR.
4 and output to the phase comparator 10.

Each input side of the variable frequency dividers 11, 12, 13, 14 is connected to the output side of the voltage controlled oscillator 15,
The frequency is divided by an integer division ratio.

The phase comparator 7 outputs the phase and frequency of the output (feedback signal FV1) of the variable frequency divider 11 and the reference signal F
Compare the phase and frequency of R1. As a result of the comparison, the phase comparator 7 outputs a pump-up signal and a pump-down signal to two output terminals (not shown), respectively. The charge pump 17 receives a pump-up signal and a pump-down signal, and outputs an error signal ER1.

Similarly, the phase comparator 8 determines the phase and frequency of the feedback signal FV2 of the variable frequency divider 12 and the reference signal FR2.
Are compared with each other in phase and frequency. The phase comparator 9 outputs a pump-up signal and a pump-down signal as a result of the comparison. The charge pump 18 receives the two signals and outputs an error signal ER2.

Further, the phase comparator 9 determines the phase and frequency of the feedback signal FV3 of the variable frequency divider 13 and the reference signal FR3.
Are compared with each other in phase and frequency. The phase comparator 9 outputs a pump-up signal and a pump-down signal as a result of the comparison.

The phase comparator 10 compares the phase and frequency of the feedback signal FV4 of the variable frequency divider 14 with the phase and frequency of the reference signal FR4. As a result of the comparison, the phase comparator 10 outputs a pump-up signal and a pump-down signal. The charge pump 20 receives the two signals and outputs an error signal ER4. Thus, each phase comparator 7,
8, 9, 10 are the reference signals FR1, FR2, FR3,
FR4 and each feedback signal FV1, FV2, FV3, FV4
Are compared with each other, and as a result, each error signal ER1,
ER2, ER3, and ER4 are output.

The low-pass filter 21 includes a phase comparator 7,
Error signals ER1, ER2, ER3 from 8, 9, 10
In response to the control signal ER4, the control voltage CV is
Output to The voltage controlled oscillator 15 controls the control voltage CV
Generates an output signal VO.

The switches 22, 23, 24, 25 are composed of, for example, gates. The switch 22 is provided between the output side of the voltage controlled oscillator 15 and the input side of the variable frequency divider 11. The switch 23 is provided between the output side of the voltage controlled oscillator 15 and the input side of the variable frequency divider 12. The switch 24 is connected to the output side of the voltage controlled oscillator 15 and the variable frequency divider 1
3 is provided between the input side. The switch 25 is provided between the output side of the voltage controlled oscillator 15 and the input side of the variable frequency divider 14.

The control unit 26 includes, for example, the microcomputer 16 and a gate control circuit 27. The gate control circuit 27 outputs control signals G1, G2, G3, and G4 based on each signal from the microcomputer 16 and the input of the reference signals FR1 to FR4, and is composed of a logic circuit.

The control signal G1 is supplied to the switch 22.
The control signal G2 is supplied to the switch 23, the control signal G3 is supplied to the switch 24, and the control signal G4 is supplied to the switch 25. The gate control circuit 27 is the same as that of Japanese Patent Application No. 11-215251 filed by the present applicant, and the description of the circuit 27 will be omitted in this specification.

Next, the phase comparators 7 to 10 will be described in detail with reference to FIGS. FIG. 2 is a block diagram of a second phase comparator (described later), and FIG. 3 is a characteristic diagram of the phase comparators 7 to 10. The phase comparators 7 to 10 are at least divided into two groups. For example, the phase comparator 7 is a first phase comparator and will be referred to as such below. Phase comparator 8,
Reference numerals 9 and 10 denote second phase comparators, which are hereinafter referred to as such.

The second phase comparators 8, 9, 10 will be described with reference to the block diagram of FIG. In FIG. 2, the first delay circuit 2
8 comprises, for example, a series circuit of a plurality of inverters.
The input side of the first delay circuit 28 is connected to the first input terminal 29, and the output side is connected to the clock terminal C of the flip-flop 30.

One terminal of the flip-flop 30 is connected to a second input terminal 32 via an inverter 31.
The input terminal D of the flip-flop 30 is connected to the inverted output terminal P of the flip-flop 33. The output terminal Q of the flip-flop 30 is connected to the first output terminal 34, and the inverted output terminal P of the flip-flop 30 is connected to the input terminal D of the flip-flop 33.

The second delay circuit 35 comprises, for example, a series circuit of a plurality of inverters. The input side is connected to the second input terminal 32 and the output side is connected to the clock terminal C of the flip-flop 33. The output terminal Q of the flip-flop 33 is connected to the second output terminal 36, and one terminal of the flip-flop 33 is connected to the first input terminal 29 via the inverter 37. These components constitute second phase comparators 8, 9, and 10.

In the second phase comparator 8, the first input terminal 2
9 is supplied with a reference signal FR2, and the second input terminal 32 is supplied with a feedback signal FV2. Then, the first output terminal 34 outputs the pump-up signal PU, and the second output terminal 3
6 outputs a pump-down signal PD.

In this configuration, when a pulse of the reference signal FR2 is input to the first input terminal 29, this pulse is delayed by the first delay circuit 28. When a pulse of the feedback signal FV2 is input to the second input terminal 32, the phase of the pulse is compared with the delay pulse, and a pump-up signal PU as a result is output from the first output terminal. As described above, by delaying the phase comparison timing in the first delay circuit 28 and the second delay circuit 35, the output voltage becomes zero even if the phase difference between the reference signal FR2 and the feedback signal FV2 is relatively large.

In FIG. 3, the horizontal axis shows the phase difference between the reference signal FR and the feedback signal FV, and the vertical axis shows the output voltage (pump-up signal PU, pump-down signal). The characteristic a is the characteristic of an ideal phase comparator having no dead zone. The characteristic b is a characteristic of the phase comparator having a large dead zone D2, and the characteristic c is a characteristic of a phase comparator having a small dead zone D1.

As described with reference to FIG. 2, the second phase comparators 8, 9, and 10 include the first delay circuit 28 and the second delay circuit 35.
, The output voltage becomes zero even if the phase difference between the reference signal FR and the feedback signal FV is relatively large. That is, the second phase comparators 8, 9, and 10 have the characteristic b shown in FIG. 3 and have a large dead zone D2.

The first phase comparator 7 comprises, for example, the second phase comparators 8, 9, 10 (see FIG. 2) from the first delay circuit 2
8 and the second delay circuit 35 are excluded. as a result,
The phase comparison timing of the reference signal FR1 and the feedback signal FV1 is the same as before, and the output voltage becomes zero even if the phase difference is relatively small. That is, the first phase comparator 7 has the characteristic c shown in FIG. 3 and has a small dead zone D1.

As described above, in the PLL device 1, the dead zones of the plurality of phase comparators 7 to 10 are made different. Specifically, the dead zone D1 of the first phase comparator 7 is made small, and the dead zone D2 of the second phase comparators 8, 9, 10 is made large. The above components constitute the present PLL device 1.

Next, according to FIG. 1 to FIG.
The operation of the device 1 will be described. In these figures, when the user first presses the start button, a start signal is input to the control unit 26.

The control unit 26 supplies a power supply voltage to each component shown in FIG. 1 according to the input of the start signal. The reference oscillator 2 outputs each of the reference signals FR1 to FR4. At this time, the control signals G1 to G4 remain Lo signals. The switches 22 to 25 are also closed, and the variable frequency dividers 11 to 11 are closed.
14 stops the frequency dividing operation.

When a predetermined time has elapsed from the input of the start signal, the control section 26 switches the control signal G1 to the Hi signal and outputs the Hi signal to the switch 22. as a result,
The variable frequency divider 11 starts the frequency dividing operation, and outputs the feedback signal FV1 obtained by dividing the output signal VO by the set frequency dividing ratio to the phase comparator 7.
Output to

When the time elapses and the reference signal FR1 rises, the phase comparator 7 compares the phase of the reference signal FR1 with the phase of the feedback signal FV1, and outputs the error signal ER1 via the charge pump 17 to the low-pass signal. Output to the filter 21.

When the time further elapses, the control unit 30 switches the control signal G2 to the Hi signal and opens the switch 23.
At this time, the switch 22 is kept open.

At this time, the variable frequency divider 12 starts the frequency dividing operation, and outputs the feedback signal FV2 to the phase comparator 8. When the time elapses and the reference signal FR2 rises, the phase comparator 8 compares the phase of the reference signal FR2 with the phase of the feedback signal FV2, and outputs an error signal ER2 to the low-pass filter 21 via the charge pump 18. .

When the time further elapses, the control unit 26 switches the control signal G3 to the Hi signal, and opens the switch 24.
At this time, the switch 23 is kept open.

At this time, the variable frequency divider 13 starts the frequency dividing operation and outputs the feedback signal FV3 to the phase comparator 9. When the time elapses and the reference signal FR3 rises, the phase comparator 9 compares the phase of the reference signal FR3 with the phase of the feedback signal FV3, and outputs an error signal ER3 to the low-pass filter 21 via the charge pump 19. .

When the time further elapses, the control section 26 switches the control signal G4 to the Hi signal, and opens the switch 25.
At this time, the switch 24 is kept open.

At this time, the variable frequency divider 14 starts the frequency dividing operation and outputs the feedback signal FV4 to the phase comparator 10. When the time elapses and the reference signal FR4 rises, the phase comparator 10 sets the reference signal FR4 and the feedback signal FV
4 and outputs an error signal ER4 to the low-pass filter 21 via the charge pump 20.

To summarize the above operations, the control unit 26
The frequency dividing operation of each of the variable frequency dividers 11 to 14 is started in accordance with the phase of each of the reference signals FR1 to FR4. Then, the first phase comparator 7 and the second phase comparators 8, 9, and 10 compare the phases of the reference signals FR1 to FR4 and the feedback signals FV1 to FV4, respectively. As a result, the phase comparators 7 to 10 output the error signals ER1 to ER4 to the low-pass filter 21 via the charge pumps 17 to 20, respectively.

The low-pass filter 21 outputs the error signals ER1 to ER1.
In response to ER4, control voltage CV is output to voltage controlled oscillator 15. The voltage control oscillator 15 controls the control voltage CV
Generates an output signal VO. This state is referred to as A1
Shown by dots (see FIG. 3). At this time, the phase difference between the reference signal FR and the feedback signal FV is large.

As described above, the reference oscillator 2 outputs the reference signal FR1 having the reference frequency FR (period TR = 1 / FR).
Occurs. The reference signals FR2, FR3, FR4 are sequentially delayed by 1/4 cycle (TR / 4) from the reference signal FR1 by the delay circuits 3, 4, 5, respectively.

Each of the variable frequency dividers 11, 12, 13,
The start of the frequency division operation of each of the reference signals FR1, FR2, F
The phase is adjusted to the phases of R3 and FR4. Therefore, at the start of the frequency division operation, the signals are sequentially delayed by TR / 4, and the phase comparison timings of the phase comparators 7, 8, 9, 10 are each delayed by approximately TR / 4. It was done.

As described above, by starting the frequency dividing operation of each of the variable frequency dividers 11 to 14 in accordance with the phase of each of the reference signals FR1 to FR4, the phase comparison timing of each of the phase comparators 7 to 10 becomes The intervals are substantially equal, and accurate phase comparison can be performed.

As described above, the reference signals FR1 to FR4 have different phases (for example, π / FR
Phase is shifted by two) and each reference signal F
A phase comparison is performed for each of R1 to FR4. As a result, the phase comparison is performed a plurality of times during one cycle (TR) of the reference signal FR1, and the lock-up time is reduced to about 1/4 of the conventional lock-up time.

When the above-described phase comparison is repeated and time elapses, the phase of the feedback signal FV obtained by dividing the output signal VO approaches the reference signal FR (see point A2 in FIG. 3). If this state is referred to as "not in the locked state", when the locked state is not established, the first phase comparator 7 and the second phase comparators 8, 9, and 10 operate in all four stages, and the charge pumps 17 to
20 to the low-pass filter 21 and the error signal ER1
ER4 is output.

Further, the above-described phase comparison is repeated, and after a lapse of time, the phase difference between the reference signal FR and the feedback signal FV reaches point A3 (see FIG. 3). At this time, as shown in FIG.
The outputs of the second phase comparators 8, 9, and 10 become zero, and the second
Charge pump 1 connected to phase comparators 8, 9, 10
The error signals ER2 to ER4 output from 8 to 20 become zero.

If the point A3 is called "almost locked", only the first phase comparator 7 outputs at this time. As described above, at the points A1 and A2, the first phase comparator 7
The number of output stages of the second phase comparators 8, 9, and 10 is four, but when the point A3 is reached, the number of output stages becomes one (only the first phase comparator 7 outputs).

Further, the above-described phase comparison is repeated, and after a lapse of time, the phase difference between the reference signal FR1 and the feedback signal FV1 reaches the point A4. At this time, the output of the first phase comparator 7 becomes zero (see FIG. 3), and the error signal ER1 output by the charge pump 17 becomes zero. Further, by setting the point A4 smaller than the point A5 at which the PLL device 1 is "locked", the PLL device 1 is maintained in the locked state by the output of the first phase comparator 7.

To summarize the above operation, the size of the dead zone D1 of the first phase comparator 7 and the size of the dead zone D2 of the second phase comparators 8, 9 and 10 are made different. As a result, there is no need to provide external switching means for the phase comparators 7 to 10 (for example, a gate provided at the subsequent stage of the phase comparator, as in the related art).

The reason is that the phase comparison between the first phase comparator 7 and the second phase comparators 8, 9 and 10 is repeated, and when the phase difference between the reference signal FR and the feedback signal FV decreases, the dead zone increases. Phase comparator (for example, the second phase comparator 8,
The output of (9, 10) becomes zero.

As a result, as shown at point A3 in FIG. 3, the number of output stages of the phase comparators 7 to 10 is switched to four. As described above, even if the external switching means is not provided, the number of output stages is automatically switched to one by the characteristics of the second phase comparators 8, 9, and 10 (the dead zone D2 is large).

In FIG. 3, from the point A1 to the point immediately before the point A3, the four-stage phase comparators 7 to 10 are output, and the number of phase comparisons within one cycle of the reference signal is increased (four times the conventional number). , To speed up the start-up (reduce the lock-up time). And
When a substantially locked state (point A3 in FIG. 3) is reached, the phase comparator 7
The number of output stages can be made one so that the outputs of other phase comparators (for example, the second phase comparators 8 to 10) do not disturb the output of the first phase comparator 7. .

[0054]

As described above, according to the first aspect of the present invention, a generating means for generating a plurality of reference signals having different phases, a variable frequency divider for dividing the output of the voltage controlled oscillator and outputting a feedback signal are provided. , A plurality of phase comparators for comparing the phase of each of the reference signals with the feedback signal, and the dead zones of the phase comparators are made different. With this configuration, the phase comparison is performed a plurality of times during one cycle of the reference signal, and the lock time (rise) is shortened. Further, by making the dead zones of a plurality of phase comparators different, it is possible to arbitrarily set the phase difference at which the output voltage of the phase comparator becomes zero.

According to a second aspect of the present invention, the number of output stages of each of the phase comparators is switched by providing different dead zones for the phase comparators without providing external switching means for each of the phase comparators. . As described above, since no external switching means is provided for switching the number of output stages of each phase comparator, a controller for controlling the switching timing is not required, and the cost is reduced. Further, it is possible to prevent the outputs of the phase comparators from interfering with each other due to the shift of the switching timing as in the related art.

According to the third aspect of the present invention, the phase comparator comprises a first phase comparator having a small dead zone and a second phase comparator having a large dead zone. And the second phase comparator outputs, and when the lock state is substantially established, only the first phase comparator outputs. As described above, when the lock state is not established (at the time of rising, etc.), the first phase comparator and the second phase comparator are output, so that the phase comparison is performed a plurality of times during one cycle of the reference signal. Lock time is faster. Further, only the first phase comparator outputs when the lock state is substantially attained, so that it is possible to prevent the output of the second phase comparator from interfering with the output of the first phase comparator. Further, since the phase comparator itself controls the number of output stages, a conventional lock detector and a controller for controlling the number of output stages of the phase comparator are unnecessary.

According to a fourth aspect of the present invention, the second phase comparator includes a first delay circuit to which the reference signal is inputted, and a second delay circuit to which the feedback signal is inputted. With this configuration, the size of the dead zone of the second phase comparator can be easily and accurately obtained (realized).

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL device 1 according to an embodiment of the present invention.

FIG. 2 is a block diagram of second phase comparators 8, 9, and 10 used in the PLL device 1.

FIG. 3 shows phase comparators 7-1 used in the PLL device.
0 is a characteristic diagram of FIG.

[Explanation of symbols]

 6 Generating means 7, 8, 9, 10 Phase comparator 11, 12, 13, 14 Variable frequency divider 15 Voltage controlled oscillator

Continuation of the front page (72) Inventor Masaru Horikoshi 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hisaka Uchiyama 2-5-5-1 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. 5J106 AA04 CC01 CC30 CC38 CC41 CC52 CC58 DD08 DD32 DD34 DD42 DD43 EE08 GG04 HH00 HH10 JJ02 KK03 KK39 LL02

Claims (4)

[Claims] 1. A generator for generating a plurality of reference signals having different phases, a variable frequency divider for dividing the output of a voltage controlled oscillator and outputting a feedback signal, and comparing the phase of each of the reference signals and the feedback signal. A plurality of phase comparators, wherein the dead zones of the phase comparators are made different. 2. The method according to claim 1, wherein the number of output stages of each of the phase comparators is switched by providing different dead zones of the phase comparators without providing external switching means for each of the phase comparators. PLL device. 3. A phase comparator comprising a first phase comparator having a small dead zone and a second phase comparator having a large dead zone, wherein the first phase comparator and the second phase comparator are not in a locked state. 2. The PLL device according to claim 1, wherein when the comparator outputs the signal and the lock state is substantially established, only the first phase comparator outputs the signal. 4. The PL according to claim 3, wherein the second phase comparator includes a first delay circuit to which the reference signal is input, and a second delay circuit to which the feedback signal is input.
L device.