WO2014006654A1

WO2014006654A1 - Semiconductor device

Info

Publication number: WO2014006654A1
Application number: PCT/JP2012/004339
Authority: WO
Inventors: 輝世晴尾崎
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2012-07-04
Filing date: 2012-07-04
Publication date: 2014-01-09

Abstract

A semiconductor device according to an embodiment comprises: a phase comparator which generates phase difference determination signals (UP, DN); control current generation circuits (211-21m) each of which is provided with a current source for generating a first bias current having a predetermined current value, and inputs/outputs a frequency control current generated from the first bias current on the basis of the phase difference determination signals (UP, DN); a loop filter (26) which generates frequency control voltage on the basis of the frequency control current; a voltage control oscillator (27) which controls the frequency of an output signal (S3) according to the frequency control voltage; and a control unit (109) which generates a parallel number switching signal (S1) and a bias current switching signal (S2). Regarding the control current generation circuits (211-21m), the number of control current generation circuits which operate in parallel in response to the parallel number switching signal (S1) is controlled, and the frequency control current inputted/outputted by one control current generation circuit in response to the bias current switching signal (S2) is set to the reciprocal multiple of a parallel number.

Description

Semiconductor device

The present invention relates to a semiconductor device, and can be suitably used for, for example, a semiconductor device having a PLL (Phase Locked Loop) circuit that generates a local signal.

In a semiconductor device, a PLL circuit is used to control the frequency of a signal such as a clock signal or a sine wave signal used internally. This PLL circuit can generate a signal obtained by multiplying the reference signal, and can generate a signal having an arbitrary frequency by controlling the multiplication number. Thus, the signal generated by the PLL circuit is used in demodulation processing and modulation processing on data to be transmitted / received, for example, in a semiconductor device used for communication. Here, with respect to signals used in communication demodulation processing and modulation processing, specifications for phase errors differ depending on communication standards.
Therefore, Patent Document 1 discloses a technique for suppressing the magnitude of the phase error of the clock signal generated by the PLL circuit. In the PLL circuit described in Patent Document 1, the phase comparison between the reference signal and the output signal is performed using clock signals whose phases are different by 180 degrees. As a result, in the PLL circuit described in Patent Document 1, the frequency dividing ratio of the frequency divider provided in the path for feeding back the output signal to the phase comparator is suppressed, and the phase error caused by the frequency divider is suppressed.
In the PLL circuit described in Patent Document 1, in order to operate the charge pump circuit for each of the results of phase comparison at different timings, two charge pump circuits corresponding to each of the phase comparison timings Have In the PLL circuit described in Patent Document 1, the control voltage of the voltage controlled oscillator is generated by the output currents of the two charge pump circuits.

Japanese Patent No. 4236998

However, when the PLL circuit described in Patent Document 1 is used to configure a single semiconductor device corresponding to a plurality of communication standards, it is necessary to configure the PLL circuit in accordance with the communication standard of the strictest specification for phase error. There is. In such a case, in the PLL circuit described in Patent Document 1, it is necessary to increase the number of charge pump circuits that are operated to suppress the phase error. In other words, the PLL circuit described in Patent Document 1 has a problem that the current consumption of the entire PLL circuit becomes unnecessarily large in an operation mode in which communication of a communication standard that allows a large phase error is performed. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, the semiconductor device has a plurality of controls that input and output a frequency control current that controls the magnitude of the frequency control voltage used to control the frequency of the output signal generated by the voltage controlled oscillator. A current generation circuit; In the semiconductor device, the current input / output by one control current generation circuit is set to the inverse number of the parallel number in accordance with the parallel number of the control current generation circuits.

According to one embodiment, the semiconductor device can suppress the current consumption according to the magnitude of the phase error of the output signal of the PLL circuit.

1 is a block diagram of a semiconductor device according to a first embodiment; 1 is a block diagram of a PLL circuit according to a first exemplary embodiment; FIG. 3 is a block diagram of a control current generation circuit according to the first exemplary embodiment. 1 is a circuit diagram of a current switching circuit according to a first embodiment; 1 is a block diagram of a local signal distribution circuit according to a first exemplary embodiment; FIG. 6 is a diagram for explaining an operation of a control current generation circuit that does not include the current switching circuit according to the first embodiment; FIG. 3 is a block diagram of a PLL circuit for explaining an open loop gain of the PLL circuit according to the first exemplary embodiment; FIG. 3 is a diagram for explaining frequency characteristics of the PLL circuit according to the first exemplary embodiment; FIG. 3 is a diagram for explaining the operation of the control current generating circuit according to the first embodiment. It is a figure for demonstrating the specification of the phase error of a communication standard. FIG. 6 is a diagram for explaining a relationship between a consumption current of the control current generation circuit according to the first embodiment and a phase error; FIG. 6 is a diagram for explaining a difference in frequency characteristics of a PLL circuit due to a difference in the number of parallel control current generation circuits according to the first embodiment; FIG. 3 is a block diagram of a PLL circuit according to a second exemplary embodiment. FIG. 6 is a block diagram of a local signal distribution circuit according to a second exemplary embodiment. FIG. 6 is a block diagram of a PLL circuit according to a third exemplary embodiment. FIG. 6 is a block diagram of a control current generation circuit according to a third exemplary embodiment. 10 is a flowchart showing an operation of the semiconductor device according to the fourth embodiment; 10 is a flowchart showing an operation of the semiconductor device according to the fifth embodiment; FIG. 10 is a schematic diagram of a layout of a control current generation circuit according to a sixth embodiment;

Embodiment 1
Hereinafter, embodiments will be described with reference to the drawings. The embodiment described below relates to a semiconductor device including a PLL circuit. Thus, a semiconductor device that performs transmission / reception processing in wireless communication will be described as an example of a semiconductor device including a PLL circuit. A semiconductor device described below corresponds to a plurality of wireless communication schemes (for example, IEEE802.11a / b / n / p). The semiconductor device can appropriately select a wireless communication method to be used from a plurality of wireless communication methods. Note that the configuration described below can be applied not only to wireless communication but also to all semiconductor devices including a PLL circuit.

FIG. 1 shows a block diagram of a semiconductor device 1 according to the first embodiment. As shown in FIG. 1, the semiconductor device 1 has an external terminal TM. The semiconductor device 1 is connected to another semiconductor device or element via the external terminal TM. The semiconductor device 1 includes a reception

front end unit

101a, 101b, 102a, 102b, 103a, 103b, a

reception processing unit

104a, 104b, a transmission filter 105, a transmission front end unit 106, a transmission front end unit 107, a transmission front end unit 108, A baseband processing unit 109, a PLL circuit 10, and a local signal distribution circuit 11 are included.

The semiconductor device 1 shown in FIG. 1 performs multi-input type reception processing. For this reason, the semiconductor device 1 includes a first system (for example, A system) reception system and a second system (for example, B system) reception system. Therefore, in FIG. 1, “a” is added to the end of the code of the block configuring the A-system reception system, and “b” is added to the end of the code of the block configuring the B-system reception system.

The reception front-

end units

101a and 101b are reception front-end units provided corresponding to a communication method (for example, IEEE 802.11p) that performs communication using a 760 MHz band radio signal. The reception

front end units

102a and 102b are reception front end units provided corresponding to a communication method (for example, IEEE802.11b / g / n) that performs communication using a 2.4 GHz band radio signal. The reception front-

end units

103a and 103b are reception front-end units provided corresponding to a wireless system (for example, IEEE802.11a / n / p) that performs communication using a 5.9 GHz band wireless signal.

The reception front end unit receives a local signal having a frequency corresponding to the communication method from the local signal distribution circuit 11. The reception front-end unit generates a baseband signal from a radio signal (RF signal) that is input by modulating the reception signal using a local signal. That is, the reception front end unit generates a baseband signal from the RF signal by performing a modulation process of the direct conversion method.

The

reception processing units

104a and 104b perform amplification processing of the baseband signal and conversion processing (analog / digital conversion processing) of the amplified baseband signal from an analog signal to a digital signal. That is, the

reception processing units

104a and 104b generate data signals RDa and RDb from the baseband signals. Since the baseband signal has the same frequency regardless of which communication method is used, one reception processing unit is provided for a plurality of reception front end units. In the example shown in FIG. 1, one reception processing unit is provided for each of the A system and the B system.

The transmission filter 105 performs a filtering process on the transmission data SD output from the baseband processing circuit 109. The transmission front end unit 106 is a transmission front end unit provided corresponding to a communication method (for example, IEEE802.11p) for performing communication using a 760 MHz band radio signal. The transmission front end unit 107 is a transmission front end unit provided corresponding to a communication method (for example, IEEE802.11b / g / n) that performs communication using a 2.4 GHz band radio signal. The reception front end unit 108 is a transmission front end unit provided corresponding to a wireless system (for example, IEEE802.11a / n / p) that performs communication using a 5.9 GHz band wireless signal.

The transmission front end unit receives a local signal having a frequency corresponding to the communication method from the local signal distribution circuit 11. Then, the transmission front end unit modulates the transmission data SD with the received local signal and outputs it.

The baseband processing circuit 109 performs a decoding process on the reception data RDa and RDb output from the

reception processing units

104a and 104b and outputs them to other circuits such as an application processor. In addition, the baseband processing circuit 109 receives the reception data RDa obtained through the A-system reception system and the reception data RDa obtained through the B-system reception system, which has the higher reception sensitivity. Processing such as selecting received data obtained from the system or generating received data with higher accuracy by combining received data obtained from the two receiving systems is performed. Further, the baseband processing circuit 109 performs transmission processing on the data obtained from the application processor or the like to generate transmission data SD.

The baseband processing circuit 109 functions as a control circuit for the PLL circuit 10. More specifically, the baseband processing circuit 109 generates the parallel number switching signal S1 and the bias current switching signal S2 according to a communication method to be used or a communication situation such as reception intensity. The parallel number switching signal S1 and the bias current switching signal S2 are control signals given to a control current generation circuit described later. The parallel number switching signal S1 is a signal for designating a parallel number indicating the number of control current generating circuits operated in parallel. The bias current switching signal S2 is a signal that designates the inverse of the parallel number as the bias current setting value. The bias current switching signal S2 may specify a bias current setting value so that the bias current decreases as the number of parallel increases.

The PLL circuit 10 receives the reference signal Fref from the oscillator 2 provided outside, and generates an output signal S3 obtained by multiplying the reference signal Fref. The output signal S3 is a signal that is a source of the local signal. The local signal distribution circuit 11 generates a plurality of local signals having a frequency corresponding to each communication method from the output signal S3. The local signal distribution circuit 11 distributes the generated local signal to the corresponding transmission front end unit and transmission front end unit. Details of the PLL circuit 10 and the local signal distribution circuit 11 will be described later.

Subsequently, details of the PLL circuit 10 will be described. FIG. 2 shows a block diagram of the PLL circuit according to the first exemplary embodiment. In the block diagram shown in FIG. 2, the PLL circuit 10 and the control unit 109 are shown. The control unit 109 is the baseband processing circuit of FIG. 1 and outputs a parallel number switching signal S1 and a bias current switching signal S2 related to the PLL circuit 10. The control unit 109 increases the number of parallels specified by the parallel number switching signal S1 as the magnitude of the phase error required in the communication method to be used decreases. Further, the control unit 109 decreases the bias current setting value specified by the bias current switching signal S2 in response to the increase in the number of parallels specified by the parallel number switching signal S1.

As shown in FIG. 2, the PLL circuit 10 includes control current generation circuits 211 to 21m (m is an integer indicating the number of control current generation circuits), a loop filter 26, a voltage control oscillator 27, a prescaler 28, a sigma delta modulator. 29.

Each of the control current generation circuits 211 to 21m includes a current source that generates a first bias current having a predetermined current value, and is generated from the first bias current based on the phase difference determination signals UP and DN. Input / output frequency control current. Further, the control current generation circuits 211 to 21m output a current obtained by adding the currents input / output by the charge pump circuits included therein as a frequency control current to be supplied to the loop filter 26.

The control current generation circuit 211 includes a phase comparator 221, a charge pump circuit 231, a current source 241, and a current switching circuit 251. The control current generation circuits 212 to 21m have circuits corresponding to the phase comparator 221, the charge pump circuit 231, the current source 241, and the current switching circuit 251, respectively. That is, the control current generation circuits 211 to 21m have the same circuit configuration. A plurality of phase comparators are provided corresponding to the control current generating circuits 211 to 21m. In the PLL circuit 10 shown in FIG. 2, the phase comparator is included in the control current generation circuit. However, the phase comparator can be mounted as another circuit block.

The phase comparator 221 outputs phase difference determination signals UP and DN indicating the phase difference between the reference signal Fref and the feedback signal Ffb generated from the output signal S3. The charge pump circuit 231 flows out the frequency control current in response to the phase difference determination signal UP being enabled, and flows in the frequency control current in response to the phase difference determination signal DN being enabled.

The current source 241 generates a first bias current having a predetermined current value. The current switching circuit 251 generates a second bias current obtained by multiplying the first bias current by a reciprocal number of the parallel number based on the bias current switching signal S2. The charge pump circuit 231 inputs / outputs a current corresponding to the second bias current as a frequency control current in accordance with the phase difference determination signals UP and DN.

The loop filter 26 generates a frequency control voltage based on the frequency control current. Note that the total value of the frequency control currents output from the control current generation circuits 211 to 21m is input to the loop filter 26. The voltage controlled oscillator 27 controls the frequency of the output signal S3 according to the frequency control voltage. For example, when the voltage controlled oscillator 27 is composed of an LC type voltage controlled oscillator, the frequency of the output signal S3 is controlled by changing the value of the capacitance by the frequency control voltage. The voltage controlled oscillator 27 outputs the internal oscillation signal Fout. In the example shown in FIG. 2, the internal oscillation signal Fout is output as it is as the output signal S3.

The prescaler 28 is provided between the voltage controlled oscillator 27 and the phase comparators 211 to 21m, and divides the output signal S3 to generate a feedback signal Ffb. The sigma delta modulator 29 generates a frequency division ratio control signal S4 that specifies the frequency division ratio of the prescaler 28. More specifically, the sigma delta modulator 29 fluctuates the frequency division ratio by the sigma delta modulation process, and realizes a frequency division ratio finer than the frequency division ratio obtained from the hardware configuration of the prescaler 28.

Next, a more detailed configuration of the control current generation circuits 211 to 21m will be described. FIG. 3 shows a block diagram of the control current generating circuits 211 to 21m according to the first embodiment. As shown in FIG. 3, the parallel number switching signal S1 is input to the control current generating circuits 211 to 21m. The parallel number switching signal S1 is, for example, a bundle of enable signals corresponding to the control current generating circuits 211 to 21m. The control current generating circuits 211 to 21m operate when the input parallel number switching signal S1 is enabled, and stop when the parallel number switching signal S1 is disabled. For example, the control current generation circuits 211 to 21m operate a circuit such as a current source when the corresponding parallel number switching signal S1 is in the enabled state, and the current when the corresponding parallel number switching signal S1 is in the disabled state. The circuit such as the power source is stopped to reduce the current consumption of the circuit. Here, when the control current generation circuits 211 to 21m are in a stopped state, for example, the generation of the first bias current by the current source is stopped, and the output of the charge pump circuit is set in a high impedance state.

As shown in FIG. 3, the control current generation circuits 211 to 21m have the same circuit configuration. Therefore, in this description, the control current generation circuit 211 will be described as a representative example of the control current generation circuit. As illustrated in FIG. 3, the control current generation circuit 211 includes a current source 241, a current switching circuit 251, a phase comparator 221, and a charge pump circuit 231.

The current source 241 generates a first bias current. The first bias current is a current having a predetermined current value, and is generated by, for example, a band gap current source. In FIG. 3, Ibias indicating the amount of the first bias current is used as the sign of the first bias current.

The current switching circuit 251 generates a second bias current in which the first bias current Ibias is a reciprocal multiple of the parallel number N according to the bias current setting value specified by the bias current switching signal S2. In FIG. 3, Ibias / N indicating the amount of the second bias current is used as the sign of the second bias current.

The phase comparator 221 outputs phase difference determination signals UP and DN indicating the phase difference between the reference signal Fref and the feedback signal Ffb. More specifically, when the phase of the feedback signal Ffb is behind the phase of the reference signal Fref, the phase comparator 221 enables the phase difference determination signal UP (for example, low level), and the phase difference determination signal DN is disabled (for example, high level). On the other hand, when the phase of the feedback signal Ffb is ahead of the phase of the reference signal Fref, the phase comparator 221 disables the phase difference determination signal UP (for example, high level) and sets the phase difference determination signal DN to Enable state (for example, low level).

The charge pump circuit 231 inputs / outputs a current corresponding to the second bias current as a frequency control current in accordance with the phase difference determination signals UP and DN. The PLL circuit 10 gives the loop filter 26 a sum of the frequency control currents output from the charge pump circuits 231 to 23m of the control current generation circuits 211 to 21m. In FIG. 3, the charge pump circuits 231 to 23m each show Icp / N indicating the magnitude of the frequency control current as a sign of the frequency control current. In the present embodiment, the current value Icp indicates the current value of the frequency control current applied to the loop filter 26. In the control current generation circuits 211 to 21m, the second bias current that serves as a reference for the current value Icp is used. Is 1 / N times the magnitude of the current value Ibias of the first bias current. Therefore, the frequency control current output from each of the control current generation circuits 211 to 21m according to the first embodiment is 1 / N times the current value Icp. As shown in FIG. 3, in the PLL circuit 10, the loop filter 26 is supplied with a current obtained by adding the currents output from the N control current generation circuits, that is, a frequency control current with a current value of Icp.

Here, in the PLL circuit 10 according to the first embodiment, the magnitude of the noise component with respect to the carrier component of the frequency control current is reduced by increasing the first bias current by 1 / N times in the current switching circuits 251 to 25m. To do. Therefore, details of the charge pump circuit 231, the current source 241, and the current switching circuit 251 will be described. FIG. 4 shows a detailed circuit diagram of the charge pump circuit 231, the current source 241, and the current switching circuit 251.

In the example shown in FIG. 4, the current source 241 is shown as one circuit symbol. The current source 241 is connected between the power supply terminal VDD and the current switching circuit 251 and outputs a first bias current Ibias.

The current switching circuit 251 includes NMOS transistors MN1 to MN3 and PMOS transistors MP1 and MP2. The sources of the NMOS transistors MN1, MN2, and MN3 are connected to the ground terminal VSS. The gate of the NMOS transistor MN1 is connected to the drain of the NMOS transistor MN1. The first bias current Ibias is input to the drain of the NMOS transistor MN1. The gates of the NMOS transistors MN2 and MN3 are connected in common with the gate of the NMOS transistor MN1. The drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP1. The drain of the NMOS transistor MN3 serves as a first output terminal of the current switching circuit 251 and outputs a current I2. That is, the NMOS transistors MN1, MN2, and MN3 constitute a current mirror circuit.

Here, the NMOS transistors MN1 and MN2 have the same transistor size M0. Therefore, the current amount I1 output from the NMOS transistor MN2 is the same current amount Ibias as the first bias current. The ratio between the transistor size M0 of the NMOS transistor MN1 and the transistor size M1 of the NMOS transistor MN3 is set to 1: 1 / N. 1 / N is the value of the bias current setting value specified by the bias current switching signal S2. That is, the NMOS transistor MN3 has a configuration in which the transistor size can be changed by the bias current switching signal S2. As a result, the amount of current I2 output from the NMOS transistor MN3 is 1 / N times the first bias current.

The transistor size is a value determined by the ratio between the gate width and the gate length of the transistor. In the following description, the transistor size will be described based on the same definition. The NMOS transistor MN3 has a configuration capable of changing the transistor size. Such a configuration can be realized, for example, by switching the number of transistors that operate effectively by switching transistors connected in parallel and switching on and off the switch connected to the drain. In this embodiment, it is assumed that the parallel number of control current generation circuits is switched to 1, 2, 4, and 8. Therefore, for example, when the transistor size M0 of the NMOS transistor MN1 is set to 8 which is the smallest of the common multiples of 1, 2, 4, and 8, the transistor size M1 of the NMOS transistor MN3 is set to 8, 4, 2, 1. If set, the bias current set values of 1, 1/2, 1/4, and 1/8 can be realized.

The sources of the PMOS transistors MP1 and MP2 are connected to the power supply terminal VDD. The gate of the PMOS transistor MP1 is connected to the drain of the PMOS transistor MP1. The current I1 is input to the drain of the PMOS transistor MP1. The gate of the PMOS transistor MP2 is connected in common with the gate of the PMOS transistor MP1. The drain of the PMOS transistor MP2 serves as a second output terminal of the current switching circuit 251 and outputs a current I3. That is, the PMOS transistors MP1 and MP2 constitute a current mirror circuit. The current mirror circuit generates I1 having the same amount of current as the first bias current Ibias.

Here, the ratio between the transistor size M2 of the PMOS transistor MP1 and the transistor size M3 of the PMOS transistor MP2 is set to 1: 1 / N. 1 / N is the value of the bias current setting value specified by the bias current switching signal S2. That is, the PMOS transistor MP2 has a configuration in which the transistor size can be changed by the bias current switching signal S2. As a result, the amount of current I3 output from the PMOS transistor MP2 is 1 / N times the first bias current.

That is, the current switching circuit 251 has a current mirror circuit composed of a first transistor and a second transistor. The first transistor (for example, NMOS transistor MN1, PMOS transistor MP1) has a first terminal having a first bias current Ibias, a control terminal connected to the first terminal, and a first terminal of the first transistor. And a second terminal connected to a first power supply terminal different from the first terminal. The second transistor (eg, NMOS transistor MN3, PMOS transistor MP2) includes a first terminal having a second bias current, a control terminal connected to the control terminal of the first transistor, and a second terminal A second terminal connected to a first power supply terminal different from the first terminal of the transistor; The current mirror circuit switches the size of the second bias current with respect to the first bias current by switching the transistor size of the second transistor according to the bias current switching signal. Note that the first power supply terminal corresponds to the ground terminal VSS when the current mirror circuit is configured by an NMOS transistor, and corresponds to the power supply terminal VDD when the current mirror circuit is configured by a PMOS transistor.

The charge pump circuit 231 includes NMOS transistors MN4 to MN6, PMOS transistors MP3 and MP4, and an inverter. The sources of the NMOS transistors MN4 and MN5 are connected to the ground terminal VSS. The gate of the NMOS transistor MN4 is connected to the drain of the NMOS transistor MN4. The current I3 output from the current switching circuit 251 is input to the drain of the NMOS transistor MN4. The gate of the NMOS transistor MN5 is connected in common with the gate of the NMOS transistor MN4. The drain of the NMOS transistor MN5 is connected to the drain of the PMOS transistor MP4 and constitutes the output terminal of the charge pump circuit 231. The NMOS transistor MN5 outputs a current I5. The NMOS transistor MN6 is connected between the node connecting the gates of the MMOS transistors MN4 and MN5 and the ground terminal VSS. The phase difference determination signal DN is input to the gate of the NMOS transistor MN6 via the inverter.

Here, the relationship between the current amount of the current I5 and the current I3 is determined by the ratio between the transistor size of the NMOS transistor MN4 and the transistor size of the NMOS transistor MN5. For example, if the ratio between the transistor size of the NMOS transistor MN4 and the transistor size of the NMOS transistor MN5 is 1: 1, the current amount of the current I5 and the current I3 are the same. If the ratio between the transistor size of the NMOS transistor MN4 and the transistor size of the NMOS transistor MN5 is 1: 3, the current I5 has a current amount three times that of the current I3. The ratio of the transistor size of the NMOS transistor MN4 and the transistor size of the NMOS transistor MN5 is set in accordance with the ratio of the amount of current between the first bias current and the frequency control current applied to the loop filter 26.

The sources of the PMOS transistors MP3 and MP4 are connected to the power supply terminal VDD. The gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP3. The current I2 output from the current switching circuit 251 is input to the drain of the PMOS transistor MP3. The gate of the PMOS transistor MP4 is connected in common with the gate of the PMOS transistor MP3. The drain of the PMOS transistor MP4 is connected to the drain of the NMOS transistor MN5 and constitutes the output terminal of the charge pump circuit 231. The PMOS transistor MP4 outputs a current I4. The PMOS transistor MP5 is connected between a node connecting the gates of the PMOS transistors MP3 and MP4 and the power supply terminal VDD. The phase difference determination signal UP is input to the gate of the PMOS transistor MP5.

Here, the relationship between the current amount of the current I4 and the current I2 is determined by the ratio between the transistor size of the PMOS transistor MP3 and the transistor size of the PMOS transistor MP4. For example, if the ratio between the transistor size of the PMOS transistor MP3 and the transistor size of the PMOS transistor MP4 is 1: 1, the current amount of the current I4 and the current I2 are the same. If the ratio between the transistor size of the PMOS transistor MP3 and the transistor size of the PMOS transistor MP4 is 1: 3, the current I4 has a current amount three times that of the current I2. The ratio between the transistor size of the PMOS transistor MP3 and the transistor size of the PMOS transistor MP4 is set in accordance with the ratio of the amount of current between the first bias current and the frequency control current applied to the loop filter 26.

Here, the PMOS transistor MP4 and the NMOS transistor MN5 are turned on / off by the PMOS transistor MP5 / NMOS transistor MN6 controlled by the phase difference determination signal UP / phase difference determination signal DN. It is difficult to design (timing design) that achieves both on / off operation and control of the currents I4 and I5 flowing through the PMOS transistor MP4 and the NMOS transistor MN5, and the characteristics are likely to deteriorate. Therefore, the current adjustment is preferably performed by the PMOS transistor MP2 and the NMOS transistor MN3.

Subsequently, the local signal distribution circuit 11 will be described. The local signal distribution circuit 11 generates first and second local signals from the output signal S3, distributes the first local signal to the first transmission / reception circuit, and distributes the second local signal to the second transmission / reception circuit. Distribute. The local signal distribution circuit 11 according to the first exemplary embodiment generates three local signals of local signals f_local1, f_local2, and f_local3. In such a case, one of the two local signals among the plurality of local signals corresponds to the first local signal, and the other corresponds to the second local signal. The first transmission / reception circuit performs data transmission / reception based on a first local signal having a first frequency. For example, the first transmission / reception circuit corresponds to a plurality of different frequency bands (for example, a reception front end unit). And a circuit including a reception front end unit). The second transmission / reception circuit performs data transmission / reception based on a second local signal having a second frequency different from the first frequency. For example, other transmission / reception circuits corresponding to a plurality of different frequency bands are used. It is one of.

Here, a detailed block diagram of the local signal distribution circuit 11 is shown in FIG. As shown in FIG. 5, the local signal distribution circuit 11 includes a 1/16 frequency divider 31,

buffer circuits

32, 34, and 36, a 1/4 frequency divider 33, and a 1/2 frequency divider 35.

The local signal distribution circuit 11 outputs a local signal f_local1 having a frequency of 760 MHz by setting the frequency of the output signal S3 of the PLL circuit 10 to 1/16 by the 1/16 frequency divider 31. The buffer circuit 32 is a drive circuit that distributes the local signal f_local1 to a plurality of circuits. The local signal distribution circuit 11 outputs a local signal f_local2 having a frequency of 2.4 GHz by setting the frequency of the output signal S3 of the PLL circuit 10 to 1/4 by the 1/4 frequency divider 33. The buffer circuit 34 is a drive circuit that distributes the local signal f_local2 to a plurality of circuits. The local signal distribution circuit 11 outputs a local signal f_local3 having a frequency of 4.9 G to 5.9 GHz by halving the frequency of the output signal S3 of the PLL circuit 10 by the ½ divider 35. . The buffer circuit 36 is a drive circuit that distributes the local signal f_local3 to a plurality of circuits.

Subsequently, the operation of the semiconductor device 1 according to the first embodiment will be described. In the semiconductor device 1 according to the first embodiment, when the PLL circuit 10 generates a local signal, the parallel number of the control current generating circuits 211 to 21m and the frequency that one control current generating circuit inputs and outputs according to the communication method. Switches the magnitude of the control current. Thereby, in the semiconductor device 1 according to the first embodiment, power consumption and face error are optimally controlled, and waste of power consumption is reduced.

Therefore, first, a problem that occurs when only the parallel number of control current generation circuits is switched without switching the magnitude of the frequency control current input / output by one control current generation circuit will be described. FIG. 6 is a diagram illustrating the operation of the control current generation circuit that does not include the current switching circuit according to the first embodiment. The control current generation circuit shown in FIG. 6 is a circuit obtained by removing the control current switching circuits 251 to 25m from the control current generation circuit shown in FIG. 3, and each circuit block is the same as the control current generation circuit shown in FIG. The same. However, in order to clarify the difference from the control current generating circuit according to the first embodiment, in FIG. 6, “a” is added to the end of the reference numerals attached to each block.

The control current generation circuits 211a to 21ma shown in FIG. 6 each output a frequency control current. At this time, each frequency control current includes a carrier component and a noise component. Each carrier component has a size of Icp, and each noise component has a size of In_out. The noise component has an uncorrelated phase relationship between the control current generation circuits 211a to 21ma, and the magnitude thereof is represented by an average value of noise.

The frequency control currents output from the control current generation circuits 211a to 21ma are added and given to the loop filter 26. At this time, the added frequency control current carrier component Ica is expressed by the equation (1), and the noise component In is expressed by the equation (2).

That is, if the switching of the magnitude of the frequency control current output by one control current generation circuit is not performed in accordance with the switching of the parallel number of the control current generation circuits 211a to 21ma, the frequency control current that is finally generated Of the carrier component Ica increases in proportion to the parallel number. In this case, the magnitude of the noise component In of the finally generated frequency control current is increased by the square root of the parallel number.

When the magnitude of the frequency control current that is finally generated increases or decreases in response to switching of the parallel number of the control current generation circuit, the open loop gain of the PLL circuit increases or decreases, and the phase error, settling time, reference Affects spurious and phase margin. Therefore, the open loop gain of the PLL circuit will be described.

FIG. 7 is a block diagram of the PLL circuit for explaining the open loop gain of the PLL circuit. This block diagram of the PLL circuit is also applicable to the PLL circuit described in FIG. In the PLL circuit shown in FIG. 7, the transfer function combining the phase comparator and the charge pump circuit is expressed by Icp / 2π, the transfer function of the loop filter is expressed by F (S), and the transfer function of the voltage controlled oscillator VCO. Is represented by 2πKv / S, and the transfer function of the frequency divider is represented by 1 / div. The open loop gain Ao of the PLL circuit is expressed by equation (3).

In Equation (3), Icp is a frequency control current input / output by the charge pump circuit, Kv is a predetermined coefficient in the voltage controlled oscillator VCO, and div is a frequency division ratio of the frequency divider, τ1 is a value expressed by the equation (4), and τ2 is a value expressed by the equation (5).

In the above equations (4) and (5), C1 and C2 are the capacitance values of the capacitors C1 and C2 constituting the loop filter, respectively, and R2 is the resistance value of the resistor R2 of the loop filter.

As can be seen from equations (3) to (5), when the magnitude of the frequency control current input / output from / to the charge pump circuit varies, variables other than the frequency control current do not vary. Ao increases in proportion to the magnitude of the frequency control current. In order to explain the influence when the open loop gain Ao fluctuates, FIG. 8 shows a diagram for explaining the frequency characteristics of the PLL circuit. The graph of the frequency characteristic shown in FIG. 8 is in the vicinity of the frequency band where the open loop gain Ao is 0 dB.

As shown in FIG. 8, the open loop gain Ao increases as the frequency control current Icp increases. As the open loop gain Ao increases, the frequency at which the gain becomes 0 dB also increases. As a result, the amount of spurious suppression is deteriorated and the phase error is increased.

Further, when the open loop gain Ao is increased only by the change of the frequency control current Icp, the pole is obtained from τ ₁ shown in the equation (4) (1 / (2πτ ₁ ) in FIG. 8) and τ _2. The zero point (1 / 2πτ _{2 in} FIG. 8) does not vary. Therefore, the phase with respect to the gain of the PLL circuit does not fluctuate, and the phase margin becomes small. When the phase margin becomes small, there arises a problem that the PLL circuit is not worst locked. That is, there is a problem that adversely affects the settling time.

As described above, when the frequency control current Icp fluctuates, various adverse effects are exerted on various characteristics of the PLL circuit. However, in the semiconductor device 1 according to the first embodiment, the magnitude of the frequency control current output by one control current generation circuit is switched according to the switching of the parallel number of the control current generation circuits 211 to 21m, and the number of parallel Regardless, the final frequency control current is kept constant. Therefore, the above problem does not occur in the PLL circuit 10 of the semiconductor device 1 according to the first embodiment.

Therefore, the operation of the control current generation circuits 211 to 21m of the semiconductor device 1 according to the first embodiment will be described. FIG. 9 is a diagram for explaining the operation of the control current generating circuit according to the first embodiment. The block diagram shown in FIG. 9 is the same as that shown in FIG.

As shown in FIG. 9, in the semiconductor device 1 according to the first embodiment, when the parallel number of control current generation circuits is N (that is, m = N), the frequency control output from one control current generation circuit The magnitude of the carrier component of the current is 1 / N times the final frequency control current Ica. This is because the first bias current Ibias is controlled to 1 / N times in the current switching circuits 251 to 25m. The magnitude of the noise component of the frequency control current output from one control current generation circuit is 1 / N times that when the magnitude of the frequency control current is not 1 / N times. This is because in the current switching circuits 251 to 25m, the noise component also becomes 1 / N when the first bias current Ibias is set to 1 / N times. In the semiconductor device 1 according to the first embodiment, the added frequency control current carrier component Ica is expressed by the equation (6), and the noise component In is expressed by the equation (7). As shown in FIG. 9, in the semiconductor device 1 according to the first embodiment, the frequency control current output by each control current generation circuit is generated based on the first bias current generated from different current sources. The noise component of the frequency control current has an uncorrelated phase relationship between the control current generation circuits. In addition, the noise component shown in FIG. 9 represents an average value of noise magnitude per unit time.

In Equation (7), an equal sign that means that the noise component is substantially equal is used. This is because when the bias current to the charge pump circuit 231 is set to 1 / N by the current switching circuit 252, This is because the flicker noise of the transistors constituting the charge pump circuit 231 may be strictly deviated from 1 / N.

That is, when switching of the magnitude of the frequency control current output from one control current generation circuit is performed in accordance with the switching of the parallel number of the control current generation circuits 211 to 21m, the frequency control current to be finally generated is changed. The size is constant regardless of the parallel number. Further, in this case, the magnitude of the noise component of the frequency control current that is finally generated is one times the square root of the parallel number. That is, the semiconductor device 1 according to the first embodiment is characterized in that the noise component of the frequency control current applied to the loop filter 26 decreases as the parallel number increases.

Subsequently, a phase error and power consumption of the PLL circuit 10 of the semiconductor device 1 according to the first embodiment will be described. First. Since the semiconductor device 1 according to the first embodiment is compatible with a plurality of communication methods, a required phase error will be described for each communication method. FIG. 10 is a diagram for explaining the specifications of the phase error of the communication standard. In FIG. 10, transmission EVM (Error Vector Magnitude) is shown as a standard value related to the phase error. This transmission EVM is a value indicating the ratio between the area of the signal component and the area of the noise component in the spectrum of the signal.

As shown in FIG. 10, in IEEE802.11a, a transmission EVM of −25 dB is determined when the frequency band is 4.9 to 4.8 GHz. In IEEE 802.11a / n, a transmission EVM of −28 dB is determined when the frequency band is 4.9 to 4.8 GHz. In IEEE 802.11b / g, a transmission EVM of −25 dB is determined when the frequency band is 2.4 GHz. In IEEE802.11b / g / n, a transmission EVM of −28 dB is determined when the frequency band is 2.4 GHz. In IEEE802.11p, a transmission EVM of −25 dB is determined when the frequency band is 760 MHz and 5.9 GHz.

Then, in order to satisfy these standards, a value converted to EVM required for the local signal f_local3 at 5.9 GHz is described next to the transmission EVM standard value in FIG. As shown in FIG. 9, in order to satisfy the above-mentioned standard, in IEEE 802.11a, an EVM of −29 dB is obtained for the local signal f_local3. In IEEE802.11a / n, an EVM of −32 dB is obtained for the local signal f_local3. In IEEE 802.11b / g, an EVM of −23 dB is obtained for the local signal f_local3. In IEEE 802.11b / g / n, an EVM of −26 dB is obtained for the local signal f_local3. At 760 MHz of IEEE802.11p, an EVM of -11 dB is obtained for the local signal f_local3. In 5.9 GHz of IEEE802.11p, -32 dB EVM is obtained for the local signal f_local3. This value includes a margin of −4 dB from the original value in consideration of a phase error generated in the local signal distribution circuit 11, a phase error generated in the transmission front end unit, and the like.

The value obtained by converting the EVM required for the local signal f_local3 into a phase error is described next to the EVM of the output signal D3. As shown in FIG. 10, in order to satisfy the above-mentioned standard, in IEEE802.11a, 1.61 deg. An rms phase error is determined in the local signal f_local3. In IEEE 802.11a / n, 1.14 deg. An rms phase error is determined in the local signal f_local3. In IEEE 802.11b / g, 3.22 deg. An rms phase error is determined in the local signal f_local3. In IEEE802.11b / g / n, 2.28 deg. An rms phase error is determined in the local signal f_local3. In IEEE 802.11p at 760 MHz, 12.83 deg. An rms phase error is determined in the local signal f_local3. In IEEE 802.11p 5.9 GHz, 1.61 deg. An rms phase error is determined in the local signal f_local3.

Subsequently, a simulation result when the parallel number of the control current generation circuits is changed in the semiconductor device 1 according to the first embodiment will be described. In this simulation, the relationship between the consumption current of the control current generation circuit and the phase error of the PLL circuit 10 when the local signal f_local3 of 5.9 GHz is generated was obtained. FIG. 11 is a diagram for explaining the relationship between the current consumption of the control current generating circuit according to the first embodiment and the phase error.

As shown in FIG. 11, in the circuit used for the simulation, even if the parallel number is 1, the second strictest standard (IEEE 802.11a, 11p requiring 1.61 deg. Rms) shown in FIG. Can be satisfied. Each time the number of parallel control current generation circuits is increased to 2, 4, and 8, the current consumption increases, but the phase error decreases. This is because when the number of control current generation circuits is increased, the number of control current generation circuits that consume current increases. When the parallel number of control current generation circuits is set to 8, the standard of IEEE 802.11a / n, which is the most severe standard (1.14 deg. Rms), can be satisfied.

Further, the frequency characteristics of the PLL circuit 10 according to the first embodiment will be described. FIG. 12 is a diagram for explaining the difference in the frequency characteristics of the PLL circuit due to the difference in the number of parallel control current generation circuits according to the first embodiment. As shown in FIG. 12, in the PLL circuit 10 according to the first exemplary embodiment, the cutoff frequency does not change even if the parallel number of the control current generating circuits is changed. On the other hand, in the PLL circuit according to the first embodiment, the phase error in the low frequency band is reduced and the gain is reduced by increasing the parallel number of the control current generating circuits.

From the above description, the PLL circuit 10 according to the first embodiment reduces the number of parallel control current generation circuits 211 to 21m when the required phase error is large and increases when the required phase error is small. . Further, the PLL circuit 10 according to the embodiment increases the magnitude of the frequency control current input / output by one control current generation circuit when the number of parallel control current generation circuits 211 to 21m is small, and generates the control current When the number of parallel circuits 211 to 21m is large, the magnitude of the frequency control current input / output by one control current generation circuit is reduced. At this time, in the PLL circuit 10 according to the first exemplary embodiment, when the parallel number of the control current generation circuits 211 to 21m is N and the magnitude of the frequency control current finally applied to the loop filter 26 is Icp, one control is performed. The magnitude of the frequency control current input / output by the current generation circuit 211 is Icp / N.

Thereby, in the PLL circuit 10 according to the first exemplary embodiment, the fluctuation of the frequency control current Icp due to the switching of the parallel number of the control current generating circuits 211 to 21m is suppressed, and the fluctuation of various characteristics of the PLL circuit is suppressed.

In the PLL circuit 10, the control current generating circuits 211 to 21m individually have current sources 241 to 24m, and the first bias current generated by the current sources 241 to 24m is individually 1 / N times (N is parallel). A second bias current is generated. Then, a frequency control current is generated based on the individually generated second bias current, and these are added together to generate a frequency control current Icp to be given to the loop filter 26.

Thus, the magnitude of the noise component In of the frequency control current Icp is set to (1 / √N) * (In_out) (In_out is a noise component included in the frequency control current output by one control current generation circuit). That is, in the PLL circuit according to the first embodiment, the noise component of the frequency control current Icp can be reduced as the number of parallel control current generation circuits increases. In the semiconductor device 1 according to the first embodiment, the phase error of the output signal S3 generated by the PLL circuit 10 is reduced by reducing the noise component of the frequency control current Icp according to the increase in the number of parallel control current generation circuits. Can be controlled to a size satisfying the standard value of the communication system. Further, in the PLL circuit 10 according to the first embodiment, when the phase error required by the communication method to be used is large, while reducing the parallel number of the control current generating circuits 211 to 21m, it is possible to reduce waste of current consumption. The phase error can be made smaller than the required size.

In the PLL circuit 10 according to the first embodiment, each of the control current generation circuits 211 to 21m has a phase comparator. As a result, flicker noise or the like generated due to the phase comparator becomes uncorrelated between the control current generation circuits. Therefore, in the PLL circuit 10 according to the first embodiment, the noise related to the phase comparator can be set to the square root of the parallel number in the finally generated frequency control current.

In the semiconductor device 1 according to the first embodiment, the first bias current Ibias is reciprocal times (1 / N times) the parallel number by the current switching circuits 251 to 25m provided before the charge pump circuits 231 to 23m. ) To generate a second bias current. When the frequency control current output from one control current generation circuit is controlled to 1 / N times in the charge pump circuits 231 to 23m, the noise component included in the frequency control current output from one control current generation circuit is 1 / N. Not N times. However, as in the PLL circuit 10 according to the first embodiment, the noise component included in the frequency control current output by one control current generation circuit is obtained by multiplying the bias current by 1 / N times before the charge pump circuit. Can be reduced to 1 / N times to reduce the noise component. Further, by individually generating a bias current in each of the control current generation circuits 211 to 21m, the phase relationship of noise components included in the frequency control current input / output by each control current generation circuit is made uncorrelated. As a result, the noise component when the currents are added can be reduced to √N times to reduce the noise component.

In addition, the PLL circuit 10 according to the first embodiment includes the prescaler 28 that generates the feedback signal Ffb from the output signal S3. As a result, the PLL circuit 10 can generate the output signal S3 having a frequency higher than that of the reference signal Fref. In the PLL circuit 10, the sigma delta modulator 29 generates a frequency division ratio control signal S 4 for controlling the frequency division ratio of the prescaler 28. Thus, by generating the division ratio control signal S4 using the sigma delta modulator 29, it is possible to set a division ratio with higher resolution than the division ratio determined from the hardware configuration of the prescaler 28. .

In the PLL circuit 10 according to the first embodiment, when the parallel number of the control current generating circuits 211 to 21m is N and the magnitude of the frequency control current finally applied to the loop filter 26 is Icp, one control current Although the magnitude of the frequency control current input / output by the generation circuit 211 is Icp / N, the magnitude of the frequency control current is not necessarily set to Icp / N. When the parallel number of the control current generation circuits 211 to 21m is small, the magnitude of the frequency control current input / output by one control current generation circuit is increased, and when the parallel number of the control current generation circuits 211 to 21m is large, The magnitude of the frequency control current input / output by one control current generation circuit may be reduced.

Embodiment 2
In the second embodiment, a PLL circuit 10a which is another form of the PLL circuit 10 will be described. FIG. 13 shows a block diagram of the PLL circuit according to the second embodiment. In the description of the second embodiment, the components described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

As illustrated in FIG. 13, the PLL circuit 10 a according to the second embodiment includes a ½ frequency divider 41 between the voltage controlled oscillator 27 and the prescaler 28 of the PLL circuit 10. The output of the 1/2 frequency divider 41 is set as an output signal S3.

The 1/2 frequency divider 41 halves the frequency of the internal oscillation signal Fout to generate the output signal S3. That is, in the second embodiment, the output signal S3 has 4.8 GHz to 6.08 GHz which is half the frequency of the internal oscillation signal Fout.

A local signal distribution circuit 11a corresponding to the PLL circuit 10a according to the second embodiment will be described. FIG. 14 is a block diagram of the local signal distribution circuit 11a according to the second embodiment. As shown in FIG. 14, the local signal distribution circuit 11a removes the 1/2 divider 35 of the local signal distribution circuit 11 according to the first embodiment, and the 1/16 divider 31 and the 1/4 divider. 33 is replaced with a 1/8 frequency divider 51 and a 1/2 frequency divider 53, respectively.

From the above description, in the PLL circuit 10a according to the second embodiment, the frequency of the internal oscillation signal Fout output from the voltage controlled oscillator 27 is halved and supplied to the prescaler 28 and the local signal distribution circuit 11a. Thus, the prescaler 28 and the local signal distribution circuit 11a according to the second embodiment can be configured using circuit elements that are slower than the PLL circuit 10 according to the first embodiment. By doing so, the circuit configuration can be further simplified.

Embodiment 3
In the third embodiment, a PLL circuit 10b which is another form of the PLL circuit 10 will be described. FIG. 15 shows a block diagram of the PLL circuit according to the third embodiment. In the description of the third embodiment, the components described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

As shown in FIG. 15, the PLL circuit 10b according to the third embodiment includes control current generation circuits 611 to 61m and a phase comparator 62 instead of the control current generation circuits 211 to 21m. The phase comparator 62 has substantially the same function as the phase comparators 221 to 22m. This phase comparator 62 is commonly used for the control current generation circuits 611 to 61m. That is, the phase comparator 62 provides one phase difference determination signal UP, DN to the control current generation circuits 611 to 61m.

The control current generation circuits 611 to 61m are obtained by removing the phase comparators 221 to 22m from the control current generation circuits 211 to 21m. In the third embodiment, the control current generation circuits 611 to 61m include charge pump circuits 631 to 63m, current sources 641 to 64m, and current switching circuits 651 to 65m.

Here, the charge pump circuits 631 to 63m are the same circuits as the charge pump circuits 231 to 23m, the current sources 641 to 64m are the same circuits as the current sources 241 to 24m, and the current switching circuits 651 to 65m This is the same circuit as the switching circuits 251 to 25m.

Subsequently, details of the control current generation circuits 611 to 61m will be described. FIG. 16 shows a detailed block diagram of the control current generation circuits 611 to 61m. As shown in FIG. 16, the control current generating circuits 611 to 61m according to the third embodiment receive the phase difference determination signals UP and DN from the phase comparator 62 and operate the charge pump circuits 631 to 63m. The other configurations of the control current generation circuits 611 to 61m are the same as those of the control current generation circuits 211 to 21m, and thus description thereof is omitted here.

From the above description, in the PLL circuit 10b according to the third embodiment, a plurality of control current generation circuits are operated by the phase difference determination signals UP and DN generated by one phase comparator. Thereby, the PLL circuit 10b according to the third embodiment can reduce the circuit area related to the phase comparator. Further, the PLL circuit 10b according to the third embodiment can reduce the power consumption compared to the PLL circuit 10 according to the first embodiment by using one phase comparator.

Embodiment 4
In the fourth embodiment, a method for determining the parallel number specified by the parallel number switching signal S1 and the bias current setting value specified by the bias current switching signal S2 in the semiconductor device 1 according to the first embodiment will be described.

FIG. 17 is a flowchart showing the operation of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 17, the semiconductor device 1 first sets a communication standard to be used before starting communication (step S10). Next, the semiconductor device 1 selects a parallel number corresponding to the communication standard from the initial setting values prepared in advance (step S11). Then, the semiconductor device 1 outputs a parallel number switching signal S1 that designates the selected parallel number and a bias current switching signal S2 that indicates a bias current setting value indicating the inverse of the selected parallel number. Thereafter, the semiconductor device 1 starts communication by operating the control current generating circuits 211 to 21m in accordance with the selected parallel number.

Subsequently, the semiconductor device 1 determines whether the received radio wave level is within a preset reference value range by using the PGA code (step S12). More specifically, the baseband processing unit 109 determines the received radio wave level. When the baseband processing unit 109 determines that the received radio wave level exceeds the range determined by the preset minimum reception sensitivity level and strong input level (NO branch of step S12), the semiconductor device 1 ends the parallel number adjustment process. This is because communication is not possible in such a case. On the other hand, when the baseband processing unit 109 determines that the received radio wave level is within a range determined by the preset minimum reception sensitivity level and strong input level (YES branch of step S12), the semiconductor device 1 Performs the adjustment process of the parallel number.

In the parallel number adjustment process, first, the baseband processing unit 109 determines whether the communication speed is equal to or higher than a reference value (step S13). More specifically, the baseband processing unit 109 determines whether the decoding process is performed by OFDM (OrthogonalgonFrequency Division Multiplexing). In step S13, when it is determined that the communication speed is less than the reference value because the decoding process is performed by BPSK (Binary Phase Shift Shift Keying) or the like (NO branch in step S13), the parallel number is reduced by one. The bias current set value is decreased by one step (step S14). And the semiconductor device 1 repeats the process of step S14 and step S13 until the communication speed becomes sufficient speed in step S13. In step S13, the semiconductor device 1 ends the parallel number adjustment process in response to the switching of the decoding process to the process based on OFDM (YES in step S13).

That is, the control unit (for example, the baseband processing unit 109) sets the initial number of the parallel number and the bias current setting value according to the communication standard to be used, and the communication speed of communication performed based on the initial value is a reference. If it is less than the value, the parallel number switching signal S1 that specifies a new parallel number that is increased from the current parallel number, and a bias current that specifies a new bias current setting value that is a smaller current bias current setting value A switching signal S2 is generated.

From the above description, by performing the parallel number adjustment processing according to the fourth embodiment, the semiconductor device 1 can improve the phase error and prevent the communication speed from being lowered due to noise. Further, when the communication speed is sufficient, the semiconductor device 1 according to the fourth embodiment can prevent an unnecessary increase in power consumption without increasing the parallel number.

Note that the processes in steps S11 and S12 in FIG. 17 are also performed in the semiconductor device 1 according to the first embodiment.

Embodiment 5
In the fifth embodiment, a modification of the method for determining the parallel number specified by the parallel number switching signal S1 and the bias current setting value specified by the bias current switching signal S2 in the semiconductor device 1 according to the fourth embodiment will be described.

FIG. 18 is a flowchart showing the operation of the semiconductor device 1 according to the fifth embodiment. As shown in FIG. 18, the parallel number adjustment procedure according to the fifth embodiment is performed after step S13 of FIG. In the fifth embodiment, the communication speed is determined in step S13 based on whether or not decoding processing using 64QAM (64 Quadrature Amplitude Modulation) is performed. If it is determined in step S13 that the communication speed is sufficient, the parallel number is decreased by one step and the bias current set value is increased by one step (step S21).

Subsequently, in the fifth embodiment, the baseband processing unit 109 determines whether or not the communication speed satisfies the reference value (step S22). More specifically, the baseband processing unit 109 determines whether or not demodulation processing is performed by 64QAM even in a smaller parallel number than in the determination processing in step S13. If it is determined in step S22 that the communication speed is sufficient (YES in step S22), the baseband processing unit 109 decreases the parallel number by one step and increases the bias current setting value by one step. (Step S23). Thereafter, the semiconductor device 1 repeats the processes in steps S23 and S22 until it is determined in step S22 that the communication speed cannot be secured sufficiently. Then, in step S22, the semiconductor device 1 performs the process of step S24 when it is determined that the communication speed is insufficient. In step S24, the parallel number is increased by one step, and the bias current set value is decreased by one step. As a result, the semiconductor device 1 can operate with a minimum number of parallel processes that can satisfy the communication speed.

That is, the control unit (for example, the baseband processing unit 109) performs the parallel number reduction process when the communication speed of communication performed based on the current parallel number and the bias current setting value is equal to or higher than the reference value. The process of increasing the bias current set value is repeated until the communication speed becomes less than the reference value. Then, the baseband processing unit 109 has a new parallel number that is increased by one when the communication speed is less than the reference value, a new bias current setting value that is decreased by one, and a bias current setting value that is decreased by one. Is determined as the final value.

From the above description, by performing the parallel number adjustment processing according to the fifth embodiment, the semiconductor device 1 can set the minimum parallel number that can ensure the communication speed. As a result, the semiconductor device 1 can operate with only power consumption by a minimum circuit capable of ensuring a communication speed.

Embodiment 6
In the sixth embodiment, the layout of the control current generation circuits 211 to 21m will be described. FIG. 19 shows a schematic diagram of the layout of the control current generation circuit. In the example shown in FIG. 19, m = 4.

The control current generation circuits 211 to 21m need to supply the reference signal Fref and the feedback signal Ffb to the phase comparators 211 to 21m so that the delay times are equal among the plurality of phase comparators. Therefore, as shown in FIG. 19, the reference signal Fref and the feedback signal Ffb input to the plurality of phase comparators have equal-length clock wirings in which the distances from the signal sources of the respective signals to the plurality of phase comparators are equal. Is input via. For example, the length of the clock wiring from the point where the clock wiring of the reference signal Fref and the feedback signal Ffb branches to the gate electrode of the transistor that constitutes the phase comparator to which the reference signal Fref and the feedback signal Ffb are input is each path. To be equal. At this time, crosstalk between signals is prevented by shortening the distance in which the equal length clock wiring for transmitting the reference signal Fref and the equal length clock wiring for transmitting the feedback signal Ffb run in parallel. When such wiring is used, a large area is required for a region where the equal-length clock wiring is arranged. Therefore, it is preferable to arrange a current source in this region.

Thus, the layout area can be reduced by arranging the current source in the region where the equal-length clock wiring is arranged.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2

External signal source

10, 10a, 10b PLL circuit 11 Local signal distribution circuit 211-21m Control current generation circuit 221-22m Phase comparator 231-23m Charge pump circuit 241-24m Current source 251-25m Current switching circuit 26 Loop filter 27 Voltage controlled oscillator 28 Prescaler 29 Sigma delta modulator 31 1/16

divider

32, 34, 36 Buffer circuit 33 1/4

divider

35, 41, 53 1/2 divider 51 1/8 Peripherals 611 to 61m Control current generation circuit 62 Phase comparators 631 to 63m Charge pump circuit 641 to 64m Current source 251 to 25m Current switching circuit 101a to 103a, 101b to 103b Reception

front end unit

104a, 104b Reception processing unit 105

Transmission filter

106, 107, 108 Transmission front end unit 109 Baseband processing unit S1 Parallel number switching signal S2 Bias current switching signal S3 Output signal S4 Frequency division ratio control signal Fout Internal oscillation signal Fref Reference signal Ffb Feedback signal

Claims

A phase comparator that outputs a phase difference determination signal indicating a phase difference between the reference signal and the feedback signal generated from the output signal;
Each includes a current source that generates a first bias current having a predetermined current value, and inputs and outputs a frequency control current generated from the first bias current based on the phase difference determination signal. A control current generation circuit;
A loop filter that generates a frequency control voltage based on the frequency control current;
A voltage controlled oscillator that controls the frequency of the output signal according to the frequency control voltage;
A parallel number switching signal for designating a parallel number indicating the number of the control current generating circuits to be operated in parallel; and a bias current switching signal for designating a decrease in a bias current value in accordance with an increase in the parallel number. A control unit for generating,
In the plurality of control current generation circuits, the number of the control current generation circuits operating in parallel according to the parallel number switching signal is controlled, and one control current generation circuit inputs / outputs according to the bias current switching signal A semiconductor device in which the frequency control current is set to a reciprocal number times the parallel number.
2. The semiconductor device according to claim 1, wherein the bias current switching signal specifies an inverse of the parallel number as a bias current setting value.
The plurality of control current generation circuits are respectively
The current source;
A current switching circuit for generating a second bias current obtained by multiplying the first bias current by a reciprocal of the parallel number based on the bias current switching signal;
The semiconductor device according to claim 2, further comprising: a charge pump circuit that inputs and outputs a current corresponding to the second bias current as the frequency control current in accordance with the phase difference determination signal.
The current switching circuit is
A first transistor having a first terminal to which the first bias current is input, a control terminal connected to the first terminal, and a second terminal connected to a first power supply terminal; ,
A first terminal that outputs the second bias current; a control terminal connected to the control terminal of the first transistor; and a second terminal connected to the first power supply terminal. Two transistors,
A current mirror circuit comprising:
The current mirror circuit switches the size of the second bias current with respect to the first bias current by switching a transistor size of the second transistor according to the bias current switching signal. Semiconductor device.
4. The semiconductor device according to claim 3, wherein the plurality of control current generation circuits output a current obtained by adding the currents input / output by the charge pump circuit included therein as the frequency control current.
3. The semiconductor device according to claim 2, wherein a plurality of the phase comparators are provided corresponding to the plurality of control current generation circuits.
The reference signal and the feedback signal input to a plurality of the phase comparators are input via equal-length clock wirings in which distances from the signal sources of the respective signals to the plurality of phase comparators are equal. 6. The semiconductor device according to 6.
The semiconductor device according to claim 7, wherein the current source is arranged in a region where the equal-length clock wiring is arranged.
3. The semiconductor device according to claim 2, wherein the parallel number increases as a phase error required for the output signal decreases.
3. The semiconductor device according to claim 2, further comprising a prescaler that is provided between the voltage controlled oscillator and the phase comparator and generates the feedback signal by dividing the output signal.
The semiconductor device according to claim 10, further comprising a sigma delta modulator that generates a division ratio control signal that specifies a division ratio of the prescaler.
11. The semiconductor device according to claim 10, further comprising a frequency divider that is provided between the prescaler and the voltage controlled oscillator and generates a frequency-divided signal obtained by frequency-dividing the output signal.
A first transmission / reception circuit for transmitting / receiving data based on a first local signal having a first frequency;
A second transmission / reception circuit for transmitting / receiving the data based on a second local signal having a second frequency different from the first frequency;
The first and second local signals are generated from the output signal, the first local signal is distributed to the first transmission / reception circuit, and the second local signal is distributed to the second transmission / reception circuit. The semiconductor device according to claim 2, further comprising a local signal distribution circuit.
The control unit sets an initial value of the parallel number and the bias current setting value according to a communication standard to be used, and when a communication speed of communication performed based on the initial value is less than a reference value The parallel number switching signal that specifies the new parallel number that has increased the current parallel number, and the bias current switching signal that specifies the new bias current setting value that has decreased the current bias current setting value. The semiconductor device according to claim 2 to be generated.
The controller is
When the communication speed of communication performed based on the current parallel number and the bias current setting value is equal to or higher than a reference value, the reduction process of the parallel number, the increase process of the bias current setting value, and the communication speed are Repeat until below the reference value,
A new parallel number obtained by increasing the parallel number by one when the communication speed becomes less than the reference value and a new bias current set value obtained by reducing the bias current set value by one are final values. The semiconductor device according to claim 14, which is determined as: