JPH0878822A - Semiconductor-mounted circuit device - Google Patents
Semiconductor-mounted circuit deviceInfo
- Publication number
- JPH0878822A JPH0878822A JP23036894A JP23036894A JPH0878822A JP H0878822 A JPH0878822 A JP H0878822A JP 23036894 A JP23036894 A JP 23036894A JP 23036894 A JP23036894 A JP 23036894A JP H0878822 A JPH0878822 A JP H0878822A
- Authority
- JP
- Japan
- Prior art keywords
- base member
- semiconductor chip
- semiconductor
- plating layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップを回路基
板に実装した回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit device having a semiconductor chip mounted on a circuit board.
【０００２】[0002]
【従来の技術】従来より、ＩＣやＬＳＩなどの半導体チ
ップをセラミック基板等に実装する方法として、フェイ
スダウンボンディング法と称される方法が用いられてき
た。かかる方法は、半導体チップと回路基板とに半田ボ
ールを形成し、両者を位置合わせした後に半田を溶融さ
せて接合（リフローソルダリング）するものである。こ
のフェイスダウンボンディング法は、半田ボールをマト
リクス状に配置して端子密度を上げることで、集積度が
高く端子数の多い半導体チップに対応できるという利点
を有している。2. Description of the Related Art Conventionally, a method called face-down bonding has been used as a method for mounting a semiconductor chip such as an IC or LSI on a ceramic substrate or the like. In such a method, solder balls are formed on a semiconductor chip and a circuit board, and after aligning them, the solder is melted and joined (reflow soldering). This face-down bonding method has an advantage that it can be applied to a semiconductor chip having a high degree of integration and a large number of terminals by arranging solder balls in a matrix to increase the terminal density.
【０００３】[0003]
【発明が解決しようとする課題】しかし、このような実
装方法は高価な半田ボールを用いる必要があり、さらに
その半田ボールを半導体チップと回路基板とに一個づつ
マウントする必要があるために非常に手間がかかり、そ
の結果、回路装置が高価なものとなってしまうという問
題を有していた。However, such a mounting method requires the use of expensive solder balls, and the solder balls need to be mounted one by one on the semiconductor chip and the circuit board. There is a problem that the circuit device becomes expensive as a result of time and effort.
【０００４】[0004]
【課題を解決するための手段】本発明は、前記課題を解
決するため、半導体素子をベース部材上に装着した半導
体チップを、前記半導体チップと導通する配線パターン
が施された回路基板に接合してなる半導体実装回路装置
において、前記ベース部材がメッキ適合樹脂からなり、
前記ベース部材が前記回路基板と接合する接合面側から
前記半導体チップが装着された半導体素子側に貫通する
スルーホールと、前記接合面側に前記ベース部材と一体
成型された凸部と、この凸部と前記半導体素子側とを前
記スルーホールを介して導通する導体メッキ層と、前記
凸部の前記導体メッキ層に積層形成された半田メッキ層
と、を有するものである。In order to solve the above-mentioned problems, the present invention joins a semiconductor chip having a semiconductor element mounted on a base member to a circuit board provided with a wiring pattern for conducting the semiconductor chip. In the semiconductor mounted circuit device, the base member is made of a plating compatible resin,
Through holes penetrating from the joint surface side where the base member is joined to the circuit board to the semiconductor element side where the semiconductor chip is mounted, a convex portion integrally molded with the base member on the joint surface side, and the convex portion And a solder plating layer laminated on the conductor plating layer of the convex portion, and a conductor plating layer for electrically connecting the portion and the semiconductor element side through the through hole.
【０００５】[0005]
【作用】半導体チップと回路基板との接合に高価な半田
ボールを用いる必要がなく、半導体チップの導体メッキ
層及び半田メッキ層をメッキ法にて形成するために手間
がかからず、半導体チップを回路基板に接合することが
でき、安価な半導体実装回路装置を提供することができ
る。そして、半田ボールを用いずに、従来のフェイスダ
ウンボンディング法と同様な利点を得ることができる。It is not necessary to use expensive solder balls for joining the semiconductor chip and the circuit board, and it does not take time and effort to form the conductor plating layer and the solder plating layer of the semiconductor chip by the plating method. An inexpensive semiconductor mounted circuit device that can be bonded to a circuit board can be provided. Then, the same advantages as the conventional face-down bonding method can be obtained without using the solder balls.
【０００６】[0006]
【実施例】以下、図面を用いて本発明の一実施例を説明
する。図１乃至図３は、本発明にかかる一実施例の断面
図である。An embodiment of the present invention will be described below with reference to the drawings. 1 to 3 are sectional views of an embodiment according to the present invention.
【０００７】１は半導体チップであって、ＩＣ，ＬＳＩ
等の半導体素子２が、メッキ適合樹脂からなるベース部
材３の半導体素子側ａに装着され、半導体素子２は半導
体素子２から引き出されたボンディングワイヤ４と共
に、例えばシリコンゲルからなる封止剤５によって封止
されている。６はベース部材３の接合面側ｂにベース部
材３と一体成型された半球状の凸部であり、図２に示す
ように、凸部６は半導体チップ１の接合面側ｂに８行８
列のマトリクス状に配設されている。７はベース部材３
の接合面側ｂから半導体素子側ａに貫通するスルーホー
ルである。８はスルーホール７内面を介して接合面側ｂ
の凸部６と半導体素子側ａを導通させるように、メッキ
法にて形成される例えば銅からなる導体メッキ層であ
る。この導体メッキ層８は半導体素子側ａでボンディン
グワイヤ４と接続されており、半導体素子２はボンディ
ングワイヤ４と導体メッキ層８とによって、ベース部材
３の接合面側ｂと導通されている。Reference numeral 1 denotes a semiconductor chip, which is an IC or LSI
Is mounted on the semiconductor element side a of the base member 3 made of a plating compatible resin, and the semiconductor element 2 is bonded together with the bonding wire 4 pulled out from the semiconductor element 2 by a sealant 5 made of, for example, silicon gel. It is sealed. Reference numeral 6 denotes a hemispherical convex portion integrally molded with the base member 3 on the joint surface side b of the base member 3. As shown in FIG. 2, the convex portion 6 is 8 rows 8 on the joint surface side b of the semiconductor chip 1.
They are arranged in a matrix of rows. 7 is a base member 3
Is a through hole penetrating from the bonding surface side b to the semiconductor element side a. 8 is a joint surface side b through the inner surface of the through hole 7.
Is a conductor plating layer made of, for example, copper and formed by a plating method so as to electrically connect the convex portion 6 and the semiconductor element side a. The conductor plating layer 8 is connected to the bonding wire 4 on the semiconductor element side a, and the semiconductor element 2 is electrically connected to the bonding surface side b of the base member 3 by the bonding wire 4 and the conductor plating layer 8.
【０００８】９はベース部材３の凸部６にメッキ法にて
形成された半田メッキ層であり、半田メッキ層９は導体
メッキ層８に積層形成されている。なお、導体メッキ層
８と半田メッキ層９との間にニッケルメッキ層（図示し
ない）を設ければ、半田メッキ層９の付着が一層良好と
なる。A solder plating layer 9 is formed on the convex portion 6 of the base member 3 by a plating method, and the solder plating layer 9 is laminated on the conductor plating layer 8. If a nickel plating layer (not shown) is provided between the conductor plating layer 8 and the solder plating layer 9, the adhesion of the solder plating layer 9 is further improved.
【０００９】10は回路基板であって、回路基板10には半
導体チップ１と導通される配線パターン11が施されてい
る。半導体チップ１は回路基板10に位置合わせされた後
に、凸部６の半田メッキ層９を溶融して配線パターン11
と導通され、溶融した半田メッキ層９の半田が硬化する
ことにより、半導体チップ１と回路基板10とが接合され
る。A circuit board 10 is provided with a wiring pattern 11 which is electrically connected to the semiconductor chip 1. After the semiconductor chip 1 is aligned with the circuit board 10, the solder plating layer 9 of the protrusion 6 is melted to form the wiring pattern 11.
The semiconductor chip 1 and the circuit board 10 are bonded to each other by the conduction of the solder and the hardening of the molten solder of the solder plating layer 9.
【００１０】上述したように、半導体チップ１のベース
部材３に樹脂材料を用いているために、ベース部材３の
凸部６を一体に形成することができると共に、さらにメ
ッキ適合樹脂とすることで、ベース部材３の接合面側ｂ
にマトリクス状に多数配設された凸部６にメッキ法にて
半田メッキ層９を設けることができるのである。即ち、
従来例で述べたような半田ボールを用いる場合には、半
導体チップ側だけでも64個（８行８列）の半田ボールを
マウントする必要があるが、本発明によれば凸部６の半
田メッキ層９は１回のメッキ工程によって形成できる。As described above, since the resin material is used for the base member 3 of the semiconductor chip 1, the convex portion 6 of the base member 3 can be integrally formed, and by using the plating compatible resin. , The joint surface side b of the base member 3
It is possible to provide the solder plating layer 9 on the convex portions 6 arranged in a matrix form by a plating method. That is,
In the case of using the solder balls as described in the conventional example, it is necessary to mount 64 (8 rows and 8 columns) solder balls only on the semiconductor chip side. Layer 9 can be formed by a single plating process.
【００１１】なお、ベース部材３に用いるメッキ適合樹
脂は、微細な凸部６を形成するのに好適な溶融粘度の低
い材料が適当であり、例えばポリプラスチックス（株）
の「ベクトラＣ８１０（商品名）」が適している。It is to be noted that the plating compatible resin used for the base member 3 is suitably a material having a low melt viscosity suitable for forming the fine protrusions 6, for example, Polyplastics Co., Ltd.
“Vectra C810 (trade name)” is suitable.
【００１２】また、ベース部材３の凸部６は上述したよ
うな半球状に限らず、比較的自由に設計できるものであ
り、例えば図４に示すように、台形形状に形成すること
もできる。Further, the convex portion 6 of the base member 3 is not limited to the above-mentioned hemispherical shape and can be designed relatively freely, and can be formed in a trapezoidal shape as shown in FIG. 4, for example.
【００１３】[0013]
【発明の効果】本発明は、前記課題を解決するため、半
導体素子をベース部材上に装着した半導体チップを、前
記半導体チップと導通する配線パターンが施された回路
基板に接合してなる半導体実装回路装置において、前記
ベース部材がメッキ適合樹脂からなり、前記ベース部材
が前記回路基板と接合する接合面側から前記半導体チッ
プが装着された半導体素子側に貫通するスルーホール
と、前記接合面側に前記ベース部材と一体成型された凸
部と、この凸部と前記半導体素子側とを前記スルーホー
ルを介して導通する導体メッキ層と、前記凸部の前記導
体メッキ層に積層形成された半田メッキ層と、を有する
ものであり、半導体チップと回路基板との接合に高価な
半田ボールを用いる必要がなく、半導体チップの導体メ
ッキ層及び半田メッキ層をメッキ法にて形成するために
手間がかからず、半導体チップを回路基板に接合するこ
とができ、安価な半導体実装回路装置を提供することが
できる。また、凸部をマトリクス状に配置して端子密度
を上げることで、集積度が高く端子数の多い半導体チッ
プに対応できるという従来のフェイスダウンボンディン
グ法と同等な利点を得ることができる。In order to solve the above-mentioned problems, the present invention is a semiconductor mounting in which a semiconductor chip in which a semiconductor element is mounted on a base member is joined to a circuit board provided with a wiring pattern for conducting the semiconductor chip. In the circuit device, the base member is made of a plating compatible resin, and a through hole penetrating from the joint surface side where the base member is joined to the circuit board to the semiconductor element side where the semiconductor chip is mounted, and the joint surface side. A convex portion integrally molded with the base member, a conductor plating layer for electrically connecting the convex portion and the semiconductor element side through the through hole, and solder plating laminated on the conductor plating layer of the convex portion Since it is not necessary to use expensive solder balls for joining the semiconductor chip and the circuit board, the conductor plating layer and the solder plating layer of the semiconductor chip are included. Takes the hassle to form the layer by a plating method, it is possible to bond the semiconductor chip to the circuit board, it is possible to provide an inexpensive semiconductor mounting circuit device. Further, by arranging the convex portions in a matrix to increase the terminal density, it is possible to obtain the same advantage as that of the conventional face-down bonding method that can be applied to a semiconductor chip having a high degree of integration and a large number of terminals.
【図１】本発明の実施例にかかる断面図。FIG. 1 is a sectional view according to an embodiment of the present invention.
【図２】同上実施例の半導体チップの下面図。FIG. 2 is a bottom view of the semiconductor chip according to the embodiment.
【図３】同上実施例の要部拡大図。FIG. 3 is an enlarged view of a main part of the embodiment.
【図４】本発明の他の実施例にかかる要部拡大図。FIG. 4 is an enlarged view of a main part according to another embodiment of the present invention.
１ 半導体チップ ２ 半導体素子 ３ ベース部材 ６ 凸部 ７ スルーホール ８ 導体メッキ層 ９ 半田メッキ層 10 回路基板 11 配線パターン ａ 半導体チップ側 ｂ 接合面側 1 Semiconductor Chip 2 Semiconductor Element 3 Base Member 6 Projection 7 Through Hole 8 Conductor Plating Layer 9 Solder Plating Layer 10 Circuit Board 11 Wiring Pattern a Semiconductor Chip Side b Bonding Side
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 1/18 Ｊ 8718−4Ｅ Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H05K 1/18 J 8718-4E
Claims (1)
導体チップを、前記半導体チップと導通する配線パター
ンが施された回路基板に接合してなる半導体実装回路装
置において、前記ベース部材がメッキ適合樹脂からな
り、前記ベース部材が前記回路基板と接合する接合面側
から前記半導体チップが装着された半導体素子側に貫通
するスルーホールと、前記接合面側に前記ベース部材と
一体成型された凸部と、この凸部と前記半導体素子側と
を前記スルーホールを介して導通する導体メッキ層と、
前記凸部の前記導体メッキ層に積層形成された半田メッ
キ層と、を有することを特徴とする半導体実装回路装
置。1. A semiconductor mounting circuit device comprising a semiconductor chip having a semiconductor element mounted on a base member, and a circuit board provided with a wiring pattern for conducting the semiconductor chip, wherein the base member is a plating compatible resin. And a through hole penetrating from the joint surface side where the base member is joined to the circuit board to the semiconductor element side where the semiconductor chip is mounted, and a convex portion integrally molded with the base member on the joint surface side. A conductor plating layer for electrically connecting the convex portion and the semiconductor element side through the through hole,
And a solder plating layer laminated on the conductor plating layer of the convex portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23036894A JPH0878822A (en) | 1994-08-31 | 1994-08-31 | Semiconductor-mounted circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23036894A JPH0878822A (en) | 1994-08-31 | 1994-08-31 | Semiconductor-mounted circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0878822A true JPH0878822A (en) | 1996-03-22 |
Family
ID=16906768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23036894A Pending JPH0878822A (en) | 1994-08-31 | 1994-08-31 | Semiconductor-mounted circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0878822A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196860A (en) * | 2004-12-16 | 2006-07-27 | Shinko Electric Ind Co Ltd | Semiconductor package and method of fabricating it |
-
1994
- 1994-08-31 JP JP23036894A patent/JPH0878822A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196860A (en) * | 2004-12-16 | 2006-07-27 | Shinko Electric Ind Co Ltd | Semiconductor package and method of fabricating it |
| US8530351B2 (en) | 2004-12-16 | 2013-09-10 | Shinko Electric Industries Co., Ltd. | Semiconductor package and fabrication method |
| TWI471956B (en) * | 2004-12-16 | 2015-02-01 | Shinko Electric Ind Co | Semiconductor package and fabrication method |
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