JPH09148371A - Structure of semiconductor module and mounting method thereof - Google Patents
Structure of semiconductor module and mounting method thereofInfo
- Publication number
- JPH09148371A JPH09148371A JP32233895A JP32233895A JPH09148371A JP H09148371 A JPH09148371 A JP H09148371A JP 32233895 A JP32233895 A JP 32233895A JP 32233895 A JP32233895 A JP 32233895A JP H09148371 A JPH09148371 A JP H09148371A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor module
- printed wiring
- wiring board
- semiconductor
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体デバイスに関
し、殊に半導体チップを搭載しながらも小型化、薄型化
が可能な半導体モジュールの構造とその取り付け方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a semiconductor module which can be miniaturized and thinned while mounting a semiconductor chip and a mounting method thereof.
【０００２】[0002]
【従来の技術】従来の半導体モジュールとしては、例え
ば図８に示した如き構造を有したものが一般的に用いら
れている。同図において符号１は半導体チップであっ
て、接着剤２によってケース基板３にその底面が固定さ
れている。前記ケース基板３の対向し合う端縁には夫々
上面、側面、下面にかけてコ字状に外部接続用の外部端
子（導電パターン）４、５が形成されており、各外部端
子４、５は前記半導体チップ１の上面の端子（図示せ
ず）に対してワイヤ６、７によってそれぞれ電気的に接
続されている。さらにケース基板３の上面周縁部には封
止用の金属から成る環状の枠体８が一体形成されてお
り、ケース基板３上面および枠体８によって形成される
空間に樹脂９を充填している。なお、図８において点線
で示したのはケースであり、絶縁基板１２上をケースに
より封止した場合にはこのような状態となる。このよう
な構造の半導体モジュールでは、半導体チップ１の上面
の図示しない外部端子と外部端子４、５との接続をワイ
ヤ６、７を用いて接続を行なっているため、ワイヤ６、
７がケース基板や図示しない封止蓋等の他の部位に接触
しないように、ワイヤの高さを十分に確保する必要があ
り、その結果半導体モジュールの厚みが大きくなるとい
う欠点がある。さらにワイヤ６、７の一端をケース基板
の外部端子４、５に接続するためのスペース、及び枠体
８を形成するためのスペースを、ケース基板３の上面縁
部に確保する必要があるために、半導体モジュールの面
積が大きくなるという欠点もある。2. Description of the Related Art As a conventional semiconductor module, one having a structure as shown in FIG. 8 is generally used. In the figure, reference numeral 1 is a semiconductor chip, the bottom surface of which is fixed to the case substrate 3 with an adhesive 2. External terminals (conductive patterns) 4 and 5 for external connection are formed in a U-shape from the upper surface, the side surface, and the lower surface at the opposite edges of the case substrate 3, respectively. Wires 6 and 7 are electrically connected to terminals (not shown) on the upper surface of the semiconductor chip 1. Further, an annular frame body 8 made of a metal for sealing is integrally formed on the peripheral edge of the upper surface of the case substrate 3, and the space formed by the upper surface of the case substrate 3 and the frame body 8 is filled with a resin 9. . It should be noted that the case shown by the dotted line in FIG. 8 is such a case when the insulating substrate 12 is sealed with the case. In the semiconductor module having such a structure, since the external terminals (not shown) on the upper surface of the semiconductor chip 1 and the external terminals 4, 5 are connected using the wires 6, 7, the wires 6,
It is necessary to secure the height of the wire sufficiently so that the wire 7 does not come into contact with other parts such as the case substrate and the sealing lid (not shown), and as a result, there is a drawback that the thickness of the semiconductor module becomes large. Further, it is necessary to secure a space for connecting one ends of the wires 6, 7 to the external terminals 4, 5 of the case substrate and a space for forming the frame body 8 at the upper edge of the case substrate 3. However, there is also a drawback that the area of the semiconductor module becomes large.
【０００３】上述のような欠点を解決するための手法と
して、例えば図９のような構造の半導体モジュールが提
案されている。同図の半導体モジュールにおいては、半
導体チップ１の下面の図示しない外部端子にはんだや金
等から成る導電性突起物１０、１１を一体形成してお
き、この導電性突起物を絶縁性基板１２の表面に形成さ
れた導電性パターン１３、１４に電気的に導通するよう
接続している。この接続方法としては、例えば導電性突
起物１０、１１がはんだから成る場合には、リフローま
たは熱圧着による接続、金から成る場合には熱圧着また
は導電性接着剤を用いた接続方法が一般的に採用されて
いる。さらに半導体チップ１と絶縁性基板１２との隙間
には、封止用樹脂１５が充填されている。また、絶縁性
基板１２上面の導電性パターン１３、１４は、絶縁性基
板１２の端部まで引き延ばされ、絶縁性基板１２の上面
端部、側面及び下面端部にかけてコ字状に被着された外
部端子１６、１７と接続されている。なお、導電性突起
物１０、１１と封止用樹脂１５との間は空所ではなく、
上記溶着用金属、導電性接着剤等が位置している。この
ような構成の半導体モジュールをプリント配線板に搭載
すると、図１０のような構成になる。すなわちプリント
配線板１８上の配線パターン１９、２０と、前記外部端
子１６、１７とをはんだ２１、２２により電気的に接続
することにより、プリント配線板上への搭載が完了す
る。As a method for solving the above-mentioned drawbacks, for example, a semiconductor module having a structure as shown in FIG. 9 has been proposed. In the semiconductor module shown in the figure, conductive projections 10 and 11 made of solder, gold, or the like are integrally formed on external terminals (not shown) on the lower surface of the semiconductor chip 1, and the conductive projections are formed on the insulating substrate 12. The conductive patterns 13 and 14 formed on the surface are electrically connected to each other. As the connection method, for example, when the conductive protrusions 10 and 11 are made of solder, connection by reflow or thermocompression bonding is used, and when they are made of gold, thermocompression bonding or a connection method using a conductive adhesive is generally used. Has been adopted by. Further, the gap between the semiconductor chip 1 and the insulating substrate 12 is filled with the sealing resin 15. Further, the conductive patterns 13 and 14 on the upper surface of the insulating substrate 12 are extended to the end portion of the insulating substrate 12, and are attached in a U shape to the upper end portion, the side surface and the lower end portion of the insulating substrate 12. The external terminals 16 and 17 are connected to each other. The space between the conductive protrusions 10 and 11 and the sealing resin 15 is not a vacant space,
The metal for welding, the conductive adhesive, etc. are located. When a semiconductor module having such a structure is mounted on a printed wiring board, a structure as shown in FIG. 10 is obtained. That is, the wiring patterns 19 and 20 on the printed wiring board 18 and the external terminals 16 and 17 are electrically connected by the solders 21 and 22 to complete the mounting on the printed wiring board.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うに構成したことにより、図８に示した半導体モジュー
ルよりも若干の小型化（小面積化、薄型化）が可能とな
るものの、十分とはいえず、さらなる小型化への要求が
高まっている。特に実装高さを低くすることが望まれて
いる。本発明は上述した如き半導体モジュールが有する
欠点を除去する為になされたものであって、小型に実装
可能な半導体モジュールを提供することを目的とする。However, although it is possible to make the semiconductor module a little smaller (smaller area and thinner) than the semiconductor module shown in FIG. 8 by such a structure, it is still sufficient. Instead, there is an increasing demand for further miniaturization. In particular, it is desired to reduce the mounting height. The present invention has been made to eliminate the drawbacks of the semiconductor module as described above, and an object thereof is to provide a semiconductor module that can be mounted in a small size.
【０００５】[0005]
【課題を解決する為の手段】上述の目的を達成するた
め、請求項１の発明は、絶縁性基板の表面に形成された
外部端子と、半導体チップの端子に形成された導電性突
起物とを電気的に導通するよう接合して成る半導体モジ
ュールを、プリント配線板上の配線パターン上に電気的
に接続したものに於いて、前記絶縁性基板の外部端子
を、前記絶縁性基板の半導体チップを搭載した面のみに
形成したことを特徴とする。請求項２の発明は、前記プ
リント配線板に凹陥を形成しておき、この凹陥に前記半
導体チップを嵌合するようにしたことを特徴とする。請
求項３の発明は、前記プリント配線板に貫通孔を形成し
ておき、この貫通孔に前記半導体チップが嵌合されるよ
うにしたことを特徴とする。In order to achieve the above-mentioned object, the invention of claim 1 provides an external terminal formed on the surface of an insulating substrate, and a conductive protrusion formed on the terminal of a semiconductor chip. In which a semiconductor module formed by joining so as to be electrically connected to each other is electrically connected to a wiring pattern on a printed wiring board, the external terminal of the insulating substrate is a semiconductor chip of the insulating substrate. It is characterized in that it is formed only on the surface on which is mounted. The invention of claim 2 is characterized in that a recess is formed in the printed wiring board, and the semiconductor chip is fitted into the recess. According to a third aspect of the invention, a through hole is formed in the printed wiring board, and the semiconductor chip is fitted into the through hole.
【０００６】[0006]
【発明の実施の形態】以下、本発明を図示した実施例に
基づいて詳細に説明する。図１は本発明の一実施例を示
す断面図である。本実施例では、絶縁性基板１２に半導
体チップ１を搭載した半導体モジュールＭを、プリント
配線板１８上に取り付ける際に、あらかじめプリント配
線板１８の半導体モジュールＭに対向する面に凹陥２３
を形成しておき、半導体モジュールＭの半導体チップ１
が凹陥２３に嵌入されるように半導体モジュールＭを絶
縁性基板１２上に搭載し、プリント配線板１８上の配線
パターン１９、２０と半導体モジュールの外部端子１
６、１７とをはんだ２１、２２により電気的に接続した
ものである。なお、その他の符号は、上記従来例の図面
と同様であり、符号１０、１１は導電性突起物、１５は
封止用樹脂である。上述のように半導体チップ１をプリ
ント配線板１８側に向けると共に、プリント配線板１８
に設けた凹陥２３内に半導体チップ１を嵌入させるよう
に、半導体モジュールＭをプリント配線板１８に取り付
けることにより、半導体チップの肉厚分だけ実装高さを
低くすることが可能となる。またプリント配線板１８の
半導体モジュールを搭載した面と反対面にも他の部品の
搭載および配線パターンの形成が可能となる。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the illustrated embodiments. FIG. 1 is a sectional view showing one embodiment of the present invention. In this embodiment, when the semiconductor module M having the semiconductor chip 1 mounted on the insulating substrate 12 is mounted on the printed wiring board 18, a recess 23 is formed on the surface of the printed wiring board 18 facing the semiconductor module M in advance.
The semiconductor chip 1 of the semiconductor module M.
The semiconductor module M is mounted on the insulative substrate 12 so as to fit into the recess 23, and the wiring patterns 19 and 20 on the printed wiring board 18 and the external terminals 1 of the semiconductor module 1 are mounted.
6 and 17 are electrically connected by solders 21 and 22. The other reference numerals are the same as those in the drawings of the above-mentioned conventional example, reference numerals 10 and 11 are conductive protrusions, and 15 is a sealing resin. The semiconductor chip 1 is directed to the printed wiring board 18 side as described above, and
By mounting the semiconductor module M on the printed wiring board 18 so that the semiconductor chip 1 is fitted in the recess 23 provided in the board 23, the mounting height can be reduced by the thickness of the semiconductor chip. Further, it is possible to mount other components and form a wiring pattern on the surface of the printed wiring board 18 opposite to the surface on which the semiconductor module is mounted.
【０００７】なお、凹陥２３を形成する方法としては、
プリント基板面に切削加工を加える方法、プリント基板
面をエッチングする方法、或は穴の開いていない薄い基
板材料上に穴の開いた薄い基板材料を積層することによ
り凹陥２３を形成する方法等を挙げることができる。最
後の方法に於て凹陥の深さを調整する場合には、同一形
状の穴を有した薄い基板材料を複数枚積層すれば良い。
ところで、肉厚がより薄いプリント配線板１８に対し
て、図１に示した手法によって半導体モジュールＭを取
り付ける場合、上記いずれの凹陥形成方法によっても、
凹陥２３を形成することが困難となることがあり、この
問題を解決するためには図２に示す構成を採用すること
が有効である。As a method of forming the recess 23,
A method of cutting the printed circuit board surface, a method of etching the printed circuit board surface, a method of forming a recess 23 by laminating a thin board material with holes on a thin board material without holes, and the like. Can be mentioned. When adjusting the depth of the recess in the last method, a plurality of thin substrate materials having holes of the same shape may be laminated.
By the way, when the semiconductor module M is attached to the thinner printed wiring board 18 by the method shown in FIG.
It may be difficult to form the recess 23, and in order to solve this problem, it is effective to adopt the configuration shown in FIG.
【０００８】即ち、図２は本発明の第２の実施例を示す
断面図であり、この実施例では、絶縁性基板１２に半導
体チップ１を搭載した半導体モジュールＭをプリント配
線板１８に実装する際に、あらかじめプリント配線板１
８の半導体モジュールＭと対向する面に貫通孔２４を形
成しておき、半導体モジュールの半導体チップ１が前記
孔２４内に嵌入されるように半導体モジュールを搭載
し、プリント配線板１８の配線パターン１９、２０と半
導体モジュールの外部端子１６、１７をはんだ２１、２
２により電気的に接続している。上述のように半導体モ
ジュールＭをプリント配線板１８上に取り付けることに
より、上述の実施例と同様に半導体チップ１の高さ分だ
け実装高さを低くすることが可能である。このように貫
通孔２４を形成してしまうと、プリント配線板１８の裏
面に配線パターンを形成することはできないが、図１の
実施例の凹陥２３に比べ、貫通孔２４の方が加工が容易
であるため、安価なプリント配線板１８を提供すること
が可能となる。That is, FIG. 2 is a sectional view showing a second embodiment of the present invention. In this embodiment, a semiconductor module M in which the semiconductor chip 1 is mounted on the insulating substrate 12 is mounted on the printed wiring board 18. At the time of printed wiring board 1
8 has a through hole 24 formed in the surface facing the semiconductor module M, the semiconductor module is mounted so that the semiconductor chip 1 of the semiconductor module is fitted into the hole 24, and the wiring pattern 19 of the printed wiring board 18 is provided. , 20 and the external terminals 16, 17 of the semiconductor module are soldered 21, 2
It is electrically connected by 2. By mounting the semiconductor module M on the printed wiring board 18 as described above, the mounting height can be reduced by the height of the semiconductor chip 1 as in the above-described embodiment. If the through holes 24 are formed in this way, the wiring pattern cannot be formed on the back surface of the printed wiring board 18, but the through holes 24 are easier to process than the recesses 23 of the embodiment of FIG. Therefore, it is possible to provide the inexpensive printed wiring board 18.
【０００９】図３は本発明の第３の実施例を示す断面図
であり、この半導体モジュールは、図１、図２中に示し
たものと同様の構成を備えている。この半導体モジュー
ルＭにおいては、導通パッド２５、２６が絶縁性基板１
２の半導体チップ１の搭載面側だけに設けられており、
図８の従来例に示した如き絶縁性基板１２の側面および
裏面の外部端子が設けられていない。図１又は図２に示
したプリント配線板１８への取り付け方法を採用するに
当たっては、このような構成の半導体モジュールＭの方
が適しているばかりでなく、半導体モジュールの絶縁性
基板１２の製造に当たっても配線を片側のみに形成すれ
ば良いので、絶縁性基板１２へのパターンの形成が容易
となる。同一構成の半導体チップ１を用いた場合、図１
又は図２の半導体モジュールの取り付け方法を採用する
ことにより、図８に示した従来の半導体モジュールの外
部端子４、５の配置（ＩＮとＯＵＴの配置）と同等の外
部端子配置を実現することができるので、外部端子の接
続対象となるプリント配線板上の配線パターンに変更を
加える必要がないというメリットを提供する。FIG. 3 is a sectional view showing a third embodiment of the present invention, and this semiconductor module has the same structure as that shown in FIGS. 1 and 2. In this semiconductor module M, the conduction pads 25 and 26 are the insulating substrate 1.
2 is provided only on the mounting surface side of the semiconductor chip 1,
External terminals on the side surface and the back surface of the insulating substrate 12 as shown in the conventional example of FIG. 8 are not provided. In adopting the method of attaching to the printed wiring board 18 shown in FIG. 1 or 2, not only the semiconductor module M having such a structure is more suitable, but also the insulating substrate 12 of the semiconductor module is manufactured. Also, since the wiring may be formed on only one side, the pattern can be easily formed on the insulating substrate 12. When the semiconductor chips 1 having the same structure are used, as shown in FIG.
Alternatively, by adopting the mounting method of the semiconductor module of FIG. 2, it is possible to realize the external terminal arrangement equivalent to the arrangement of the external terminals 4 and 5 (arrangement of IN and OUT) of the conventional semiconductor module shown in FIG. Therefore, it is possible to provide an advantage that it is not necessary to change the wiring pattern on the printed wiring board to which the external terminals are connected.
【００１０】これを詳述すると、例えば従来の（図８に
示された）半導体モジュールは図４（ａ）の底面図（下
方に位置するプリント配線板側から見た図）に示すよう
に、外部端子４、５は、Ａ、Ｂ、Ｃ、Ｄの４端子構造で
あり、各外部端子は図示の配列となっている。これに対
して、半導体チップ１の表裏が反転している図９、図１
０においては、プリント配線板１８側から見た図４
（ｂ）のように絶縁基板１２側の外部端子Ａ、Ｂ、Ｃ、
Ｄの配置が左右反転している。このことは、プリント配
線板１８側の配線パターンの大幅な変更を強いる結果と
なる。図５(a) は図４(a) の外部端子Ａ、Ｂ、Ｃ、Ｄに
対応するプリント配線板側の配線パターンを示してお
り、各リードパターンＡ、Ｂ、Ｃ、Ｄは、夫々外部端子
Ａ、Ｂ、Ｃ、Ｄに対応して接続されるものである。次
に、図５(b) は図４(b) の外部端子Ａ、Ｂ、Ｃ、Ｄの配
列に対応してプリント配線板側に形成されるリードパタ
ーンであり、絶縁性基板１２側の外部端子が左右逆転し
ている結果としてプリント配線板側のリードパターンも
配線をクロスさせる等の大幅な変更が必要となる。To explain this in detail, for example, a conventional semiconductor module (shown in FIG. 8) is as shown in a bottom view of FIG. 4A (a view seen from a printed wiring board side located below). The external terminals 4 and 5 have a four-terminal structure of A, B, C, and D, and each external terminal has the arrangement shown in the drawing. On the other hand, the front and back of the semiconductor chip 1 are reversed, as shown in FIGS.
In FIG. 4, when viewed from the printed wiring board 18 side in FIG.
As shown in (b), the external terminals A, B, C on the insulating substrate 12 side,
The arrangement of D is horizontally reversed. This results in a drastic change in the wiring pattern on the printed wiring board 18 side. FIG. 5 (a) shows a wiring pattern on the printed wiring board side corresponding to the external terminals A, B, C, D of FIG. 4 (a), and each lead pattern A, B, C, D is external. The terminals are connected corresponding to the terminals A, B, C and D. Next, FIG. 5B is a lead pattern formed on the printed wiring board side corresponding to the arrangement of the external terminals A, B, C and D of FIG. As a result of left-right inversion of the terminals, the lead pattern on the printed wiring board side also requires a major change such as crossing the wiring.
【００１１】次に、図４(c) は本発明による絶縁基板の
外部端子の構成を示す底面図であり、各外部端子１６、
１７（Ａ、Ｂ、Ｃ、Ｄ）の配列は図９、図１０のものと
まったく同じである。このため、図５(c) に示すように
プリント配線板側のリードパターンは図８のものと全く
同じになる。このことは、図８のモジュール用に作成さ
れたプリント配線パターンをそのまま用いて図１、図２
のモジュールを作成できることを意味する。なお、図５
(c) 中一点鎖線で示した部分は絶縁性基板１２が小さい
場合であり、このような小さい絶縁性基板１２を既存の
プリント配線板に適用する場合には図示した如き延長配
線パターン３０を付加すれば済むので容易であり、柔軟
な対応が可能となる。Next, FIG. 4 (c) is a bottom view showing the structure of the external terminals of the insulating substrate according to the present invention.
The arrangement of 17 (A, B, C, D) is exactly the same as that of FIGS. 9 and 10. Therefore, as shown in FIG. 5 (c), the lead pattern on the printed wiring board side is exactly the same as that of FIG. This is because the printed wiring pattern created for the module in FIG. 8 is used as it is in FIG.
Means that you can create a module. FIG.
(c) The portion indicated by the alternate long and short dash line is the case where the insulating substrate 12 is small, and when such a small insulating substrate 12 is applied to an existing printed wiring board, the extension wiring pattern 30 as shown is added. All that is required is easy, and flexible correspondence is possible.
【００１２】このように図９、図１０のモジュールのよ
うに絶縁性基板の外部端子が図８に示した既存のものと
左右逆転していると、プリント配線板側の配線パターン
を大幅に改造する必要があった為、既存のプリント配線
板を利用したモジュールの置き換えを容易に行うことが
できなかった。これに対し本発明の半導体モジュールの
取り付け方法を採用すれば、絶縁性基板の外部端子の配
列が（半導体チップ１の向きも）図８の場合と一致する
ため、従来の半導体モジュールとの置き換えが極めて容
易になる。尚、以上本発明を１つの半導体チップを搭載
した半導体モジュールに適用したものを例として説明し
たが、本発明はこれのみに限定されるものではなく、一
つの絶縁性基板に複数個の半導体チップを搭載したも
の、さらに半導体以外の電子部品を同時に搭載した半導
体モジュールであってもよい。また半導体チップを直接
組み付ける相手側部品としての絶縁性基板としては、プ
リント配線板、セラミック基板またはシリコン基板を例
示することができる。As described above, when the external terminals of the insulating substrate are left-right reversed from those of the existing one shown in FIG. 8 as in the module of FIGS. 9 and 10, the wiring pattern on the printed wiring board side is greatly modified. Therefore, it was not possible to easily replace the module using the existing printed wiring board. On the other hand, if the semiconductor module mounting method of the present invention is adopted, the arrangement of the external terminals of the insulating substrate (and the orientation of the semiconductor chip 1) matches that of FIG. It will be extremely easy. Although the present invention has been described by way of example in which the present invention is applied to a semiconductor module mounted with one semiconductor chip, the present invention is not limited to this, and a plurality of semiconductor chips can be provided on one insulating substrate. It may be a semiconductor module on which is mounted, or a semiconductor module on which electronic components other than the semiconductor are mounted at the same time. Moreover, a printed wiring board, a ceramic substrate, or a silicon substrate can be illustrated as an insulating substrate as a counterpart component to which a semiconductor chip is directly assembled.
【００１３】[0013]
【発明の効果】本発明は以上説明した如く構成するもの
であるから小型または薄型に実装可能な半導体モジュー
ルおよび薄型の実装品を提供する上で、また従来の半導
体モジュールとの置き換えを容易にする上で著しい効果
を発揮する。Since the present invention is configured as described above, it provides a semiconductor module that can be mounted in a small size or a thin shape and a thin mounted product, and facilitates replacement with a conventional semiconductor module. Exerts a remarkable effect on the above.
【図１】本発明に係わる半導体モジュールのプリント配
線板への取り付け方法の一実施例を示す断面図。FIG. 1 is a cross-sectional view showing an embodiment of a method for attaching a semiconductor module to a printed wiring board according to the present invention.
【図２】本発明に係わる半導体モジュールのプリント配
線板への取り付け方法の他の実施例を示す断面図。FIG. 2 is a cross-sectional view showing another embodiment of a method for attaching a semiconductor module to a printed wiring board according to the present invention.
【図３】本発明に係わる半導体モジュール構造の一実施
例を示す断面図。FIG. 3 is a sectional view showing an embodiment of a semiconductor module structure according to the present invention.
【図４】（ａ）、（ｂ）及び（ｃ）は半導体チップの外
部端子配置の向きを示す模式図。4A, 4B and 4C are schematic diagrams showing the orientation of the external terminal arrangement of the semiconductor chip.
【図５】（ａ）、（ｂ）及び（ｃ）は従来及び本発明に
よる配線状態を示す図。5 (a), (b) and (c) are diagrams showing a wiring state according to the related art and the present invention.
【図６】（ａ）及び（ｂ）は本発明の他の実施例の底面
図及びＸ−Ｘ断面図。6 (a) and 6 (b) are a bottom view and an X-X sectional view of another embodiment of the present invention.
【図７】本発明の他の実施例の底面図。FIG. 7 is a bottom view of another embodiment of the present invention.
【図８】従来の半導体モジュールの構造を示す断面図。FIG. 8 is a sectional view showing the structure of a conventional semiconductor module.
【図９】従来の半導体モジュールの構造を示す断面図。FIG. 9 is a sectional view showing the structure of a conventional semiconductor module.
【図１０】従来の半導体モジュールのプリント配線板へ
の取り付け方法を示す断面図。FIG. 10 is a cross-sectional view showing a conventional method for attaching a semiconductor module to a printed wiring board.
Ｍ・・・・半導体モジュール １……半導体チップ ２……接着剤 ３……ケース基板 ４、５……導電パターン ６、７……ワイヤ ８……枠体 ９……樹脂 １０、１１……導電性突起物 １２……絶縁性基板 １３、１４……導電性パターン １５……封止用樹脂 １６、１７、２５、２６……導電パッド １８……プリント配線板 １９、２０……配線パターン ２１、２２……はんだ ２３……凹陥 ２４……孔 M ... Semiconductor module 1 ... Semiconductor chip 2 ... Adhesive 3 ... Case substrate 4, 5 ... Conductive pattern 6, 7 ... Wire 8 ... Frame 9 ... Resin 10, 11 ... Conductive Protrusion 12 ... Insulating substrate 13, 14 ... Conductive pattern 15 ... Sealing resin 16, 17, 25, 26 ... Conductive pad 18 ... Printed wiring board 19, 20 ... Wiring pattern 21, 22 ... Solder 23 ... Concave 24 ... Hole
Claims (3)
と、半導体チップの端子に形成された導電性突起物とを
電気的に導通するよう接合して成る半導体モジュール
を、プリント配線板上の配線パターン上に電気的に接続
したものに於いて、 前記絶縁性基板の外部端子を、前記絶縁性基板の半導体
チップを搭載した面のみに形成したことを特徴とする半
導体モジュールの構造。1. A semiconductor module, comprising an external terminal formed on a surface of an insulating substrate and a conductive protrusion formed on a terminal of a semiconductor chip, which are joined together so as to be electrically conductive, on a printed wiring board. A structure of a semiconductor module, wherein the external terminal of the insulating substrate is formed only on the surface of the insulating substrate on which the semiconductor chip is mounted, which is electrically connected to the wiring pattern.
き、この凹陥に前記半導体チップを嵌合するようにした
ことを特徴とする請求項１記載の半導体モジュールの取
り付け方法。2. The method of mounting a semiconductor module according to claim 1, wherein a recess is formed in the printed wiring board, and the semiconductor chip is fitted into the recess.
おき、この貫通孔に前記半導体チップが嵌合されるよう
にしたことを特徴とする請求項１記載の半導体モジュー
ルの取り付け方法。3. The method of mounting a semiconductor module according to claim 1, wherein a through hole is formed in the printed wiring board, and the semiconductor chip is fitted into the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32233895A JPH09148371A (en) | 1995-11-16 | 1995-11-16 | Structure of semiconductor module and mounting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32233895A JPH09148371A (en) | 1995-11-16 | 1995-11-16 | Structure of semiconductor module and mounting method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09148371A true JPH09148371A (en) | 1997-06-06 |
Family
ID=18142537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32233895A Pending JPH09148371A (en) | 1995-11-16 | 1995-11-16 | Structure of semiconductor module and mounting method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09148371A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1416778A3 (en) * | 2002-11-01 | 2006-10-11 | Alps Electric Co., Ltd. | Small and securely-soldered electronic unit |
| JP2007274000A (en) * | 2007-05-01 | 2007-10-18 | Seiko Instruments Inc | Semiconductor device, method of manufacturing same, and method of manufacturing display device |
-
1995
- 1995-11-16 JP JP32233895A patent/JPH09148371A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1416778A3 (en) * | 2002-11-01 | 2006-10-11 | Alps Electric Co., Ltd. | Small and securely-soldered electronic unit |
| JP2007274000A (en) * | 2007-05-01 | 2007-10-18 | Seiko Instruments Inc | Semiconductor device, method of manufacturing same, and method of manufacturing display device |
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