JPH0878611A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0878611A JPH0878611A JP20644794A JP20644794A JPH0878611A JP H0878611 A JPH0878611 A JP H0878611A JP 20644794 A JP20644794 A JP 20644794A JP 20644794 A JP20644794 A JP 20644794A JP H0878611 A JPH0878611 A JP H0878611A
- Authority
- JP
- Japan
- Prior art keywords
- mold resin
- semiconductor chip
- semiconductor device
- thermal expansion
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
セミパワークラス以上の半導体パッケージ構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure of a semi-power class or higher.
【０００２】[0002]
【従来の技術】従来、かかるセミパワークラス以上の大
電力半導体装置のパッケージにおいては、負荷が短絡し
た場合などの異常時に発煙・発熱等の恐れがあるので、
半導体素子の破壊防止のために、半導体チップと接続さ
れるボンディングワイヤや、あるいはその周辺に各種の
工夫がなされている。2. Description of the Related Art Conventionally, in such a package of a high power semiconductor device of a semi-power class or higher, there is a fear of smoke generation or heat generation at the time of an abnormality such as a load short circuit.
In order to prevent the destruction of the semiconductor element, various measures have been taken in the bonding wire connected to the semiconductor chip or in the vicinity thereof.
【０００３】図３は従来の一例を示す半導体装置の構造
図である。図３に示すように、従来の半導体パッケージ
は、半導体チップ１を第一のリードフレーム部２上に固
定するとともに、ボンディングワイヤ５，６により半導
体チップ１のパッドと第二，第三のリードフレーム部
３，４とを接続する。しかる後、半導体チップ１を含む
全体をカバーで覆うか、あるいは樹脂で覆いモールド樹
脂部８を形成するかしている。FIG. 3 is a structural diagram of a conventional semiconductor device. As shown in FIG. 3, in the conventional semiconductor package, the semiconductor chip 1 is fixed on the first lead frame portion 2, and the pads of the semiconductor chip 1 and the second and third lead frames are bonded by the bonding wires 5 and 6. The parts 3 and 4 are connected. After that, the entire surface including the semiconductor chip 1 is covered with a cover or is covered with a resin to form the mold resin portion 8.
【０００４】かかる構造の半導体パッケージにおいて、
半導体チップ１を保護するための過電流遮断機能を実現
するにあたっては、例えば、特開昭６４−５０４５７号
公報に記載されたように、ボンディングワイヤ５，６に
形状記憶合金を用いたり、あるいは特開平４−１９９８
６５号公報に記載されたように、ボンディングワイヤ
５，６が接続されるパッドとアルミ配線間にヒューズ材
料を用いたりするか、ボンディングワイヤ５，６そのも
のをヒューズ材で形成するかしている。In the semiconductor package having such a structure,
In order to realize the overcurrent interruption function for protecting the semiconductor chip 1, for example, as described in JP-A-64-50457, a shape memory alloy is used for the bonding wires 5 and 6, or a special memory is used. Kaihei 4-1998
As described in Japanese Patent Laid-Open No. 65, the fuse material is used between the pad to which the bonding wires 5 and 6 are connected and the aluminum wiring, or the bonding wires 5 and 6 themselves are formed of the fuse material.
【０００５】[0005]
【発明が解決しようとする課題】上述した従来の半導体
装置において、前者の形状記憶合金を用いる場合には、
可動部を有するために、ワイヤの周囲を空間とする必要
があり、そのために半導体チップを樹脂等で封止するこ
とができないので、熱の放散性が悪化するという問題が
ある。この場合には、特に大電力を扱う半導体装置に適
用することができないという欠点がある。また、前者の
技術を用いる場合には、内部が中空であることや、ワイ
ヤの一端が固定されていない構造になるため、振動に対
して弱いという欠点もある。更に、前者の例は電流が遮
断されて半導体チップの温度が低下すると、自動的に元
の状態に復帰してしまうため、電流が遮断されている間
に根本的な対策を施さないと再び回路が遮断されること
になり、回路が不安定な状態に陥ってしまうという欠点
がある。In the conventional semiconductor device described above, when the former shape memory alloy is used,
Since there is a movable portion, it is necessary to make a space around the wire, and therefore the semiconductor chip cannot be sealed with a resin or the like, so that there is a problem that heat dissipation is deteriorated. In this case, there is a drawback in that it cannot be applied to a semiconductor device that handles particularly high power. Further, when the former technique is used, there is a drawback that it is vulnerable to vibration because it has a hollow interior and one end of the wire is not fixed. Furthermore, in the former example, when the current is cut off and the temperature of the semiconductor chip drops, the semiconductor chip automatically returns to its original state.Therefore, if fundamental measures are not taken while the current is cut off, the circuit will be restored again. Will be cut off and the circuit will fall into an unstable state.
【０００６】一方、後者のヒューズ材料を用いる場合に
は、半導体チップにヒューズ材を接続するためのリード
フレーム部を新設しなければならないという欠点があ
る。また、ワイヤにヒューズ材料を直接用いようとする
場合には、その加工性やボンディング方法の技術につい
て新たな問題が発生するという欠点がある。すなわち、
加工性については、直径１０〜１００μｍ程度の細線で
ループ状を形成する必要があったり、ボンディング方法
については、現在の金ワイヤであれば、電極を形成する
アルミとの金共晶を利用しているので、この点が可能か
否かといった問題がある。On the other hand, when the latter fuse material is used, there is a drawback that a lead frame portion for connecting the fuse material to the semiconductor chip must be newly provided. In addition, when the fuse material is directly used for the wire, there is a drawback that a new problem occurs in the workability and the technique of the bonding method. That is,
Regarding workability, it is necessary to form a loop shape with a thin wire with a diameter of about 10 to 100 μm, and regarding the bonding method, if the current gold wire is used, a gold eutectic with aluminum forming an electrode is used. Therefore, there is a problem as to whether or not this point is possible.
【０００７】本発明の目的は、かかるボンディングワイ
ヤに特種の材質を用いることなく、しかも負荷短絡など
の異常時に発生する過電流により半導体チップ等の回路
および周辺の装置に悪影響を与えないような半導体装置
を提供することにある。An object of the present invention is to provide a semiconductor that does not use a special material for such a bonding wire and does not adversely affect a circuit such as a semiconductor chip and peripheral devices due to an overcurrent generated at the time of an abnormality such as a load short circuit. To provide a device.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置は、
リードフレーム上に搭載した半導体チップと、前記半導
体チップおよび前記半導体チップに接続したボンディン
グワイヤの一部を覆う第一のモールド樹脂部と、前記第
一のモールド樹脂部を含んで外周を覆い且つ前記第一の
モールド樹脂部とは熱膨張係数を異ならせた第二のモー
ルド樹脂部とを有し、過電流発生時には前記第一および
第二のモールド樹脂部の境界面における前記ボンディン
グワイヤを切断するようにして構成される。The semiconductor device of the present invention comprises:
A semiconductor chip mounted on a lead frame, a first mold resin portion that covers the semiconductor chip and a part of the bonding wire connected to the semiconductor chip, and a first mold resin portion that covers the outer periphery and includes the first mold resin portion. The first mold resin portion has a second mold resin portion having a different coefficient of thermal expansion, and cuts the bonding wire at the interface between the first and second mold resin portions when an overcurrent occurs. It is configured in this way.
【０００９】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１は本発明の一実施例を示す半導体装置
の構造図である。図１に示すように、本実施例は表面実
装タイプの半導体パッケージであり、半導体チップ１を
アイランドとなる第一のリードフレーム部２上に搭載固
定する。また、半導体チップ１上のボンディングパッド
からはボンディングワイヤ５，６を介してそれぞれ第
二，第三のリードフレーム部３，４と接続する。ここ
で、本実施例は第一のモールド樹脂で半導体チップ１の
周囲のみを封止し、第一のモールド樹脂部７を形成す
る。ついで、第一のモールド樹脂部７や第二，第三のリ
ードフレーム部３，４等を含む外周を第一のモールド樹
脂とは熱膨張係数の異なる第二のモールド樹脂で封止し
第二のモールド樹脂部８を形成する。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a structural diagram of a semiconductor device showing an embodiment of the present invention. As shown in FIG. 1, this embodiment is a surface-mounting type semiconductor package, in which a semiconductor chip 1 is mounted and fixed on a first lead frame portion 2 serving as an island. Further, the bonding pads on the semiconductor chip 1 are connected to the second and third lead frame parts 3 and 4 via bonding wires 5 and 6, respectively. Here, in the present embodiment, only the periphery of the semiconductor chip 1 is sealed with the first mold resin to form the first mold resin portion 7. Then, the outer periphery including the first mold resin portion 7 and the second and third lead frame portions 3 and 4 is sealed with a second mold resin having a thermal expansion coefficient different from that of the first mold resin. The mold resin part 8 is formed.
【００１０】特に、第一のモールド樹脂部７と第二のモ
ールド樹脂部８の熱膨張係数は、通常の使用条件ではそ
の差が最小となり、異常時の過電流異常時の過電流によ
る半導体チップ１の発熱時には、その差が最大になるよ
うに選定される。このため、負荷短絡などによる過電流
発生時には、半導体自体の発熱で樹脂間に歪を発生させ
る。従って、これら両樹脂部７，８の境界面において、
ボンディングワイヤ５，６にせん断応力が働き、ワイヤ
の電流容量を低下させることにより溶断させるので、過
電流を遮断することができる。In particular, the difference between the thermal expansion coefficients of the first mold resin portion 7 and the second mold resin portion 8 becomes the minimum under normal use conditions, and the semiconductor chip due to the overcurrent at the time of abnormality When the heat generation is 1, the difference is selected so as to be the maximum. Therefore, when an overcurrent occurs due to a load short circuit or the like, the semiconductor itself generates heat to cause distortion between the resins. Therefore, at the boundary surface between these two resin parts 7 and 8,
Since shear stress acts on the bonding wires 5 and 6 to reduce the current capacity of the wires to melt them, overcurrent can be interrupted.
【００１１】図２は図１に示すモールド樹脂部のガラス
転移点温度の差異による熱膨張係数特性図である。図２
に示すように、第一のモールド樹脂部７の定常時の熱膨
張係数をα1A、ガラス転移点での熱膨張係数をα1Bと
し、同様に第二のモールド樹脂部８の定常時の熱膨張係
数をα2A、ガラス転移点での熱膨張係数をα2Bと表わす
と、α1A〈α2Aで且つα1B〈α2Bとなる任意の組合わせ
を選定すれば、相対的に半導体パッケージの内側は膨張
しにくく、外側は膨張しやすいように設定することがで
きる。FIG. 2 is a thermal expansion coefficient characteristic diagram due to the difference in glass transition temperature of the mold resin portion shown in FIG. Figure 2
As shown in, the steady-state thermal expansion coefficient of the first mold resin portion 7 is α 1A , and the thermal expansion coefficient at the glass transition point is α 1B. the expansion coefficient alpha 2A, when the thermal expansion coefficient of the glass transition point represent the alpha 2B, be selected any combination as a and alpha 1B <alpha 2B with α 1A <α 2A, a relatively semiconductor package It can be set so that the inside does not expand easily and the outside easily expands.
【００１２】例えば、第一のモールド樹脂７として、α
1A＝２．３×１０-5／℃、α1B＝６．５×１０-5／℃
（ガラス転移点：１４５〜１７０℃）を用い、また第二
のモールド樹脂８として、α2A＝２．８×１０-5／℃、
α2B＝７．５×１０-5／℃（ガラス転移点：１５０〜１
７０℃）を用いると、この組合わせの例の場合、定常時
の熱膨張係数の差は、α2A−α1A＝０．５×１０-5／℃
となり、また、異常時での熱膨張係数の差は、α2B−α
1B＝１．０×１０-5／℃となる。すなわち、異常時では
定常時の２倍の歪を発生させることができる。これによ
り、通常の使用状態ではボンディングワイヤ５，６への
ストレスを最小に抑えつつ、異常時には効果を最大に発
揮することが可能になる。For example, as the first mold resin 7, α
1A = 2.3 × 10 -5 / ° C, α 1B = 6.5 × 10 -5 / ° C
(Glass transition point: 145 to 170 ° C.), and as the second mold resin 8, α 2A = 2.8 × 10 −5 / ° C.,
α 2B = 7.5 × 10 −5 / ° C. (glass transition point: 150 to 1)
70 ° C.), in the case of this combination example, the difference in the coefficient of thermal expansion in the steady state is α 2A −α 1A = 0.5 × 10 −5 / ° C.
And the difference in the coefficient of thermal expansion at the time of abnormality is α 2B −α
1B = 1.0 × 10 −5 / ° C. That is, it is possible to generate a strain that is twice as large as that in the steady state in the abnormal state. This makes it possible to minimize the stress on the bonding wires 5 and 6 in a normal use state, and maximize the effect in an abnormal state.
【００１３】次に、具体的な温度を設定し、モールド樹
脂のずれ（ΔＬ）を説明する。通常使用状態での半導体
チップ１の温度（Ｔ）をＴ＝６０℃、異常時の温度
（Ｔ’）をＴ’＝２００℃と仮定し、パッケージ寸法１
ｍｍ（Ｌ）あたりのモールド樹脂のずれを計算すると、
ΔＬ＝Δα×Ｌ×ΔＴより、通常使用状態では、 ΔＬ＝０．５×１０-5×１×１０-3×（６０−２５）＝
０．１７５μｍ であるのに対し、異常時では、 ΔＬ＝１．０×１０-5×１×１０-3×（２００−２５）
＝１．７５μｍ となる。Next, a specific temperature is set and the deviation (ΔL) of the mold resin will be described. Assuming that the temperature (T) of the semiconductor chip 1 in the normal use state is T = 60 ° C. and the temperature (T ′) at the time of abnormality is T ′ = 200 ° C., the package size 1
When calculating the deviation of the mold resin per mm (L),
From ΔL = Δα × L × ΔT, in normal use, ΔL = 0.5 × 10 −5 × 1 × 10 −3 × (60−25) =
0.175 μm, while ΔL = 1.0 × 10 −5 × 1 × 10 −3 × (200-25)
= 1.75 μm.
【００１４】しかるに、本実施例の主な利用分野である
セミパワークラス以上の半導体装置のパッケージ寸法
は、最小でも５ｍｍ程度であるので、この場合の総合的
なずれは約９μｍ強になる。これに対し、上述したクラ
スの半導体装置に用いられるボンディングワイヤの直径
は一般的に３０〜５０μｍ程度であるので、モールド樹
脂のずれによりボンディングワイヤを切断したり、ある
いはボンディングワイヤを切断するまでは至らなくても
ボンディングワイヤにせん断応力を加え、その直径を部
分的に細くして電流容量を低下させ溶断に至らしめるこ
とができる。However, since the package size of the semiconductor device of the semi-power class or higher, which is the main application field of this embodiment, is about 5 mm at the minimum, the total deviation in this case is about 9 μm or more. On the other hand, since the diameter of the bonding wire used in the above-described class of semiconductor device is generally about 30 to 50 μm, the bonding wire may be cut due to the displacement of the mold resin, or the bonding wire may not be cut. Even if it does not exist, it is possible to apply shearing stress to the bonding wire and partially reduce the diameter thereof to reduce the current capacity and lead to fusing.
【００１５】上述した一実施例においては、通常使用状
態のモールド樹脂のずれに対し異常時のずれを約１０倍
にしているが、更にもっと大きなずれを発生すれように
設定することもできる。すなわち、第一のモールド樹脂
７と第二のモールド樹脂８との組合わせを、樹脂の熱膨
張係数がガラス転移点を境に急激に上昇することに着目
して選定すればよい。In the above-described embodiment, the deviation at the time of abnormality is about 10 times the deviation of the mold resin in the normal use state, but it can be set so as to cause a larger deviation. That is, the combination of the first mold resin 7 and the second mold resin 8 may be selected by paying attention to the fact that the thermal expansion coefficient of the resin sharply increases at the glass transition point.
【００１６】例えば、内側にある第一のモールド樹脂７
のガラス転移点をＴ＝２００℃、外側にある第二のモー
ルド樹脂８のガラス転移点をＴ’＝１７０℃であるとす
ると、半導体チップ１の温度が２００℃に達するまでの
間、二種類のモールド樹脂の熱膨張係数の差は、α2B−
α1A＝５．２×１０-5／℃となる。従って、パッケージ
寸法を５ｍｍとし、前述した一実施例と同様に計算した
ときの異常時での樹脂のずれ（ΔＬ）を計算すると、Δ
Ｌは ΔＬ＝５．２×１０-5×５×１０-3×（１７０−２５）
＝３７．７μｍ となる。このため、ボンディングワイヤの直径程度のず
れを樹脂に発生させるので、かなり大きなストレスをボ
ンディングワイヤに加えることができ、ワイヤの切断も
可能になる。For example, the first molding resin 7 on the inside
The glass transition point of T = 200 ° C. and the glass transition point of the outer second mold resin 8 is T ′ = 170 ° C., there are two types until the temperature of the semiconductor chip 1 reaches 200 ° C. The difference in the coefficient of thermal expansion between the mold resins is α 2B −
α 1A = 5.2 × 10 -5 / ° C. Therefore, when the package dimension is 5 mm and the resin deviation (ΔL) at the time of abnormality when calculated in the same manner as in the above-described embodiment,
L is ΔL = 5.2 × 10 −5 × 5 × 10 −3 × (170-25)
= 37.7 μm. For this reason, since a deviation of about the diameter of the bonding wire is generated in the resin, a considerably large stress can be applied to the bonding wire, and the wire can be cut.
【００１７】[0017]
【発明の効果】以上説明したように、本発明の半導体装
置は、半導体チップを覆う樹脂を二層構造とし且つこれ
らの樹脂の熱膨張係数が通常の使用時と異常時とで大き
な差を生ずるように形成することにより、過電流防止機
能を実現でき、回路の異常範囲の拡大を防止できるの
で、負荷短絡などの異常時に発生する過電流により半導
体チップ等の回路および周辺の装置に悪影響を与えない
ようすることができるという効果がある。As described above, in the semiconductor device of the present invention, the resin covering the semiconductor chip has a two-layer structure, and the coefficient of thermal expansion of these resins causes a large difference between normal use and abnormal conditions. With this structure, the overcurrent prevention function can be realized and the abnormal range of the circuit can be prevented from being expanded.Therefore, the overcurrent that occurs during an abnormality such as a load short circuit may adversely affect the circuit such as the semiconductor chip and peripheral devices. The effect is that it can be avoided.
【００１８】また、本発明の半導体装置は、ボンディン
グワイヤに形状記憶合金等の特種な材質を用いることな
く実現できるという効果がある。Further, the semiconductor device of the present invention has an effect that it can be realized without using a special material such as a shape memory alloy for the bonding wire.
【図１】本発明の一実施例を示す半導体装置の構造図で
ある。FIG. 1 is a structural diagram of a semiconductor device showing an embodiment of the present invention.
【図２】図１に示すモールド樹脂部のガラス転移点温度
の差異による熱膨張係数特性図である。FIG. 2 is a thermal expansion coefficient characteristic diagram due to a difference in glass transition temperature of the mold resin portion shown in FIG.
【図３】従来の一例を示す半導体装置の構造図である。FIG. 3 is a structural diagram of a semiconductor device showing a conventional example.
１ 半導体チップ ２〜４ リードフレーム部 ５，６ ボンディングワイヤ ７ 第一のモールド樹脂部 ８ 第二のモールド樹脂部 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2-4 Lead frame part 5,6 Bonding wire 7 First mold resin part 8 Second mold resin part
Claims (3)
プと、前記半導体チップおよび前記半導体チップに接続
したボンディングワイヤの一部を覆う第一のモールド樹
脂部と、前記第一のモールド樹脂部を含んで外周を覆い
且つ前記第一のモールド樹脂部とは熱膨張係数を異なら
せた第二のモールド樹脂部とを有し、過電流発生時には
前記第一および第二のモールド樹脂部の境界面における
前記ボンディングワイヤを切断しうるようにしたことを
特徴とする半導体装置。1. A semiconductor chip mounted on a lead frame, a first mold resin part covering a part of the semiconductor chip and a bonding wire connected to the semiconductor chip, and a first mold resin part. It has a second mold resin portion that covers the outer periphery and has a different thermal expansion coefficient from the first mold resin portion, and at the time of overcurrent occurrence, at the boundary surface between the first and second mold resin portions. A semiconductor device characterized in that a bonding wire can be cut.
熱膨張係数は、通常の使用条件ではその差が最小とな
り、異常時の過電流による前記半導体チップの発熱時に
はその差が最大になるように選定した請求項１記載の半
導体装置。2. The difference between the thermal expansion coefficients of the first and second mold resin parts is minimum under normal use conditions, and the difference is maximum when the semiconductor chip generates heat due to an overcurrent in an abnormal condition. The semiconductor device according to claim 1, selected as described above.
前記第一および第二のモールド樹脂部の境界面における
前記ボンディングワイヤにせん断応力を加えることによ
り、電流容量を低下させて溶断させる請求項２記載の半
導体装置。3. When an overcurrent occurs in the semiconductor chip,
3. The semiconductor device according to claim 2, wherein the bonding wire at the boundary surface between the first and second mold resin portions is subjected to shear stress to reduce the current capacity and melt the fuse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20644794A JPH0878611A (en) | 1994-08-31 | 1994-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20644794A JPH0878611A (en) | 1994-08-31 | 1994-08-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0878611A true JPH0878611A (en) | 1996-03-22 |
Family
ID=16523532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20644794A Pending JPH0878611A (en) | 1994-08-31 | 1994-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0878611A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1075010A3 (en) * | 1999-07-31 | 2002-08-28 | Siemens Aktiengesellschaft | Semiconductor switch |
| WO2003100855A1 (en) * | 2002-05-24 | 2003-12-04 | Robert Bosch Gmbh | Electrical component |
| EP1906448A1 (en) * | 2006-09-29 | 2008-04-02 | Delphi Technologies, Inc. | Protected field effect transistor device |
| JP2020096471A (en) * | 2018-12-14 | 2020-06-18 | 三菱電機株式会社 | Power conversion device |
| WO2023015456A1 (en) * | 2021-08-10 | 2023-02-16 | 华为技术有限公司 | Packaging structure and electronic apparatus |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57202761A (en) * | 1982-05-24 | 1982-12-11 | Nec Corp | Resin sealed semiconductor device |
| JPS62205652A (en) * | 1986-03-05 | 1987-09-10 | Hitachi Cable Ltd | Ic package |
| JPS6334965A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Resin-sealed semiconductor device |
| JPS6340348A (en) * | 1986-08-05 | 1988-02-20 | Mitsubishi Electric Corp | Resin seal type semiconductor device and manufacture thereof |
| JPS63169746A (en) * | 1987-01-07 | 1988-07-13 | Nec Yamagata Ltd | Semiconductor device |
| JPH03296250A (en) * | 1990-04-16 | 1991-12-26 | Toshiba Corp | Semiconductor device sealed with resin |
| JPH04211150A (en) * | 1991-02-08 | 1992-08-03 | Sanken Electric Co Ltd | Circuit board |
-
1994
- 1994-08-31 JP JP20644794A patent/JPH0878611A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57202761A (en) * | 1982-05-24 | 1982-12-11 | Nec Corp | Resin sealed semiconductor device |
| JPS62205652A (en) * | 1986-03-05 | 1987-09-10 | Hitachi Cable Ltd | Ic package |
| JPS6334965A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Resin-sealed semiconductor device |
| JPS6340348A (en) * | 1986-08-05 | 1988-02-20 | Mitsubishi Electric Corp | Resin seal type semiconductor device and manufacture thereof |
| JPS63169746A (en) * | 1987-01-07 | 1988-07-13 | Nec Yamagata Ltd | Semiconductor device |
| JPH03296250A (en) * | 1990-04-16 | 1991-12-26 | Toshiba Corp | Semiconductor device sealed with resin |
| JPH04211150A (en) * | 1991-02-08 | 1992-08-03 | Sanken Electric Co Ltd | Circuit board |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1075010A3 (en) * | 1999-07-31 | 2002-08-28 | Siemens Aktiengesellschaft | Semiconductor switch |
| US6504467B1 (en) | 1999-07-31 | 2003-01-07 | Mannesmann Vdo Ag | Switch integral in a semiconductor element |
| WO2003100855A1 (en) * | 2002-05-24 | 2003-12-04 | Robert Bosch Gmbh | Electrical component |
| EP1906448A1 (en) * | 2006-09-29 | 2008-04-02 | Delphi Technologies, Inc. | Protected field effect transistor device |
| JP2020096471A (en) * | 2018-12-14 | 2020-06-18 | 三菱電機株式会社 | Power conversion device |
| WO2023015456A1 (en) * | 2021-08-10 | 2023-02-16 | 华为技术有限公司 | Packaging structure and electronic apparatus |
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| Date | Code | Title | Description |
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| A02 | Decision of refusal |
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