JP2823064B2 - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JP2823064B2
JP2823064B2 JP29749893A JP29749893A JP2823064B2 JP 2823064 B2 JP2823064 B2 JP 2823064B2 JP 29749893 A JP29749893 A JP 29749893A JP 29749893 A JP29749893 A JP 29749893A JP 2823064 B2 JP2823064 B2 JP 2823064B2
Authority
JP
Japan
Prior art keywords
film
lead frame
semiconductor device
bus bar
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29749893A
Other languages
Japanese (ja)
Other versions
JPH07130944A (en
Inventor
健一 金子
敏雄 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP29749893A priority Critical patent/JP2823064B2/en
Publication of JPH07130944A publication Critical patent/JPH07130944A/en
Application granted granted Critical
Publication of JP2823064B2 publication Critical patent/JP2823064B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置用リードフ
レームに関し、特に、リードフレームと半導体チップと
の間にフィルムが接着された半導体装置用リードフレー
ムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame for a semiconductor device in which a film is bonded between a lead frame and a semiconductor chip.

【０００２】[0002]

【従来の技術】リードフレームには、インナーリードの
ブレによるボンディングミスの防止、ボンディングワイ
ヤとベッドとの短絡防止、或いはリードの変形を防止す
るため、半導体チップとの接着の前に、例えば、ポリイ
ミド等のフィルムが貼り付けられる。フィルムをリード
フレームに貼り付けるには、予め、例えば熱可塑性接着
剤等を塗布しておき、高温に熱せられたリードフレーム
上にこのフィルムを押し付け、接着剤をリードフレーム
の温度で溶融させてフィルムをリードフレームに接着さ
せる。2. Description of the Related Art In order to prevent a bonding error due to a shift of an inner lead, a short circuit between a bonding wire and a bed, or a deformation of a lead, a lead frame is made of, for example, polyimide before bonding to a semiconductor chip. Is attached. To attach the film to the lead frame, apply a thermoplastic adhesive, for example, in advance, press the film onto the lead frame heated to a high temperature, and melt the adhesive at the temperature of the lead frame. To the lead frame.

【０００３】上記フィルムは、リードフレーム材に比
べ、熱膨張係数が大きく、フィルムの厚さもリードフレ
ームの板厚と同程度のものが一般的である。具体的に
は、鉄系、銅系のリードフレームの熱膨張係数はそれぞ
れ１０×１０-6、１７×１０-6であるのに対し、例えば
ポリイミドフィルムの熱膨張係数は、２０×１０-6であ
る。また、フィルムの接着温度は、およそ３００℃程度
であるため、ポリイミドフィルムをリードフレームに接
着する際、両者の熱膨張係数の差によって両者の寸法に
差が生じる。その後、フィルムとリードフレームとを常
温まで冷却する際の熱収縮により、フィルムの収縮にリ
ードフレームが耐えられず、両者の接着部分に反りが生
じることがある。この反りが大きいと、半導体チップを
搭載することができなくなり、半導体装置の歩留りが低
下する。The above film generally has a larger coefficient of thermal expansion than a lead frame material, and the thickness of the film is almost the same as the thickness of the lead frame. Specifically, the thermal expansion coefficients of iron-based and copper-based lead frames are 10 × 10 −6 and 17 × 10 −6 , respectively, whereas the thermal expansion coefficient of, for example, a polyimide film is 20 × 10 −6. It is. Further, since the bonding temperature of the film is about 300 ° C., when the polyimide film is bonded to the lead frame, a difference occurs between both dimensions due to a difference in thermal expansion coefficient between the two. Thereafter, due to thermal shrinkage when the film and the lead frame are cooled to room temperature, the lead frame cannot withstand the shrinkage of the film, and a warp may occur in the bonded portion between the two. If the warpage is large, it becomes impossible to mount a semiconductor chip, and the yield of the semiconductor device is reduced.

【０００４】そこで、図２に示されるような、半導体装
置用リードフレームが提案されている（特願昭６３−２
５９８８６号）。この半導体装置用リードフレームに
は、複数の切込み４が設けられたポリイミド等のフィル
ム３が用いられている。この切込み４が入ったフィルム
３を用いることにより、熱収縮により反りが生じる部分
の断面積を減少させてフィルムの収縮力を低下させ、フ
ィルムの反りを防止することができる。Therefore, a lead frame for a semiconductor device as shown in FIG. 2 has been proposed (Japanese Patent Application No. Sho 63-2).
No. 59886). This semiconductor device lead frame uses a film 3 such as polyimide provided with a plurality of cuts 4. By using the film 3 having the cuts 4, it is possible to reduce the cross-sectional area of a portion where warping occurs due to heat shrinkage, reduce the shrinking force of the film, and prevent warping of the film.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、上記半
導体用リードフレームは、フィルムに単に切込みを入れ
ただけなので、フィルムの長さとほぼ等しい長さのバス
バーを有する半導体装置用リードフレームに適用する
と、十分フィルムの収縮力を吸収することができず、更
に、切込みの周囲にしわが発生するという問題があっ
た。However, since the above-mentioned lead frame for a semiconductor is simply formed by cutting a film, if it is applied to a lead frame for a semiconductor device having a bus bar having a length substantially equal to the length of the film, it is sufficient. There is a problem in that the film cannot absorb the contraction force of the film, and further, wrinkles are generated around the cuts.

【０００６】また、上記半導体用リードフレームに半導
体チップを接着し、これらをパッケージに収納した場
合、フィルムから発生する水蒸気を含むガスにより、パ
ッケージクラックが起きる虞がある。Further, when a semiconductor chip is bonded to the semiconductor lead frame and stored in a package, a gas containing water vapor generated from the film may cause a package crack.

【０００７】したがって、本発明の目的は、フィルムの
長さとほぼ等しい長さのバスバーを有する半導体装置用
リードフレームに適用しても、フィルムの反りやしわが
発生せず、かつ、パッケージクラックが発生する虞がな
い半導体装置用リードフレームを提供することにある。Accordingly, even if the object of the present invention is applied to a lead frame for a semiconductor device having a bus bar having a length substantially equal to the length of the film, the film does not warp or wrinkle and package cracks occur. An object of the present invention is to provide a lead frame for a semiconductor device, which does not have a possibility of performing the operation.

【０００８】[0008]

【課題を解決するための手段】本発明は、上記課題を解
決するため、所定の幅にわたって並列配置された複数の
インナーリードと、複数のインナーリードの前方に位置
し、上記所定の幅より大きい幅にわたって伸びるバスバ
ーと、複数のインナーリードの個々の先端部及びバスバ
ーにそれぞれ独立して設けられた半導体チップ搭載用の
接着性フィルムより構成されることを特徴とする半導体
装置用リードフレームを提供する。In order to solve the above-mentioned problems, the present invention has a plurality of inner leads arranged in parallel over a predetermined width, and a plurality of inner leads positioned in front of the plurality of inner leads and larger than the predetermined width. providing a bus bar extending across the width, a plurality of inner leads of the respective tip and the semiconductor device lead frame, characterized in that it is composed of an adhesive film of independent semiconductor chip mounting which is provided on the bus bar .

【０００９】なお、上記接着性フィルムは、インナーリ
ード及びバスバーの個々の導体幅と少なくとも等しい幅
を有するように形成することが望ましい。It is desirable that the adhesive film is formed to have a width at least equal to the width of each conductor of the inner lead and the bus bar.

【００１０】[0010]

【作用】接着性フィルムとの接着面積が大きいバスバー
においては、接着面積が小さいリードの先端部と比べ
て、接着性フィルムの熱膨張・収縮による反りの影響が
大きい。そこで、本発明の半導体装置用リードフレーム
では、複数のインナーリード及びバスバーにそれぞれ独
立した半導体チップ搭載用の接着性フィルムを設けるこ
とにより、接着面積が大きく反りが発生しやすいバスバ
ーでのフィルムの収縮力による影響をインナーリード側
へ伝えないようにすることができる。また、インナーリ
ードにおいても、その先端部にそれぞれ独立して接着性
フィルムを設けることにしたので、他の部分へ反りによ
る影響を与えることがない。更に、フィルムが接着され
る部分が小さくなり、フィルムの反りの影響が小さくな
る。In a bus bar having a large adhesive area with an adhesive film, the influence of warpage due to thermal expansion and contraction of the adhesive film is greater than that of a lead portion having a small adhesive area. Therefore, in the semiconductor device lead frame of the present invention, by providing independent adhesive films for mounting semiconductor chips on the plurality of inner leads and the bus bar, respectively, the adhesive area is large and the film shrinks on the bus bar where warpage is likely to occur. The influence of the force can be prevented from being transmitted to the inner lead side. In addition, since the adhesive films are independently provided at the tips of the inner leads, warping does not affect other portions. Further, the portion where the film is bonded becomes smaller, and the influence of the warpage of the film is reduced.

【００１１】また、個々のインナーリード及びバスバー
にそれぞれ独立して接着性フィルムを設けることにした
ので、使用されるフィルム自体が減少し、フィルムから
発生する水蒸気を含むガスを減少させることができる。In addition, since the adhesive film is provided independently for each of the inner leads and the bus bars, the number of films used is reduced, and the gas containing water vapor generated from the films can be reduced.

【００１２】[0012]

【実施例】以下に、本発明の一実施例を図面を参照にし
つつ詳細に説明する。図１には、本実施例の半導体装置
用リードフレームが示されている。図１に示される半導
体装置用リードフレームは、ＬＯＣ構造リードフレーム
であって、インナーリード１と、バスバー２と、フィル
ム３とから構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a semiconductor device lead frame according to the present embodiment. The semiconductor device lead frame shown in FIG. 1 is a LOC structure lead frame, and includes an inner lead 1, a bus bar 2, and a film 3.

【００１３】フィルム３は、インナーリード１及びバス
バー２にそれぞれ独立して設けられる。このフィルム２
は、絶縁性のものであって半導体チップを搭載すること
ができる程度の強度を有するものであれば良く、例え
ば、ポリイミド、フッ素樹脂、エポキシ樹脂、ＦＲＰ等
からなるものである。フィルム３の貼り付け箇所は、半
導体チップ搭載部のインナーリード１及びバスバー２上
であることが望ましいが、インナーリード１及びバスバ
ー２から０．１ｍｍ程度はみ出す範囲までであれば許容
される。フィルム３とインナーリード１及びバスバー２
とを接着するために用いられる接着剤としては、例え
ば、耐熱温度３５０℃程度のポリイミド系、ポリエーテ
ルアミド系等の高温型接着剤を挙げることができる。The film 3 is provided independently on the inner lead 1 and the bus bar 2. This film 2
Is an insulating material having a strength enough to mount a semiconductor chip, and is made of, for example, polyimide, fluororesin, epoxy resin, FRP, or the like. It is desirable that the film 3 is attached on the inner lead 1 and the bus bar 2 of the semiconductor chip mounting portion, but it is permissible as long as the film 3 protrudes from the inner lead 1 and the bus bar 2 by about 0.1 mm. Film 3, inner lead 1, and bus bar 2
Examples of the adhesive used for bonding the adhesive include a high-temperature adhesive such as a polyimide-based or polyetheramide-based adhesive having a heat resistance temperature of about 350 ° C.

【００１４】本実施例の半導体装置用リードフレームの
製造法の一例を簡単に説明する。まず、例えばポリイミ
ド系の接着剤をフィルムに塗布し、このフィルムをイン
ナーリード１及びバスバー２に合った大きさに切断す
る。そして、予めリードフレームを上記接着剤が溶融す
る程度の温度まで加熱しておき、インナーリード１及び
バスバー３上に切断されたフィルムを押し付け、接着剤
をリードフレームの温度で溶融させてフィルム３を接着
させる。その後、フィルム３上に半導体チップを接着
し、ワイヤボンディング、モールド等が行われる。An example of a method for manufacturing a lead frame for a semiconductor device according to this embodiment will be briefly described. First, for example, a polyimide-based adhesive is applied to a film, and the film is cut into a size suitable for the inner lead 1 and the bus bar 2. Then, the lead frame is heated in advance to a temperature at which the adhesive melts, the cut film is pressed onto the inner lead 1 and the bus bar 3, and the adhesive is melted at the temperature of the lead frame to melt the film 3. Adhere. Thereafter, a semiconductor chip is bonded onto the film 3 and wire bonding, molding, and the like are performed.

【００１５】従来技術の欄で説明したように、フィルム
３はリードフレームより熱膨張係数が大きい。しかし、
本実施例では、インナーリード１及びバスバー２には、
それぞれ独立してフィルム３が設けられるため、他の部
分でのフィルムの反りによる影響を受けることがない。
特に、接着面積が大きく、フィルム３の反りが発生し易
いバスバー２の部分でのフィルム３の反りの影響をイン
ナーリード１のフィルム３が受けることがない。As described in the section of the prior art, the film 3 has a larger coefficient of thermal expansion than the lead frame. But,
In the present embodiment, the inner lead 1 and the bus bar 2 include:
Since the films 3 are provided independently of each other, the film 3 is not affected by the warpage of the film in other portions.
In particular, the film 3 of the inner lead 1 is not affected by the warpage of the film 3 in the portion of the bus bar 2 where the adhesive area is large and the warpage of the film 3 is likely to occur.

【００１６】[0016]

【発明の効果】以上のように、本発明の半導体装置用リ
ードフレームによれば、複数のインナーリードの個々の
先端部及びバスバーにそれぞれ独立して接着性フィルム
を設けることにしたため、フィルムの長さとほぼ等しい
長さのバスバーを有する半導体装置用リードフレームに
適用しても、フィルムの反りやしわの発生を防止するこ
とができる。As it is evident from the foregoing description, according to the lead frame for a semiconductor device of the present invention, a plurality of inner leads of the individual
Since it decided to respective tip and the bus bar independently provided adhesive film, even when applied to a semiconductor device lead frame having a length substantially equal to the bus bar and the length of the film, preventing the occurrence of warpage or wrinkles of the film can do.

【００１７】また、複数のインナーリードの個々の先端
部及びバスバーにそれぞれ独立して接着性フィルムを設
けることにして、使用されるフィルムの量を減少させた
ため、フィルムから発生する水蒸気を含むガスの発生量
が減少し、パッケージクラックが減少する。[0017] Further , each tip of a plurality of inner leads is provided.
And that independently the parts and the bus bars providing an adhesive film, due to reduce the amount of film used, the amount of gas containing water vapor generated from the film decreases, package cracks is reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図２】従来の半導体装置用リードフレームを示す平面
図である。FIG. 2 is a plan view showing a conventional semiconductor device lead frame.

【符号の説明】[Explanation of symbols]

１ インナーリード ２ バス
バー ３ フィルム ４ 切込
み1 inner lead 2 bus bar 3 film 4 cut

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−45499（ＪＰ，Ａ) 特開 平６−232324（ＪＰ，Ａ) 特開 平５−218111（ＪＰ，Ａ) 特開 平３−250637（ＪＰ，Ａ) 特開 平６−275771（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 301 H01L 21/52 H01L 23/50──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-45499 (JP, A) JP-A-6-232324 (JP, A) JP-A-5-218111 (JP, A) JP-A-3-3 250637 (JP, A) JP-A-6-277577 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 301 H01L 21/52 H01L 23/50

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】所定の幅にわたって並列配置された複数の
インナーリードと、 前記複数のインナーリードの前方に位置し、前記所定の
幅方向へ伸び、かつ、前記所定の幅より長いバスバー
と、 前記複数のインナーリードの個々の先端部及び前記バス
バーにそれぞれ独立して設けられた半導体チップ搭載用
の接着性フィルムより構成されることを特徴とする半導
体装置用リードフレーム。A plurality of inner leads arranged in parallel over a predetermined width; a bus bar located in front of the plurality of inner leads and extending in the predetermined width direction and longer than the predetermined width; individual tip and the semiconductor device lead frame, characterized in that it is composed of the adhesive film for a semiconductor chip mounting provided independently to the bus bar of the plurality of inner leads. 【請求項２】前記接着性フィルムは、前記インナーリー
ド及び前記バスバーの個々の導体幅と少なくとも等しい
幅を有する請求項１記載の半導体装置用リードフレー
ム。2. The lead frame for a semiconductor device according to claim 1, wherein said adhesive film has a width at least equal to the width of each conductor of said inner lead and said bus bar.
JP29749893A 1993-11-02 1993-11-02 Lead frame for semiconductor device Expired - Fee Related JP2823064B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29749893A JP2823064B2 (en) 1993-11-02 1993-11-02 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29749893A JP2823064B2 (en) 1993-11-02 1993-11-02 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH07130944A JPH07130944A (en) 1995-05-19
JP2823064B2 true JP2823064B2 (en) 1998-11-11

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Application Number Title Priority Date Filing Date
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JP (1) JP2823064B2 (en)

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KR100475340B1 (en) * 1997-07-08 2005-05-27 삼성전자주식회사 Lead-on Chip Package

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