JPH07130944A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH07130944A
JPH07130944A JP29749893A JP29749893A JPH07130944A JP H07130944 A JPH07130944 A JP H07130944A JP 29749893 A JP29749893 A JP 29749893A JP 29749893 A JP29749893 A JP 29749893A JP H07130944 A JPH07130944 A JP H07130944A
Authority
JP
Japan
Prior art keywords
film
lead frame
semiconductor device
bus bar
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29749893A
Other languages
Japanese (ja)
Other versions
JP2823064B2 (en
Inventor
Kenichi Kaneko
健一 金子
Toshio Kawamura
敏雄 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP29749893A priority Critical patent/JP2823064B2/en
Publication of JPH07130944A publication Critical patent/JPH07130944A/en
Application granted granted Critical
Publication of JP2823064B2 publication Critical patent/JP2823064B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent warps or wrinkles from occurring in a film and cracks from occurring in a package even by application to a lead frame of a semiconductor device having a bus bar as nearly long as the film. CONSTITUTION:This lead frame is formed out of a plurality of inner leads 1 parallely arranged over a predetermined width, bus bars 2 located in front of the plurality of inner leads 1 and extending over a width larger than a predetermined one, and chip-mounting adhesive films 3 provided independently over the plurality of inner leads 1 and bus bars 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置用リードフ
レームに関し、特に、リードフレームと半導体チップと
の間にフィルムが接着された半導体装置用リードフレー
ムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device lead frame, and more particularly to a semiconductor device lead frame in which a film is bonded between a lead frame and a semiconductor chip.

【０００２】[0002]

【従来の技術】リードフレームには、インナーリードの
ブレによるボンディングミスの防止、ボンディングワイ
ヤとベッドとの短絡防止、或いはリードの変形を防止す
るため、半導体チップとの接着の前に、例えば、ポリイ
ミド等のフィルムが貼り付けられる。フィルムをリード
フレームに貼り付けるには、予め、例えば熱可塑性接着
剤等を塗布しておき、高温に熱せられたリードフレーム
上にこのフィルムを押し付け、接着剤をリードフレーム
の温度で溶融させてフィルムをリードフレームに接着さ
せる。2. Description of the Related Art In order to prevent a bonding error due to a blur of an inner lead, a short circuit between a bonding wire and a bed, or a deformation of a lead, a lead frame is made of, for example, polyimide before being bonded to a semiconductor chip. Etc. film is attached. To attach the film to the lead frame, for example, apply a thermoplastic adhesive in advance, press this film on the lead frame heated to a high temperature, melt the adhesive at the temperature of the lead frame, and To the lead frame.

【０００３】上記フィルムは、リードフレーム材に比
べ、熱膨張係数が大きく、フィルムの厚さもリードフレ
ームの板厚と同程度のものが一般的である。具体的に
は、鉄系、銅系のリードフレームの熱膨張係数はそれぞ
れ１０×１０-6、１７×１０-6であるのに対し、例えば
ポリイミドフィルムの熱膨張係数は、２０×１０-6であ
る。また、フィルムの接着温度は、およそ３００℃程度
であるため、ポリイミドフィルムをリードフレームに接
着する際、両者の熱膨張係数の差によって両者の寸法に
差が生じる。その後、フィルムとリードフレームとを常
温まで冷却する際の熱収縮により、フィルムの収縮にリ
ードフレームが耐えられず、両者の接着部分に反りが生
じることがある。この反りが大きいと、半導体チップを
搭載することができなくなり、半導体装置の歩留りが低
下する。The above film has a thermal expansion coefficient larger than that of the lead frame material, and the thickness of the film is generally the same as the plate thickness of the lead frame. Specifically, while the thermal expansion coefficients of iron-based and copper-based lead frames are 10 × 10 −6 and 17 × 10 −6 , for example, the thermal expansion coefficient of a polyimide film is 20 × 10 −6. Is. Further, since the bonding temperature of the film is about 300 ° C., when the polyimide film is bonded to the lead frame, a difference in thermal expansion coefficient between the two causes a difference in both dimensions. After that, due to heat shrinkage when the film and the lead frame are cooled to room temperature, the lead frame may not be able to withstand the shrinkage of the film, and a warp may occur at the bonding portion between the two. If this warp is large, it becomes impossible to mount a semiconductor chip, and the yield of semiconductor devices decreases.

【０００４】そこで、図２に示されるような、半導体装
置用リードフレームが提案されている（特願昭６３−２
５９８８６号）。この半導体装置用リードフレームに
は、複数の切込み４が設けられたポリイミド等のフィル
ム３が用いられている。この切込み４が入ったフィルム
３を用いることにより、熱収縮により反りが生じる部分
の断面積を減少させてフィルムの収縮力を低下させ、フ
ィルムの反りを防止することができる。Therefore, a lead frame for a semiconductor device as shown in FIG. 2 has been proposed (Japanese Patent Application No. 63-2).
59886). A film 3 made of polyimide or the like having a plurality of cuts 4 is used for the lead frame for a semiconductor device. By using the film 3 having the notches 4, it is possible to reduce the cross-sectional area of the portion where warpage occurs due to heat shrinkage, reduce the shrinkage force of the film, and prevent the warpage of the film.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、上記半
導体用リードフレームは、フィルムに単に切込みを入れ
ただけなので、フィルムの長さとほぼ等しい長さのバス
バーを有する半導体装置用リードフレームに適用する
と、十分フィルムの収縮力を吸収することができず、更
に、切込みの周囲にしわが発生するという問題があっ
た。However, since the above-mentioned semiconductor lead frame is simply cut into the film, it is sufficiently applicable to a semiconductor device lead frame having a bus bar having a length substantially equal to the length of the film. There was a problem that the shrinkage force of the film could not be absorbed and wrinkles were generated around the cut.

【０００６】また、上記半導体用リードフレームに半導
体チップを接着し、これらをパッケージに収納した場
合、フィルムから発生する水蒸気を含むガスにより、パ
ッケージクラックが起きる虞がある。When semiconductor chips are adhered to the semiconductor lead frame and housed in a package, gas containing water vapor generated from the film may cause package cracking.

【０００７】したがって、本発明の目的は、フィルムの
長さとほぼ等しい長さのバスバーを有する半導体装置用
リードフレームに適用しても、フィルムの反りやしわが
発生せず、かつ、パッケージクラックが発生する虞がな
い半導体装置用リードフレームを提供することにある。Therefore, even if the object of the present invention is applied to a lead frame for a semiconductor device having a bus bar having a length substantially equal to the length of the film, the film does not warp or wrinkle and a package crack occurs. An object of the present invention is to provide a lead frame for a semiconductor device that does not have the risk of

【０００８】[0008]

【課題を解決するための手段】本発明は、上記課題を解
決するため、所定の幅にわたって並列配置された複数の
インナーリードと、複数のインナーリードの前方に位置
し、上記所定の幅より大きい幅にわたって伸びるバスバ
ーと、複数のインナーリード及びバスバーに独立して設
けられた半導体チップ搭載用の接着性フィルムより構成
されることを特徴とする半導体装置用リードフレームを
提供する。In order to solve the above-mentioned problems, the present invention has a plurality of inner leads arranged in parallel over a predetermined width and a plurality of inner leads located in front of the inner leads and having a width larger than the predetermined width. Provided is a lead frame for a semiconductor device, which comprises a bus bar extending over a width and a plurality of inner leads and an adhesive film for mounting a semiconductor chip, which is independently provided on the bus bar.

【０００９】なお、上記接着性フィルムは、インナーリ
ード及びバスバーの個々の導体幅と少なくとも等しい幅
を有するように形成することが望ましい。The adhesive film is preferably formed so as to have a width at least equal to the width of each conductor of the inner lead and the bus bar.

【００１０】[0010]

【作用】接着性フィルムとの接着面積が大きいバスバー
においては、接着面積が小さいリードの先端部と比べ
て、接着性フィルムの熱膨張・収縮による反りの影響が
大きい。そこで、本発明の半導体装置用リードフレーム
では、複数のインナーリード及びバスバーにそれぞれ独
立した半導体チップ搭載用の接着性フィルムを設けるこ
とにより、接着面積が大きく反りが発生しやすいバスバ
ーでのフィルムの収縮力による影響をインナーリード側
へ伝えないようにすることができる。また、インナーリ
ードにおいても、その先端部にそれぞれ独立して接着性
フィルムを設けることにしたので、他の部分へ反りによ
る影響を与えることがない。更に、フィルムが接着され
る部分が小さくなり、フィルムの反りの影響が小さくな
る。In a bus bar having a large adhesive area with the adhesive film, the warp due to thermal expansion and contraction of the adhesive film is larger than that of the tip portion of the lead having a small adhesive area. Therefore, in the lead frame for a semiconductor device of the present invention, the plurality of inner leads and the bus bar are provided with independent adhesive films for mounting semiconductor chips, respectively. It is possible to prevent the influence of force from being transmitted to the inner lead side. Further, also in the inner lead, since the adhesive film is independently provided at the tip end portion thereof, the warp does not affect other portions. Further, the portion where the film is bonded becomes smaller, and the influence of the warp of the film becomes smaller.

【００１１】また、インナーリード及びバスバーにそれ
ぞれ独立して接着性フィルムを設けることにしたので、
使用されるフィルム自体が減少し、フィルムから発生す
る水蒸気を含むガスを減少させることができる。Since the inner lead and the bus bar are provided with the adhesive films independently of each other,
The film itself used is reduced and the gas, including water vapor, generated from the film can be reduced.

【００１２】[0012]

【実施例】以下に、本発明の一実施例を図面を参照にし
つつ詳細に説明する。図１には、本実施例の半導体装置
用リードフレームが示されている。図１に示される半導
体装置用リードフレームは、ＬＯＣ構造リードフレーム
であって、インナーリード１と、バスバー２と、フィル
ム３とから構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a lead frame for a semiconductor device of this embodiment. The lead frame for a semiconductor device shown in FIG. 1 is a LOC structure lead frame, and includes an inner lead 1, a bus bar 2, and a film 3.

【００１３】フィルム３は、インナーリード１及びバス
バー２にそれぞれ独立して設けられる。このフィルム２
は、絶縁性のものであって半導体チップを搭載すること
ができる程度の強度を有するものであれば良く、例え
ば、ポリイミド、フッ素樹脂、エポキシ樹脂、ＦＲＰ等
からなるものである。フィルム３の貼り付け箇所は、半
導体チップ搭載部のインナーリード１及びバスバー２上
であることが望ましいが、インナーリード１及びバスバ
ー２から０．１ｍｍ程度はみ出す範囲までであれば許容
される。フィルム３とインナーリード１及びバスバー２
とを接着するために用いられる接着剤としては、例え
ば、耐熱温度３５０℃程度のポリイミド系、ポリエーテ
ルアミド系等の高温型接着剤を挙げることができる。The film 3 is independently provided on the inner lead 1 and the bus bar 2. This film 2
Is an insulating material having a strength sufficient to mount a semiconductor chip, and is made of, for example, polyimide, fluororesin, epoxy resin, FRP or the like. The location where the film 3 is attached is preferably on the inner leads 1 and the busbars 2 of the semiconductor chip mounting portion, but is allowed within a range of about 0.1 mm protruding from the inner leads 1 and the busbars 2. Film 3, inner lead 1 and bus bar 2
Examples of the adhesive used for adhering to and include a high-temperature type adhesive such as a polyimide-based or polyetheramide-based adhesive having a heat-resistant temperature of about 350 ° C.

【００１４】本実施例の半導体装置用リードフレームの
製造法の一例を簡単に説明する。まず、例えばポリイミ
ド系の接着剤をフィルムに塗布し、このフィルムをイン
ナーリード１及びバスバー２に合った大きさに切断す
る。そして、予めリードフレームを上記接着剤が溶融す
る程度の温度まで加熱しておき、インナーリード１及び
バスバー３上に切断されたフィルムを押し付け、接着剤
をリードフレームの温度で溶融させてフィルム３を接着
させる。その後、フィルム３上に半導体チップを接着
し、ワイヤボンディング、モールド等が行われる。An example of a method for manufacturing the lead frame for a semiconductor device of this embodiment will be briefly described. First, for example, a polyimide adhesive is applied to a film, and the film is cut into a size suitable for the inner leads 1 and the bus bar 2. Then, the lead frame is heated in advance to a temperature at which the adhesive is melted, the cut film is pressed onto the inner leads 1 and the bus bar 3, and the adhesive is melted at the temperature of the lead frame to form the film 3. Let it adhere. After that, a semiconductor chip is bonded onto the film 3, and wire bonding, molding, etc. are performed.

【００１５】従来技術の欄で説明したように、フィルム
３はリードフレームより熱膨張係数が大きい。しかし、
本実施例では、インナーリード１及びバスバー２には、
それぞれ独立してフィルム３が設けられるため、他の部
分でのフィルムの反りによる影響を受けることがない。
特に、接着面積が大きく、フィルム３の反りが発生し易
いバスバー２の部分でのフィルム３の反りの影響をイン
ナーリード１のフィルム３が受けることがない。As described in the section of the prior art, the film 3 has a coefficient of thermal expansion larger than that of the lead frame. But,
In this embodiment, the inner lead 1 and the bus bar 2 are
Since the films 3 are provided independently of each other, they are not affected by the warp of the film in other portions.
In particular, the film 3 of the inner lead 1 is not affected by the warp of the film 3 at the portion of the bus bar 2 where the adhesion area is large and the film 3 is easily warped.

【００１６】[0016]

【発明の効果】以上のように、本発明の半導体装置用リ
ードフレームによれば、複数のインナーリード及びバス
バーに独立して接着性フィルムを設けることにしたた
め、フィルムの長さとほぼ等しい長さのバスバーを有す
る半導体装置用リードフレームに適用しても、フィルム
の反りやしわの発生を防止することができる。As described above, according to the lead frame for a semiconductor device of the present invention, since the adhesive film is independently provided on the plurality of inner leads and the bus bar, the length of the film is almost equal to the length of the film. Even when applied to a semiconductor device lead frame having a bus bar, it is possible to prevent the film from warping or wrinkling.

【００１７】また、複数のインナーリード及びバスバー
に独立して接着性フィルムを設けることにして、使用さ
れるフィルムの量を減少させたため、フィルムから発生
する水蒸気を含むガスの発生量が減少し、パッケージク
ラックが減少する。Further, since the adhesive film is independently provided on the plurality of inner leads and the bus bar to reduce the amount of the film used, the amount of gas containing water vapor generated from the film is reduced, Package cracks are reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図２】従来の半導体装置用リードフレームを示す平面
図である。FIG. 2 is a plan view showing a conventional lead frame for a semiconductor device.

【符号の説明】[Explanation of symbols]

１ インナーリード ２ バス
バー ３ フィルム ４ 切込
み1 Inner lead 2 Bus bar 3 Film 4 Notch

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 所定の幅にわたって並列配置された複数
のインナーリードと、 前記複数のインナーリードの前方に位置し、前記所定の
幅方向へ伸び、かつ、前記所定の幅より長いバスバー
と、 前記複数のインナーリード及び前記バスバーに独立して
設けられた半導体チップ搭載用の接着性フィルムより構
成されることを特徴とする半導体装置用リードフレー
ム。1. A plurality of inner leads arranged in parallel over a predetermined width, a bus bar located in front of the plurality of inner leads, extending in the predetermined width direction, and longer than the predetermined width. A lead frame for a semiconductor device, comprising a plurality of inner leads and an adhesive film independently mounted on the bus bar for mounting a semiconductor chip. 【請求項２】 前記接着性フィルムは、前記インナーリ
ード及び前記バスバーの個々の導体幅と少なくとも等し
い幅を有する請求項１記載の半導体装置用リードフレー
ム。2. The lead frame for a semiconductor device according to claim 1, wherein the adhesive film has a width at least equal to a conductor width of each of the inner lead and the bus bar.
JP29749893A 1993-11-02 1993-11-02 Lead frame for semiconductor device Expired - Fee Related JP2823064B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29749893A JP2823064B2 (en) 1993-11-02 1993-11-02 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29749893A JP2823064B2 (en) 1993-11-02 1993-11-02 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH07130944A true JPH07130944A (en) 1995-05-19
JP2823064B2 JP2823064B2 (en) 1998-11-11

Family

ID=17847291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29749893A Expired - Fee Related JP2823064B2 (en) 1993-11-02 1993-11-02 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JP2823064B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100475340B1 (en) * 1997-07-08 2005-05-27 삼성전자주식회사 Lead-on Chip Package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100475340B1 (en) * 1997-07-08 2005-05-27 삼성전자주식회사 Lead-on Chip Package

Also Published As

Publication number Publication date
JP2823064B2 (en) 1998-11-11

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