JPH0876734A - Horizontal synchronizing signal frequency discrimination circuit - Google Patents

Abstract

PURPOSE: To automatically discriminate horizontal synchronizing signal frequency of input video signal. CONSTITUTION: This circuit is provided with an edge detection part 1 outputting an edge signal S2 from a horizontal synchronizing signal S1, a delay circuit 2 delaying the edge signal S2 by a prescribed time, a clock signal generation part 3 generating a clock signal of a prescribed frequency, a counter 4 cleared by the edge signal S3 and counting the clock signal, a first pulse generation part 5 generating a first pulse P1 rising by the initial edge signal S2 and falling when a count arrives at a first count value, a second pulse generation part 6 generating a second pulse P2 rising by the initial edge signal S2 and falling when the count arrives at a second count value less than the first count value and first and second latch circuits 7, 8 latching the P1 or the P2 at the timing of the edge signal S2, and a combination of respective latch circuit outputs D1 and D2 corresponds to the horizontal synchronizing signal frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing signal frequency discriminating circuit, and more particularly, in a display monitor to which a plurality of video signals having different horizontal synchronizing signal frequencies are inputted, the horizontal synchronizing signal frequency is automatically detected. Regarding discrimination.

[0002]

2. Description of the Related Art In a display monitor to which a plurality of video signals having different horizontal synchronizing signal frequencies and the like are input, it is necessary to determine the horizontal frequency in order to switch related circuits according to the horizontal frequency. For example, PDP
In display control of a (plasma display panel) or the like, it is necessary to change the clock frequency division value of the PLL circuit and the timing of a blanking signal as a control signal according to the horizontal synchronizing frequency. Further, in a display using a cathode ray tube, it is necessary to switch the deflection circuit. Due to such a need, several methods have been conventionally used as a method of discriminating the horizontal frequency. For example, there are the following methods. An integrating circuit including a capacitor and a resistor is provided, and the integrating circuit integrates the negative horizontal synchronizing signal.
The higher the horizontal frequency, the lower the integrated output level. On the other hand, a reference voltage for the horizontal frequency is provided,
The same reference voltage and the integrated output are compared by a comparator, and the horizontal frequency is discriminated from this comparison. This discrimination method is an analog method.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a horizontal sync signal frequency discriminating circuit using a digital technique different from the conventional analog method.

[0004]

SUMMARY OF THE INVENTION According to the present invention, an edge detecting section for detecting an edge of an input horizontal synchronizing signal and outputting the edge signal, and a delay for delaying the edge signal from the edge detecting section for a predetermined number of clocks. A circuit, a clock signal generator that generates a clock signal of a predetermined frequency, a counter that is cleared by the edge signal from the delay circuit and counts the clock signal from the clock signal generator, and a first edge from the delay circuit A first pulse generator that generates a first pulse that rises with a signal and falls when the count by the counter reaches a predetermined first count number, and rises with a first edge signal from the delay circuit, When the count by the counter reaches a predetermined second count number different from the first count number, the first count value is lowered. A second pulse generating section for generating a pulse of the second pulse, a first latch circuit for latching the signal from the first pulse generating section at the timing of the edge signal from the edge detecting section, and the second pulse generating section. A second latch circuit for latching a signal from the first latch circuit at the timing of the edge signal from the edge detection unit, and a combination of the output of the first latch circuit and the output of the second latch circuit is a horizontal synchronization signal. A horizontal synchronizing signal frequency discriminating circuit adapted to correspond to a frequency is provided.

[0005]

The edge detector detects the edge of the input horizontal synchronizing signal and outputs the edge signal. The same edge signal is the first
While used as a timing signal for the second and second latch circuits, the delay circuit delays the signal for a predetermined number of clocks and is used as a clear signal for the counter and for raising the pulse of the first and second pulse generators. On the other hand, a clock signal having a predetermined frequency is generated by the clock signal generator. The counter counts while clearing the clock signal with an edge signal from the delay circuit. The first pulse generation unit generates a first pulse that rises at the first edge signal detected by the edge detection unit and falls when the count by the counter reaches the first count number.

The second pulse generation section rises at the first edge signal detected by the edge detection section and falls when the count by the counter reaches the second count number which is smaller than the first count number. To generate. In this case, both pulse generators continue the current rising state in the case where the horizontal frequency does not reach the first count number or the second count number within one cycle of the edge signal. First
The latch circuit latches the signal from the first pulse generator at the timing of the edge signal from the edge detector,
Similarly, the second latch circuit latches the signal from the generator with the second pulse at the timing of the edge signal from the edge detector. As a result, the combination of the output of the first latch circuit and the output of the second latch circuit corresponds to the horizontal synchronizing signal frequency. Further, a horizontal synchronizing signal frequency discriminating signal is obtained by calculating (calculating circuit) the output of the first latch circuit and the output of the second latch circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A horizontal synchronizing signal frequency discriminating circuit according to the present invention will be described below with reference to the drawings. 1 is a block diagram of an essential part showing an embodiment of a horizontal synchronizing signal frequency discriminating circuit according to the present invention, and FIG. 2 is a timing chart for explaining FIG. 1 and the like. The discriminating horizontal frequency is 15 KHz (FIG. A), 24 KHz
(Fig. B) and 31 KHz (Fig. C) are three examples.
In the above, 15 KHz is 15.73 KHz, 24 KHz is 24.37 KHz,
31KHz is an accurate frequency of 31.47 KHz.

In FIG. 1, reference numeral 1 is an edge detecting section for detecting an edge of an input horizontal synchronizing signal S1 and outputting an edge signal S2, and 2 is a delay for delaying the edge signal S2 from the edge detecting section 1 for a predetermined number of clocks. A circuit 3 is a clock signal generator for generating a clock signal of a predetermined cycle, 4 is a counter for counting the clock signal from the clock signal generator 3 while clearing it with an edge signal S3 from the delay circuit 2, and 5 is a delay circuit 2 The first pulse generator 6 generates a first pulse which rises at the first edge signal S3 and falls when the count by the counter 4 reaches a predetermined first count number. Edge signal S3
And the count by the counter 4 is
The second pulse generation unit that generates a second pulse that falls when a predetermined second count number that is smaller than the count number of 1 is reached, and 7 indicates the signal P1 from the first pulse generation unit 5 to the edge detection unit 1. A second latch circuit for latching the signal P2 from the second pulse generator 6 at the timing of the edge signal S2 from the edge detector 1; Reference numeral 9 is an arithmetic circuit for performing an operation based on the output of the first latch circuit 7 and the output of the second latch circuit 8 and outputting a horizontal synchronizing signal frequency discrimination signal.

Next, the operation of the present invention will be described. Edge detection of the horizontal synchronizing signal S1 by the edge detecting unit 1 is classified into four types according to the polarity of the horizontal synchronizing signal. That is, this is a method of detecting the falling edge and the rising edge of the negative polarity synchronizing signal and the falling edge and the rising edge of the positive polarity synchronizing signal, respectively. Each drawing of FIG. 2 shows the case where the input horizontal synchronizing signal S1 has a negative polarity and the trailing edge (symbol a) of the negative synchronizing signal S1 is detected. Hereinafter, each horizontal frequency Fh will be described separately. [1] When the horizontal frequency Fh = 15 KHz [FIG. 2 (A)]. It is assumed that the horizontal synchronizing signal S1 of Fh = 15 KHz is started at time To. The edge detector 1 detects the falling edge from the horizontal synchronizing signal S1 and outputs an edge signal S2. The edge signal S2 is delayed by the delay circuit 2 for a predetermined number of clocks, and the edge signal S3
To get On the other hand, the clock signal generator 3 generates a clock signal having a predetermined cycle. The frequency of the clock signal is sufficiently higher than the frequency of the horizontal synchronizing signal. The clock signal generated by the clock signal generator 3 is counted by the counter 4. The counter 4 is cleared by the edge signal S3, starts counting, and repeats thereafter.

The first pulse generator 5 rises (symbol B) in synchronization with the first edge signal S3, and falls when the count of the counter 4 reaches a predetermined count number (first count number) (symbol). C) Generate the first pulse P1. The pulse width at this time is W1 (μSec), and the following relationship is established with the horizontal frequency Fh. 41.03 μSec <W1 <63.56 μSec ………… (1) Here, 41.03 μSec is 1 / 24.37KHz, and 63.56 μSec
Se is 1 / 15.73 KHz. In addition, the second pulse generator 6
Like the first pulse P1, rises in synchronization with the first edge signal S3 (symbol B), and when the count of the counter 4 reaches a count number (second count number) smaller than the first count number. A second pulse P2 that falls (sign D) is generated. The pulse width at this time is W2 (μSec), and the following relationship is established with the horizontal frequency Fh. 31.78 μSec <W2 <41.03 μSec ………… (2) Here, 31.78 μSec is 1 / 31.47 KHz.

When Fh = 15 KHz, both the first pulse P1 and the second pulse P2 have reached the predetermined counts (first count number and second count number) in the horizontal period Th. After it once falls (C, D), it rises again at the next edge signal S3, and so on. The above-mentioned first pulse P1 and second pulse P2 are respectively the first pulse
Is sent to the latch circuit 7 and the second latch circuit 8. These latch circuits are the edge signals detected by the edge detector 1.
P1 or P2 is latched at the input timing of S2 (symbols E and F), and D1 and D2 are output. The latch outputs at this timing are D1 = L (low level) and D2 = L, respectively.
(Low level). That is, D1 = L, D2 = L is Fh = 15
Represents KHz. Further, a horizontal synchronizing signal frequency discriminating signal representing Fh is obtained by performing an arithmetic operation in the arithmetic circuit 9 based on D1 and D2.

[2] In case of horizontal frequency Fh = 24 KHz [FIG. 2 (B)]. The first and second pulses P1 and P2 rise in the same manner as in the above [1]. On the other hand, as a result of Fh becoming higher, the cycle Th becomes shorter. In this case, the second pulse P2 is W2 from the equation (2).
Since it has a relationship of <41.03 μSec (24 KHz), it has a waveform that once falls (sign G) and then rises again with the next edge signal S3. <Because of the relationship of W1
(High level) Continue the state. Therefore, the latch output D1 of the first latch circuit 7 becomes H, and the second latch circuit 8
Latch output D2 of L becomes L. That is, D1 = H, D2 = L is Fh
= 24 kHz. The operations of the blocks (edge circuit 1, delay circuit 2, clock generator 3, counter 4, arithmetic circuit 9) other than those described above are the same as those in [1] above.

[3] In the case of horizontal frequency Fh = 31 KHz [FIG. 2 (C)]. The rising edges of the first and second pulses P1 and P2 are the same as in the above [1].
And so on. As a result of higher Fh, the cycle Th becomes shorter. In this case, from formulas (1) and (2) above, 31.78
Since μSec (31 KHz) <W1, W2, the first pulse P1,
Both the second pulse P2 does not fall H (high level)
Continue the state. Therefore, the first latch circuit 7 and the second latch circuit 7
The latch outputs D1 and D2 of both the latch circuits 8 become high. That is, D1 = H and D2 = H represent Fh = 31 KHz. still,
Blocks other than those described above (edge circuit 1, delay circuit 2,
The operations of the clock generator, the counter 4, and the arithmetic circuit 9) are the same as in the above item [1].

The above is a description of the case where the horizontal frequency Fh changes from a low frequency to a high frequency. On the contrary, when the horizontal frequency Fh changes from a high frequency to a low frequency, the following is performed.
For example, if Fh = 31KHz now and this becomes Fh = 24KHz, W2 <41.03 μSec after the switching.
A period of (24 KHz) appears. Therefore, the second pulse
P2 falls at that point. However, the first pulse does not fall and remains in the H state. That is, the state is switched to the state shown in FIG. Similarly, when Fh = 31 KHz is changed to Fh = 15 KHz, the state becomes as shown in (A) after switching.
From the above, the latch outputs D1 and D2 for each horizontal frequency Fh are as shown in FIG. 2D, and the discrimination signals corresponding to the same Fh are obtained.

[0015]

As described above, according to the present invention, the horizontal frequency of an input video signal can be automatically determined by digital means. Further, by changing the pulse widths of the first pulse and the second pulse, it is possible to discriminate not only 15 KHz, 24 KHz and 31 KHz taken up in this embodiment but other frequencies.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a horizontal synchronizing signal frequency discriminating circuit according to the present invention.

2 is a timing chart for explaining FIG. 1 (A
~ C) and latch output for horizontal frequency Fh (D1, D
It is a correlation diagram (D) of 2).

[Explanation of symbols]

 1 Edge Detection Section 2 Delay Circuit 3 Clock Signal Generation Section 4 Counter 5 First Pulse Generation Section 6 Second Pulse Generation Section 7 First Latch Circuit 8 Second Latch Circuit 9 Arithmetic Circuit S1 Horizontal Sync Signal S2 Edge Signal S3 Edge signal P1 First pulse P2 Second pulse D1 First latch circuit output D2 Second latch circuit output

Claims (7)

[Claims] 1. An edge detection unit that detects an edge of an input horizontal synchronizing signal and outputs an edge signal, a delay circuit that delays the edge signal from the edge detection unit for a predetermined number of clocks, and a clock signal of a predetermined frequency. A counter for counting the clock signal from the clock signal generator and a counter that is cleared by the edge signal from the delay circuit and a rising edge at the first edge signal from the delay circuit and counted by the counter. The first pulse generation unit that generates a first pulse that falls when a predetermined first count number is reached and a first edge signal from the delay circuit, and the counter counts the first pulse. A second pulse which falls when a predetermined second count number different from the count number of is reached. A pulse generator, a first latch circuit that latches the signal from the first pulse generator at the timing of the edge signal from the edge detector, and the signal from the second pulse generator to the edge detector. A second latch circuit for latching at the timing of the edge signal from the section, and the combination of the output of the first latch circuit and the output of the second latch circuit is made to correspond to the horizontal synchronizing signal frequency. Horizontal sync signal frequency discriminating circuit. 2. An arithmetic circuit for performing an arithmetic operation based on an output of the first latch circuit and an output of the second latch circuit and outputting a horizontal synchronizing signal frequency discrimination signal. A horizontal synchronizing signal frequency discriminating circuit according to item 1. 3. The horizontal sync signal frequency discriminating circuit according to claim 1, wherein the edge detection in the edge detection unit is performed by detecting a trailing edge of a negative polarity horizontal sync signal. 4. The horizontal synchronizing signal frequency discriminating circuit according to claim 1, wherein the edge detecting section detects an edge of the negative horizontal synchronizing signal. 5. The horizontal synchronizing signal frequency discriminating circuit according to claim 1, wherein the edge detecting section detects the rising edge of the positive horizontal synchronizing signal. 6. The horizontal synchronizing signal frequency discriminating circuit according to claim 1, wherein the edge detecting section detects the falling edge of the positive horizontal synchronizing signal. 7. The horizontal synchronizing signal frequency discriminating circuit according to claim 1, wherein each of the first latch circuit and the second latch circuit comprises a flip-flop.