JPH087162B2 - Defect data acquisition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention detects the type of defect, the size of the defect and the position of the defect of a defect data capturing circuit of a defect detection device, particularly a transparent plate such as a glass plate. The present invention relates to a defect data acquisition circuit of an identification type defect detection device capable of performing the above.

[Conventional technology]

When manufacturing a transparent plate such as a glass plate, the types of defects (defects) present in the transparent plate (foreign matter, bubbles, humps, drip etc.),
As a device for detecting the size of the defect and the position of the defect, there is a flying spot type identification type defect detection device.

An outline of an example of the identification type defect detection device developed by the present applicant is shown in FIG. In this identification type defect detection device, a laser beam from a laser light source 1 is incident on a polygonal rotary mirror 2 to scan a laser spot on a glass plate 3 flowing through a manufacturing process line. The scanning direction is a direction perpendicular to the flowing direction of the glass plate (Y-axis direction), that is, the width direction of the glass plate (X-axis direction). The laser light is obliquely incident on the surface of the glass plate 3. This is to avoid interference between the light reflected from the front surface of the glass plate and the light reflected from the back surface of the glass plate.

The transmitted light, the transmitted scattered light, and the reflected light of the laser light incident on the glass plate 3 are received by the light receivers D1, D2, D3, D4, D5 having a light receiving surface elongated in the width direction of the glass plate. Each of these light receivers is configured by arranging a large number of glass fibers. The light receiver D1 receives the transmitted light, the light receiver D2 receives the paraxial transmitted scattered light, the light receivers D3 and D4 receive the far axial transmitted scattered light, and the light receiver D5 receives the reflected light. The glass fibers that make up each photoreceiver are the corresponding photomultiplier tubes PM1, PM2, PM3, PM4, PM.
The light guided to 5 and received is converted into an electric signal by each photomultiplier tube. In the signal processing circuit 4, signal processing such as differentiation processing, width processing, comparison processing, and waveform shaping is applied to these electric signals to create defect data D ₁₁ , D ₁₂ , ..., D ₅₂ . There are a plurality of types of defect data, for example, the defect data D ₁₁ is a differential detection waveform obtained by negatively differentiating the electric signal obtained by photoelectrically converting the transmitted light received by the light receiver D 1 as a predetermined detection level. It is data showing a comparison result of comparison.

For convenience of description below, the configuration up to the signal processing circuit 4 will be described.
The defect detector 5 is used. The defect data from the defect detector 5 is fetched by the defect data fetching circuit 6 and subjected to signal processing, and then sent to the central processing unit (CPU) 7. In the CPU 7, a defect pattern is created from the defect data and collated with a defect identification pattern table stored in advance to determine the defect type, size, etc.

The present invention relates to an improvement of the defect data capturing circuit in such an identification type defect detection device, but the present invention is not intended only for the identification type defect detection device described above, but is of a flying spot type. If so, any type of identification type defect detection device can be targeted. Further, the reflected and scattered light may be further added to the light for detecting the change in the light amount.

The present applicant has already proposed a circuit having the configuration shown in FIG. 10 for such a defect data acquisition circuit.

The previously proposed defect data acquisition circuit 10 includes an X-axis counter 11, an OR unit 12, a frequency dividing circuit 13, and a Y-axis counter.
14 and a FIFO memory 15. X-axis counter 11
Is a counter that counts a clock CLK for X-coordinate division, and is reset by a start pulse ST that is a scanning start signal. The start pulse ST is obtained by extracting the laser light reflected by the polygonal rotary mirror 2 of the defect detector 5 at a specific position with a glass fiber, performing photoelectric conversion, and shaping the waveform. The X-axis counter 11 outputs the count value when the defect data is taken in as X coordinate position data.

The OR unit 12 is a unit for accumulating defect data for a plurality of scans from the defect detector 5 and outputting the defect data at a predetermined timing.
It is disclosed in Japanese Unexamined Patent Publication No. 56-39419, “Defect Detection Device”. The purpose of this OR unit 12 is in relation to the processing speed of the CPU 7,
It is to improve the processing capability of the identification type defect detection device.

The frequency dividing circuit 13 frequency-divides the line synchronization signal PG corresponding to the moving distance of the glass plate in the line direction and inputs the frequency-divided signal to the OR unit 12. The OR unit 12 outputs the divided line sync signal.
The accumulated defect data is output at the timing of PG.

The Y-axis counter 14 counts the frequency-divided line synchronization signal PG from the frequency dividing circuit 13, and outputs the count value to the FIFO memory 15 as Y-coordinate position data when the defect data is input. The Y-axis counter 14 is reset by software.

The FIFO memory 15 includes X coordinate position data from the X axis counter 11, defect data from the OR unit 12, and Y axis counter 14.
The Y coordinate position data from is temporarily stored. And FIFO
Defect data and defect position data (X, Y) from memory 15
Is transferred to the memory of CPU7 by direct memory access (DMA).

In the defect data fetch circuit having such a configuration, the data obtained as a result of the processing in the OR unit 12 is transferred to the CPU 7 as the minimum processing unit via the FIFO memory 15.

However, in such a method, a plurality of defect data may be output from the OR unit 12 for one defect of the glass plate, and although the CPU 7 has one defect,
There is a problem in that it is necessary to process a plurality of defect data, and the software processing of the CPU is burdened.

Further, the defect data D ₁₁ , D ₁₂ , ..., D ₅₂ output from the defect detector 5 based on the change in the amount of light detected by each of the light receivers D1, D2, D3, D4, D5 is one. However, when scanned by a laser spot, the defects are not necessarily output at the same timing. In such a case, it is necessary to recognize that the defect data whose generation timings are shifted is the defect data from one defect.

It is an object of the present invention to provide a defect data fetching circuit that solves such problems.

[Structure of Invention]

According to the present invention, a transparent plate running in the length direction is scanned with a light spot in the width direction, and based on a combination of light amount changes of any one of transmitted light, transmitted scattered light, reflected light, and reflected scattered light. In the defect data acquisition circuit of the identification type defect detection device for detecting the type, size, position, etc. of the defect, the first pulse train related to the position of the transparent plate in the width direction is counted, and the defect data is acquired. A first counter that outputs a count value when the second pulse train that counts the second pulse train related to the position of the transparent plate in the lengthwise direction, and a second counter that outputs the count value when the defect data is captured. A counter, an OR unit that accumulates OR processing defect data for a plurality of scans, and outputs the processed defect data at the pulse generation timing of the second pulse train; and compresses the defect data from the OR unit, Compressed defect day And a continuity determining circuit for determining the continuity of the data in the length direction and the continuity in the width direction and synthesizing the data into a defect data block.

〔Example〕

 Examples of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of the present invention. The defect data is the defect detector 5 shown in FIG.
Shall be input from. This defect data acquisition circuit
20 is the defect data acquisition circuit shown in FIG.
A continuous determination circuit 21 is added after the X-axis counter 11, the OR unit 12, and the Y-axis counter 14.

FIG. 2 shows an example of the OR unit 12. This OR unit
12, a plurality of types of flaw data D _11, D _12, · · ·, respectively corresponding to D _52, the OR circuit OR _11, OR _12, · · ·, OR
₅₂ and random access memory RAM ₁₁ , RAM ₁₂ , ...
RAM ₅₂ and gate circuits G ₁₁ , G ₁₂ , ..., G ₅₂ .

FIGS. 3 and 4 are diagrams for helping understanding of the operation of the OR unit 12, and FIG. 3 shows scanning by the laser spot, clock CLK, and line synchronization signal PG after frequency division.
FIG. 4 is a schematic diagram showing the relationship with the above, and FIG. 4 is a diagram showing a state of being filled with defect data D _{11 in} the RAM ₁₁ of the OR unit. With reference to these drawings, the defect data as an example in the OR unit 12
The operation of accumulating D ₁₁ will be described. It is assumed that the glass plate is scanned n times in the X-axis direction by the laser spot during the line synchronization signal PG after frequency division. It is also assumed that each RAM of the OR unit 12 has addresses up to 1000. The address of each RAM corresponds to what number clock the clock CLK is.

Now, as shown in FIG. 3, when the glass plate 3 has a defect 35, the defect data D ₁₁ input from the defect detector 5 in the first scanning is written in the RAM ₁₁ , and the bit “1” is set at the addresses 502 and 503. "Is standing. Flaw data D ₁₁ that has been entered in the second scanning after the OR is taken in flaw data and the logical OR circuit OR ₁₁ read from the RAM _11, is re-written to RAM _11, the n-th ... Defect data D input by scanning
₁₁ is the defect data read from the RAM ₁₁ and the OR circuit O
After being ORed in R ₁₁ , it is rewritten in RAM ₁₁ ,
Finally, the bit “1” is stored in the addresses 501 to 504. The defect data D ₁₁ stored in the RAM ₁₁ in this way is the line synchronization signal PG divided by the divider circuit 13.
It is output to the continuous determination circuit 21 through the gate circuit G ₁₁ at the timing of.

The data from the OR unit 12 is the minimum processing unit described above, and the region on the glass plate 3 corresponding to this minimum processing unit is shown in FIG. That is, the area that constitutes this minimum processing unit is the pulse interval of the clock CLK in the X-axis direction,
The Y-axis direction corresponds to the pulse interval of the line synchronization signal PG after frequency division.

FIG. 6 is a block diagram showing an example of the continuity determination circuit 21 of FIG. The continuity determination circuit 21 determines the continuity of the compressed defect data in the X-axis direction with the defect data compression unit 41 that compresses the defect data from the OR unit 12 and outputs the type of the compressed defect data. X-axis continuity determination unit 42 that outputs the start address and end address in the X-axis direction.
And a Y-axis continuity determination unit 43 that determines the continuity of the compressed defect data in the Y-axis direction and outputs the Y-axis direction start address and end address.

Now, the operation of the continuous determination circuit 21 having such a configuration will be described with reference to FIGS. 7 and 8. Figure 7 shows
FIG. 8 is a diagram for conceptually explaining the operation of the defect data compression unit 41 for compressing defect data, and FIG. 8 is a diagram for explaining the operation of the X-axis continuity determination unit 42 and the Y-axis continuity determination unit 43 after compression. 5 is a diagram showing an example of a bit array of defect data of FIG.

From the OR unit 12, defect data D ₁₁ , D ₁₂ ,
.., _D52 are output, but as shown in FIG. 7, the defect data for each type has a two-dimensional bit array in the X-axis address and Y-axis address directions. now,
Considering a three-dimensional space, these two-dimensional array defect data
Assuming that D ₁₁ , D ₁₂ , ..., D ₅₂ are arranged in the Z-axis direction, a three-dimensional defect data group from the OR unit 12
It can be considered that D ₁₁ , D ₁₂ , ..., D ₅₂ are output. The defect data compression unit 41 is a three-dimensional defect data group.
D ₁₁ , D ₁₂ , ..., D ₅₂ are ORed with all the defect data in the Z-axis direction in correspondence with the X-axis address and the Y-axis address to form a compressed two-dimensional defect data DB. FIG. 7 shows an example in which the bit “1” is set only in the defect data D ₁₁ and the defect data D ₅₂ .

FIG. 8 shows an example of a bit array of defect data compressed based on the above idea.

The X-axis continuity determination unit 42 and the Y-axis continuity determination unit 43 respectively check the continuity of the bit "1" in the X-axis direction and the Y-axis direction, and detect the interruption of the bit "1". It is determined whether or not to connect in the X-axis direction and the Y-axis direction based on the parameter for the detected break.

FIG. 8 (a) shows a defect data block synthesized by the continuous determination when the parameters of the X-axis continuous determination section 42 and the Y-axis continuous determination section 43 are both 0. X-axis continuity determination unit 42
From this, 500 is output as the X-axis start address and 503 is output as the X-axis end address of this defect data block. On the other hand, the Y-axis continuity determining unit 43 outputs address 100 as the Y-axis start address and address 103 as the Y-axis end address of the defect data block.

FIG. 8B shows a defect data block synthesized by the continuous determination when the parameters of the X-axis continuous determination section 42 and the Y-axis continuous determination section 43 are both 1. If the parameter is 1, even if there is a discontinuity of bit "1" in one address, they are combined and a defective data block as shown is synthesized. In this case, from the X-axis continuity determination unit 42, the 500th address as the X-axis start address of this defect data block is
Address 503 is output as the X-axis end address. On the other hand, from the Y-axis continuity determination unit 43, Y of the defect data block
Address 101 is output as the axis start address and address 103 is output as the Y axis end address. In this way, by performing the continuous determination of interpolating the discontinuity of the bit “1” and combining, when one defect is scanned by the laser spot, the timing of generation of defect data from a plurality of light receivers is deviated. In such a case, it is possible to recognize these as defect data from one defect.

When the continuity of the bit “1” is interrupted, the Y-axis continuity determination unit 43 sets the type of the compressed defect data from the defect data compression unit 41 as X defect information indicating the defect type and size. The axis continuity determination unit 42 and the Y axis continuity determination unit 43 output the start address, end address and start address, end address in the Y axis direction of the defect data block to the FIFO memory 15 as defect position information. The Y-axis continuity determination unit 43 has a function of forcibly cutting off the bit "1" continuity in the Y-axis direction for a predetermined length and outputting the defect information and the position information to the FIFO.

As described above, according to the defect data fetching circuit of the present embodiment, the defect data output from the OR unit is compressed, and the X-axis continuous judgment and the Y-axis continuous judgment are performed on the compressed defect data, and 1 Aggregate into individual defect data blocks,
Since the defect information and position information about this defect data block are fetched into the FIFO memory 15, the CPU
It is possible to reduce the amount of information sent to.

〔The invention's effect〕

As described above, according to the defect data acquisition circuit of the present invention, the actual number of defects of the transparent plate and the number of processings by the CPU can be made to coincide with each other. It is possible to shorten the processing time of the CPU.

Further, by performing the continuous determination, even if the generation timing of the defect data from each light receiver is deviated, it can be recognized that the defect data is from one defect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the OR unit of FIG. 1, and FIGS. 3 and 4 explain the operation of the OR unit. FIG. 5, FIG. 5 is a diagram for explaining the minimum processing unit, FIG. 6 is a block diagram showing an example of the continuity determination circuit of FIG. 1, and FIGS. 7 and 8 are FIG. FIG. 9 is a block diagram showing the outline of the identification type defect detection device, and FIG. 10 is a block diagram showing a previously proposed defect data fetching circuit. 1 …… Laser light source 2 …… Polygonal rotating mirror 3 …… Glass plate 4 …… Signal processing circuit 5 …… Fault detector 6,10,20 …… Fault data acquisition circuit 7 …… CPU 11 …… X-axis counter 12 …… OR unit 13 …… Division circuit 14 …… Y axis counter 15 …… FIFO memory 21 …… Continuous judgment circuit 41 …… Defect data compression section 42 …… X axis continuous judgment section 43 …… Y axis continuous judgment Department

Claims (2)

[Claims] 1. A transparent plate running in the length direction is scanned with a light spot in the width direction, and based on a combination of changes in the light amount of any one of transmitted light, transmitted scattered light, reflected light, and reflected scattered light. In the defect data acquisition circuit of the identification type defect detection device for detecting the type, size, position, etc. of the defect, the first pulse train related to the position of the transparent plate in the width direction is counted, and the defect data is acquired. A first counter that outputs a count value when the defect data is obtained, and a second counter that counts a second pulse train related to the position of the transparent plate in the longitudinal direction and outputs a count value when defect data is taken in. And the defect data for multiple scans are accumulated and OR-processed, and the second
At the pulse generation timing of the pulse train of, OR unit for outputting the processed defect data, and compressing the defect data from the OR unit, the continuity in the length direction and the width direction of the compressed defect data, respectively. A defect data acquisition circuit, comprising: a continuous judgment circuit for judging and synthesizing into a defect data block. 2. The defect data acquisition circuit according to claim 1, wherein the continuity determination circuit includes a type of compressed defect data,
A defect data fetch circuit for outputting a start address and an end address in the length direction and a start address and an end address in the width direction of the defect data block.