JPH0870094A - Hybrid ic and its manufacture - Google Patents

Abstract

PURPOSE: To eliminate inner wiring board, realize a thin light device of high density mounting, and improve reliability of circuit connection. CONSTITUTION: A plurality of various kinds of chip circuit components 2 are arranged so as to expose the electrode surfaces on the bottom surface. In this state, the components are molded and fixed with resin 14. Specified wiring conductors 15, 16 are formed on the bottom surface and in the recessed part formed on the upper surface of the mold resin. A semiconductor chip 18 is fixed to the recessed part and sealed with resin 19. Through hole part 17 is cut out and turned into' an outer connection terminal part. Insulating layers 30 are formed on the upper surface and the bottom surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid IC and a method of manufacturing the same, and more particularly to a hybrid IC having a plurality of active elements, circuit elements and integrated circuit elements integrally formed and having a circuit function such as amplification and oscillation, and the same. The present invention relates to a manufacturing method.

[0002]

2. Description of the Related Art A conventional hybrid IC is shown in FIG.
As shown in a partially exploded perspective view (a) of FIG. 4 and a sectional view (b) of an assembled state, a plurality of various electronic components 2 such as semiconductor chips, circuit elements such as resistors and capacitors are mounted on the wiring board 1 by soldering. The mounted wiring board 1 is housed in a shield case composed of a metal bottom box 3 and a lid box 4. In addition, reference numeral 5 in the drawing denotes a connection pin for connecting to another wiring board such as a mother board (parent board). Further, FIG. 15 is a partially exploded perspective view of another conventional example, in which various electronic components 2 are mounted on a box-shaped package 7 made of an insulating material such as ceramic in which the wiring pattern 6 is formed in advance, and the wiring pattern is formed. 6 and the electronic component 2 are connected by soldering or conductive resin, and the semiconductor element is connected by wire bonding or the like. In addition, 8 in the figure is a lid of the box-shaped package 7.

FIG. 16 is a side cross-sectional view of another conventional assembly state, in which a plurality of electronic components 2 are soldered or the like to a wiring board 1 made of alumina or the like on which a wiring pattern 6 is formed in advance. The plurality of electronic components 2 are mounted and molded with resin 9. The terminal electrode 10 for surface mounting the hybrid IC on another wiring board such as a mother board is led out from the outer edge portion of the wiring board 9.

[0004]

However, each of the above-mentioned conventional hybrid ICs has a structure in which electronic components are mounted on a wiring board, and these hybrid ICs are connected to other wirings such as a mother board. When it is mounted on a board, the connecting portion uses a connecting pin or lead wire 5 as shown in FIGS. 14 to 16, or a terminal in which a through hole (not shown) of the wiring board is halved. It is difficult to reduce the thickness of the hybrid IC itself, and there is a limit to the reduction in thickness and weight of electronic equipment using the hybrid IC, and sufficient reliability of the joint cannot be obtained. There was a problem. The present invention solves such conventional drawbacks, achieves thinner and lighter weight than conventional ones, and improves reliability by eliminating the wiring board in the hybrid IC and reducing the number of connection points. A hybrid IC and a method for manufacturing the hybrid IC, which are manufactured at reduced costs by shortening the steps.

[0005]

SUMMARY OF THE INVENTION The hybrid I of the present invention
C is a plurality of chip electronic components, a mold resin in which the plurality of chip electronic components are arranged so that their electrode surfaces are exposed at the bottom surface, and a molding resin in which a concave portion is provided in the central portion of the upper surface, A first wiring conductor is formed on the bottom surface of the molding resin so as to connect the chip electronic component and reaches the peripheral portion, and is formed on the top surface of the molding resin so as to extend from the concave portion to the peripheral portion. A second wiring conductor, a divided through hole formed as a connection terminal for connecting a peripheral portion of the first wiring conductor and a peripheral portion of the second wiring conductor at a predetermined portion and connecting to an external circuit, A semiconductor chip attached to the recess on the upper surface of the mold resin and wire-bonded to the second wiring conductor, and the semiconductor chip and its bonding wire are embedded and sealed. A sealing resin which is characterized in that a provided on the upper surface and the bottom insulating layer, further,
A metal shield layer is provided on the insulating layer.

The method for manufacturing a hybrid IC of the present invention further comprises a step of mounting and mounting a component temporary fixing film having an adhesive applied on one side thereof on a film fixing jig with the adhesive surface facing upward. A step of disposing a plurality of chip electronic components at a predetermined position on the adhesive surface of the component temporary fixing film and temporarily fixing the same, and the film from the component temporary fixing film having the plurality of chip electronic components temporarily fixed to the adhesive. A step of removing the fixing jig, and a concave portion having a volume in which the plurality of chip electronic components are accommodated From a state in which a lower die having a convex portion in the central portion and a flat upper die are injection-molded with a resin, and a plurality of chip electronic components taken out from the die and molded with resin The step of removing the component temporary fixing film, the bottom surface where the electrodes of the plurality of chip electronic components are exposed by removing the component temporary fixing film, and the upper surface having the concave portion formed by the lower die convex portion Forming a predetermined wiring conductor on the substrate and forming a through-hole conductor for connecting predetermined portions of the wiring conductors on the both sides to the peripheral portion, attaching a semiconductor chip to the recess, and sealing the semiconductor chip with a resin. And a step of forming an insulating layer on the upper and lower surfaces, and a step of cutting along a line passing through the central axis of the through hole, further comprising a metal shield from above the insulating layer. It is characterized in that a step of forming a layer is provided.

[0007]

1 to 13 show a hybrid I according to the present invention.
FIG. 10 is a side view or a partial vertical cross-sectional view showing the manufacturing process of the manufacturing method for C, and FIG. 9 is a partial vertical cross-sectional view of the hybrid IC showing the basic configuration of the present invention. First, the manufacturing process will be described with reference to the drawings.

In the side view of FIG. 1, reference numeral 11 denotes a component temporary fixing film coated with an adhesive for temporarily fixing chip electronic components such as a plurality of semiconductor elements and circuit elements, the material of which is polyimide resin, PPS. Resin, etc. Further, a silicon adhesive or the like is used as the adhesive applied to the upper surface thereof. 12 is provided with a film fixing pin 13,
This is a film fixing jig for fixing the component temporary fixing film 11, and a mount for electronic components is prepared.

Next, as shown in the side view of FIG. 2, the transistor,
A plurality of various electronic components 2 such as a semiconductor chip such as a diode, a chip resistor, and a chip capacitor are arranged and adhesively fixed. At this time, the electrode surface of the electronic component 2 is arranged so as to be bonded to the component temporary fixing film 11 side.

Next, as shown in the side view of FIG. 3, the film fixing jig 12 is removed from the component temporary fixing film 11 on which the electronic component 2 is mounted.

Then, as shown in FIG. 4, a component temporary fixing film 11 to which the electronic component 2 is temporarily fixed is arranged between the lower mold 21 and the upper mold 22 which form the molding die 20. At this time, the electronic component 2 is arranged so that the surface on which the electronic component 2 is temporarily fixed is faced down in the space portion 23 of the lower mold 21, and the plate-shaped upper mold 22 is placed on the component temporary fixing film 11 side. Is placed and sandwiched so as to come into contact with the back surface of the film 11 for temporarily fixing the component. Reference numeral 24 is a positioning pin provided in the lower mold 21, which penetrates the positioning hole of the film for temporarily fixing the component and fits into the pin fitting hole 25 of the upper mold 22. Also,
A resin injection port 26 is provided on the side wall surface of the lower mold 21, and a stepped convex portion is provided in the central portion of the bottom surface of the concave portion.

Next, as shown in the sectional view of FIG. 5, the molding die 20 is held with the upper die 22 and the lower die 21 in close contact with each other.
A resin 14 such as an epoxy resin is injected from the resin injection port 26, and the electronic component 2 is molded and fixed by pressure molding in a predetermined arrangement state.

Next, the electronic component 2 and the component temporary fixing film 11 molded by the resin 14 are taken out from the molding die 20, and the component is attached from the lower surface which is the electrode surface of the electronic component 2 as shown in the sectional view of FIG. The temporary fixing film 11 is peeled off. Therefore, the electrode surface of the electronic component 2 is exposed at the bottom surface.

FIG. 7 is a sectional view showing a state in which the wiring conductors are formed on the upper surface and the lower surface in the wiring conductor forming step. The wiring conductor 15 on the lower surface is a wiring conductor that connects the exposed electrode surface of the electronic component 2, and the wiring conductor 16 on the upper surface is provided from the top surface to the bottom surface of the stepped recessed portion in the central portion. It is a wiring conductor for connection of an IC bare chip that is attached to the bottom surface in a later step. The inclination angle from the top surface to the step of the recess and the inclination angle from the step to the bottom are set to about 45 ° so that the wiring conductor can be continuously formed. This wiring conductor is formed by means such as vapor deposition, plating, metal foil sticking, and printing. Reference numeral 17 denotes a through hole, which connects the wiring conductor 16 on the upper surface and the wiring conductor 15 on the lower surface, and is cut in the direction of the central axis thereof in the final step to become an external connection terminal.

FIG. 8 is a plan view (A), a sectional view (B) and a bottom view (C) showing a state in which, for example, an IC bare chip 18 is attached to a concave portion on the upper surface and wire bonding is performed in the semiconductor bare chip assembling process. . The height of the step of the upper surface recess from the bottom surface is set to be substantially equal to the upper surface of the IC bare chip 18, which facilitates wire bonding. The hatched portions in the plan view (A) and the bottom view (C) are the wiring conductors 16 and 15.

FIG. 9 shows a potting (sealing) process in which the IC
The bare chip 18 is replaced with a thermosetting resin 19 such as an epoxy resin.
It is sectional drawing which shows the state filled with. The depth of the upper surface concave portion is set so that the bonding wire is sufficiently filled in this state and does not rise to the upper surface.

FIG. 10 is a sectional view showing a state in which the insulating layer 30 is provided on the upper surface and the lower surface in the insulating layer forming step. An epoxy resin is used as this insulating layer.

FIG. 11 shows a shield forming step in which the insulating layer 30 is formed.
It is sectional drawing which shows the state in which the metal shield layer 31 was provided by the arc spraying from above.

In the embodiments shown in FIGS. 1 to 11 above,
Although the manufacturing process of one hybrid IC is schematically shown, when actually manufacturing, a method of assembling and molding a plurality of hybrid ICs of the same type at the same time and then cutting and separating by a wire saw dicing method or a blade dicing method is adopted. To be done. FIG. 12 is a plan view (A) and a bottom view (B) showing a state in the middle of a process in the case of simultaneously assembling and molding three hybrid ICs. 32 is a positioning hole.

After the step shown in FIG. 10 or FIG. 11, each hybrid IC is cut along a line passing through the center of the through hole 17 in the peripheral portion. FIG. 13 shows a plan view of the finished product after cutting. In the case where the circuit signal may affect the other such as in the oscillation circuit or in the case where the circuit signal may be affected by the other such as the low noise amplifier circuit, it is preferable to complete the shield forming process of FIG. For example, if the present invention is applied to a frequency synthesizer using a PLL,
An independent small-sized frequency synthesizer can be realized by mounting the PLL-IC chip in the concave portion on the upper surface and molding the circuit element such as the voltage controlled oscillator (VCO).

[0021]

As described in detail above, the hybrid IC according to the present invention does not have a wiring board inside and various electronic components are not mounted on the wiring board as in the conventional case. As described above, since it is not necessary to connect the wiring board forming a part of the package by soldering or the like, high-density mounting can be achieved and the connection reliability can be improved. Further, as described above, the wiring board forming the package of the hybrid IC can be eliminated, which contributes to reduction in thickness and weight, which contributes to reduction in size and weight of the electronic device. It is a thing.

[Brief description of drawings]

FIG. 1 is a side view of an embodiment of a part of a manufacturing process of a hybrid IC of the present invention.

FIG. 2 is a side view of an embodiment of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 3 is a side view of an embodiment of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 4 is a partial vertical cross-sectional view of an embodiment of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 5 is a partial vertical sectional view of an embodiment of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 6 is a partial vertical cross-sectional view of an embodiment of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 7 is a partial vertical cross-sectional view of an embodiment of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 8 is a plan view, a sectional view, and a bottom view of a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 9 is a cross-sectional view showing a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 10 is a sectional view showing a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 11 is a cross-sectional view showing a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 12 is a plan view and a bottom view showing a part of the manufacturing process of the hybrid IC of the present invention.

FIG. 13 is a plan view of a completed product of the manufacturing process of the hybrid IC of the present invention.

FIG. 14 is a structural diagram of a conventional hybrid IC.

FIG. 15 is a partially exploded perspective view of another conventional hybrid IC.

FIG. 16 is a vertical cross-sectional view of another conventional hybrid IC.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Electronic component 3 Bottom box 4 Lid box 5 Lead wire 6 Wiring pattern 7 Box-shaped package 8 Lid of box-shaped package 9 Resin 10 Terminal electrode 11 Film for temporarily fixing parts 12 Film fixing jig 13 For film fixing Pin 14 Resin 15, 16 Wiring conductor 17 Through hole 18 Semiconductor bare chip 19 Potting resin 20 Mold 21 Lower mold 22 Upper mold 23 Space by molding mold 24 Positioning pin 25 Fitting hole 26 Resin injection port 30 Insulating layer 31 Shield layer 32 Positioning hole

Front page continuation (72) Inventor Toru Sasayama 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Inc.

Claims (4)

[Claims] 1. A plurality of chip electronic components, and a molding resin in which the plurality of chip electronic components are molded such that the electrode surfaces thereof are exposed at the bottom surface and a recess is provided in the central portion of the upper surface. A first wiring conductor formed on the bottom surface of the mold resin so as to connect the chip electronic component and reach the peripheral portion, and on the top surface of the mold resin so as to extend from the concave portion to the peripheral portion. A divided through hole formed as a connection terminal for connecting the formed second wiring conductor and the peripheral portion of the first wiring conductor to the peripheral portion of the second wiring conductor at a predetermined portion. A semiconductor chip attached to the recess on the upper surface of the mold resin and connected by wire bonding to the second wiring conductor; the semiconductor chip and its bonding wire; A hybrid IC including a sealing resin in which a core is buried and sealed, and an insulating layer provided on a top surface and a bottom surface. 2. The hybrid IC according to claim 1, wherein a metal shield layer is provided on the insulating layer. 3. A step of placing and mounting a component temporary fixing film, one side of which is coated with an adhesive, on a film fixing jig with the adhesive surface facing upward, A step of disposing a plurality of chip electronic components at a predetermined position and temporarily adhering them, and a step of removing the film fixing jig from a component provisional fixing film in which the plurality of chip electronic components are adhering and temporarily fixed, A lower mold having a concave portion having a volume for accommodating the plurality of chip electronic components and a convex portion in the central portion of the concave portion, with the side on which the plurality of chip child components are temporarily fixed to the component temporary fixing film being bonded downward. And a step of injection-molding with a resin, which is fitted into a molding die composed of a flat upper die, and a step of removing the component temporary fixing film from a state in which a plurality of chip electronic components taken out from the molding die are resin-molded. , While forming a predetermined wiring conductor on the bottom surface where the electrodes of the plurality of chip electronic components are exposed by removing the component temporary fixing film and on the top surface having the concave portion formed by the lower die convex portion, A through hole conductor for connecting predetermined portions of the wiring conductors on both sides to a portion, a step of attaching a semiconductor chip to the recess, a step of resin-sealing the semiconductor chip, and an insulating layer on the upper and lower surfaces. And a step of cutting with a line passing through the central axis of the through hole. 4. The method of manufacturing a hybrid IC according to claim 3, further comprising a step of forming a metal shield layer on the insulating layer.